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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:48:35.8527 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36e326a4-e25f-4626-1833-08dce682ec02 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7688 Content-Type: text/plain; charset="utf-8" Definition of these macros are very simple and they are used at only one place. Get rid of unnecessary redirection. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e91970b01d62..347353b9eb70 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -28,10 +28,6 @@ static u32 ibs_caps; #include #include =20 -#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT) -#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT - - /* * IBS states: * @@ -670,7 +666,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, - .config_mask =3D IBS_FETCH_CONFIG_MASK, + .config_mask =3D IBS_FETCH_MAX_CNT | IBS_FETCH_RAND_EN, .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, .valid_mask =3D IBS_FETCH_VAL, @@ -694,7 +690,7 @@ static struct perf_ibs perf_ibs_op =3D { .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, - .config_mask =3D IBS_OP_CONFIG_MASK, + .config_mask =3D IBS_OP_MAX_CNT, .cnt_mask =3D IBS_OP_MAX_CNT | IBS_OP_CUR_CNT | IBS_OP_CUR_CNT_RAND, .enable_mask =3D IBS_OP_ENABLE, --=20 2.46.2 From nobody Thu Nov 28 00:50:09 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2044.outbound.protection.outlook.com [40.107.94.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C25745F2; 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Sun, 6 Oct 2024 22:48:35 -0500 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH 2/8] perf/amd/ibs: Remove pointless sample period check Date: Mon, 7 Oct 2024 03:48:04 +0000 Message-ID: <20241007034810.754-3-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241007034810.754-1-ravi.bangoria@amd.com> References: <20241007034810.754-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|SJ2PR12MB9241:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f946cd0-eb8e-47c8-2c78-08dce682f01b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:48:42.7436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f946cd0-eb8e-47c8-2c78-08dce682f01b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9241 Content-Type: text/plain; charset="utf-8" Valid perf event sample period value for IBS PMUs (Fetch and Op both) is limited to multiple of 0x10. perf_ibs_init() has this check: if (!event->attr.sample_freq && hwc->sample_period & 0x0f) return -EINVAL; But it's broken since hwc->sample_period will always be 0 when event->attr.sample_freq is 0 (irrespective of event->attr.freq value.) One option to fix this is to change the condition: - if (!event->attr.sample_freq && hwc->sample_period & 0x0f) + if (!event->attr.freq && hwc->sample_period & 0x0f) However, that will break all userspace tools which have been using IBS event with sample_period not multiple of 0x10. Another option is to remove the condition altogether and mask lower nibble _silently_, same as what current code is inadvertently doing. I'm preferring this approach as it keeps the existing behavior. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 347353b9eb70..6b55a8520166 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -294,13 +294,8 @@ static int perf_ibs_init(struct perf_event *event) if (config & perf_ibs->cnt_mask) /* raw max_cnt may not be set */ return -EINVAL; - if (!event->attr.sample_freq && hwc->sample_period & 0x0f) - /* - * lower 4 bits can not be set in ibs max cnt, - * but allowing it in case we adjust the - * sample period to set a frequency. - */ - return -EINVAL; + + /* Silently mask off lower nibble. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:48:47.6719 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66cafebc-100c-4805-2c94-08dce682f30b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8188 Content-Type: text/plain; charset="utf-8" Instead of using standard perf_event_attr->freq=3D0 and ->sample_period fields, IBS event in 'sample period mode' can also be opened by setting period value directly in perf_event_attr->config in a MaxCnt bit-field format. IBS OP MaxCnt bits are defined as: (high bits) IbsOpCtl[26:20] =3D IbsOpMaxCnt[26:20] (low bits) IbsOpCtl[15:0] =3D IbsOpMaxCnt[19:4] Perf event sample period can be derived from MaxCnt bits as: sample_period =3D (high bits) | ((low_bits) << 4); However, current code just masks MaxCnt bits and shifts all of them, including high bits, which is incorrect. Fix it. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 6b55a8520166..79422d2e301b 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -268,7 +268,7 @@ static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; struct perf_ibs *perf_ibs; - u64 max_cnt, config; + u64 config; int ret; =20 perf_ibs =3D get_ibs_pmu(event->attr.type); @@ -300,10 +300,19 @@ static int perf_ibs_init(struct perf_event *event) if (!hwc->sample_period) hwc->sample_period =3D 0x10; } else { - max_cnt =3D config & perf_ibs->cnt_mask; + u64 period =3D 0; + + if (perf_ibs =3D=3D &perf_ibs_op) { + period =3D (config & IBS_OP_MAX_CNT) << 4; + if (ibs_caps & IBS_CAPS_OPCNTEXT) + period |=3D config & IBS_OP_MAX_CNT_EXT_MASK; + } else { + period =3D (config & IBS_FETCH_MAX_CNT) << 4; + } + config &=3D ~perf_ibs->cnt_mask; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:49:08.2032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8697058-0633-486b-fff4-08dce682ff47 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7577 Content-Type: text/plain; charset="utf-8" IBS Op uses two counters: MaxCnt and CurCnt. MaxCnt is programmed with the desired sample period. IBS hw generates sample when CurCnt reaches to MaxCnt. The size of these counter used to be 20 bits but later they were extended to 27 bits. The 7 bit extension is indicated by CPUID Fn8000_001B_EAX[6 / OpCntExt]. perf_ibs->cnt_mask variable contains bit masks for MaxCnt and CurCnt. But IBS driver does not set upper 7 bits of CurCnt in cnt_mask even when OpCntExt CPUID bit is set. Fix this. IBS driver uses cnt_mask[CurCnt] bits only while disabling an event. Fortunately, CurCnt bits are not read from MSR while re-enabling the event, instead MaxCnt is programmed with desired period and CurCnt is set to 0. Hence, we did not see any issues so far. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 3 ++- arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 79422d2e301b..152f9116af1e 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1222,7 +1222,8 @@ static __init int perf_ibs_op_init(void) if (ibs_caps & IBS_CAPS_OPCNTEXT) { perf_ibs_op.max_period |=3D IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.config_mask |=3D IBS_OP_MAX_CNT_EXT_MASK; - perf_ibs_op.cnt_mask |=3D IBS_OP_MAX_CNT_EXT_MASK; + perf_ibs_op.cnt_mask |=3D (IBS_OP_MAX_CNT_EXT_MASK | + IBS_OP_CUR_CNT_EXT_MASK); } =20 if (ibs_caps & IBS_CAPS_ZEN4) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 91b73571412f..72f1bcb0fa31 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -498,6 +498,7 @@ struct pebs_xmm { */ #define IBS_OP_CUR_CNT (0xFFF80ULL<<32) #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) +#define IBS_OP_CUR_CNT_EXT_MASK (0x7FULL<<52) #define IBS_OP_CNT_CTL (1ULL<<19) #define IBS_OP_VAL (1ULL<<18) #define IBS_OP_ENABLE (1ULL<<17) --=20 2.46.2 From nobody Thu Nov 28 00:50:09 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2049.outbound.protection.outlook.com [40.107.243.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C1B861FED; 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Sun, 6 Oct 2024 22:49:07 -0500 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH 5/8] perf/amd/ibs: Don't allow freq mode event creation through ->config interface Date: Mon, 7 Oct 2024 03:48:07 +0000 Message-ID: <20241007034810.754-6-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241007034810.754-1-ravi.bangoria@amd.com> References: <20241007034810.754-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529F:EE_|SA1PR12MB8641:EE_ X-MS-Office365-Filtering-Correlation-Id: 0780a788-329f-43a1-5928-08dce68302b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:49:13.9792 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0780a788-329f-43a1-5928-08dce68302b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8641 Content-Type: text/plain; charset="utf-8" Most perf_event_attr->config bits directly maps to IBS_{FETCH|OP}_CTL MSR. Since the sample period is programmed in these control registers, IBS PMU driver allows opening an IBS event by setting sample period value directly in perf_event_attr->config instead of using explicit perf_event_attr->sample_period interface. However, this logic is not applicable for freq mode events since the semantics of control register fields are applicable only to fixed sample period whereas the freq mode event adjusts sample period after each and every sample. Currently, IBS driver (unintentionally) allows creating freq mode event via ->config interface, which is semantically wrong as well as detrimental because it can be misused to bypass perf_event_max_sample_rate checks. Don't allow freq mode event creation through perf_event_attr->config interface. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 152f9116af1e..368ed839b612 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -302,6 +302,9 @@ static int perf_ibs_init(struct perf_event *event) } else { u64 period =3D 0; =20 + if (event->attr.freq) + return -EINVAL; + if (perf_ibs =3D=3D &perf_ibs_op) { period =3D (config & IBS_OP_MAX_CNT) << 4; if (ibs_caps & IBS_CAPS_OPCNTEXT) --=20 2.46.2 From nobody Thu Nov 28 00:50:09 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F3E861FED; Mon, 7 Oct 2024 03:49:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.40 ARC-Seal: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:49:19.7511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c54b30b0-0370-41cd-7731-08dce683062c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5732 Content-Type: text/plain; charset="utf-8" 0x10 is the minimum sample period for IBS Fetch and 0x90 for IBS Op. Current IBS pmu driver uses 0x10 for both the pmus, which is incorrect. Fix it by adding pmu specific minimum period values in struct perf_ibs. Also, bail out opening a 'sample period mode' event if the user requested sample period is less than pmu supported minimum value. For a 'freq mode' event, start calibrating sample period from pmu specific minimum period. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 368ed839b612..e7522ba45a7e 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -83,6 +83,7 @@ struct perf_ibs { u64 cnt_mask; u64 enable_mask; u64 valid_mask; + u16 min_period; u64 max_period; unsigned long offset_mask[1]; int offset_max; @@ -295,10 +296,14 @@ static int perf_ibs_init(struct perf_event *event) /* raw max_cnt may not be set */ return -EINVAL; =20 - /* Silently mask off lower nibble. IBS hw mandates it. */ - hwc->sample_period &=3D ~0x0FULL; - if (!hwc->sample_period) - hwc->sample_period =3D 0x10; + if (event->attr.freq) { + hwc->sample_period =3D perf_ibs->min_period; + } else { + /* Silently mask off lower nibble. IBS hw mandates it. */ + hwc->sample_period &=3D ~0x0FULL; + if (hwc->sample_period < perf_ibs->min_period) + return -EINVAL; + } } else { u64 period =3D 0; =20 @@ -316,10 +321,10 @@ static int perf_ibs_init(struct perf_event *event) config &=3D ~perf_ibs->cnt_mask; event->attr.sample_period =3D period; hwc->sample_period =3D period; - } =20 - if (!hwc->sample_period) - return -EINVAL; + if (hwc->sample_period < perf_ibs->min_period) + return -EINVAL; + } =20 /* * If we modify hwc->sample_period, we also need to update @@ -340,7 +345,8 @@ static int perf_ibs_set_period(struct perf_ibs *perf_ib= s, int overflow; =20 /* ignore lower 4 bits in min count: */ - overflow =3D perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, perio= d); + overflow =3D perf_event_set_period(hwc, perf_ibs->min_period, + perf_ibs->max_period, period); local64_set(&hwc->prev_count, 0); =20 return overflow; @@ -677,6 +683,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .cnt_mask =3D IBS_FETCH_MAX_CNT, .enable_mask =3D IBS_FETCH_ENABLE, .valid_mask =3D IBS_FETCH_VAL, + .min_period =3D 0x10, .max_period =3D IBS_FETCH_MAX_CNT << 4, .offset_mask =3D { MSR_AMD64_IBSFETCH_REG_MASK }, .offset_max =3D MSR_AMD64_IBSFETCH_REG_COUNT, @@ -702,6 +709,7 @@ static struct perf_ibs perf_ibs_op =3D { IBS_OP_CUR_CNT_RAND, .enable_mask =3D IBS_OP_ENABLE, .valid_mask =3D IBS_OP_VAL, + .min_period =3D 0x90, .max_period =3D IBS_OP_MAX_CNT << 4, .offset_mask =3D { MSR_AMD64_IBSOP_REG_MASK }, .offset_max =3D MSR_AMD64_IBSOP_REG_COUNT, --=20 2.46.2 From nobody Thu Nov 28 00:50:09 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2054.outbound.protection.outlook.com [40.107.223.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2F52487A5; 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Sun, 6 Oct 2024 22:49:19 -0500 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH 7/8] perf/amd/ibs: Add ->check_period() callback Date: Mon, 7 Oct 2024 03:48:09 +0000 Message-ID: <20241007034810.754-8-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241007034810.754-1-ravi.bangoria@amd.com> References: <20241007034810.754-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|IA1PR12MB7568:EE_ X-MS-Office365-Filtering-Correlation-Id: d88d0425-f8d3-4fb1-b51a-08dce6830998 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:49:25.5093 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d88d0425-f8d3-4fb1-b51a-08dce6830998 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7568 Content-Type: text/plain; charset="utf-8" IBS Fetch and IBS Op pmus have constraints on sample period. The sample period is verified at the time of opening an event but not at the ioctl() interface. Hence, a user can open an event with valid period but change it later with ioctl(). Add a ->check_period() callback to verify the period provided at ioctl() is also valid. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e7522ba45a7e..33728ed6d7a6 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -551,6 +551,28 @@ static void perf_ibs_del(struct perf_event *event, int= flags) =20 static void perf_ibs_read(struct perf_event *event) { } =20 +static int perf_ibs_check_period(struct perf_event *event, u64 value) +{ + struct perf_ibs *perf_ibs; + u64 low_nibble; + + if (event->attr.freq) + return 0; + + perf_ibs =3D container_of(event->pmu, struct perf_ibs, pmu); + low_nibble =3D value & 0xFULL; + + /* + * This contradicts with perf_ibs_init() which allows sample period + * with lower nibble bits set but silently masks them off. Whereas + * this returns error. + */ + if (low_nibble || value < perf_ibs->min_period) + return -EINVAL; + + return 0; +} + /* * We need to initialize with empty group if all attributes in the * group are dynamic. @@ -676,6 +698,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, + .check_period =3D perf_ibs_check_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, @@ -701,6 +724,7 @@ static struct perf_ibs perf_ibs_op =3D { .start =3D perf_ibs_start, .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, + .check_period =3D perf_ibs_check_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, --=20 2.46.2 From nobody Thu Nov 28 00:50:09 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2055.outbound.protection.outlook.com [40.107.92.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 604451494DA; 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Sun, 6 Oct 2024 22:49:25 -0500 From: Ravi Bangoria To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH 8/8] perf/core: Introduce pmu->adjust_period() callback Date: Mon, 7 Oct 2024 03:48:10 +0000 Message-ID: <20241007034810.754-9-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241007034810.754-1-ravi.bangoria@amd.com> References: <20241007034810.754-1-ravi.bangoria@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|LV8PR12MB9407:EE_ X-MS-Office365-Filtering-Correlation-Id: 8030c053-e09c-4197-2864-08dce6831374 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 03:49:42.0470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8030c053-e09c-4197-2864-08dce6831374 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9407 Content-Type: text/plain; charset="utf-8" Many hardware pmus have constraints about sample period. For ex, minimum supported sample period for IBS Op pmu is 0x90, the sample period must be multiple of 0x10 for IBS Fetch and IBS Op. Add an optional callback adjust_period() to struct pmu to allow pmu specific drivers to adjust sample period calculated by generic code. This will ensure the sample_period value will always be valid and no additional code is required in PMU specific drivers to re-adjust the period. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim --- arch/x86/events/amd/ibs.c | 11 +++++++++++ include/linux/perf_event.h | 5 +++++ kernel/events/core.c | 12 ++++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 33728ed6d7a6..0d1db2fffc5b 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -573,6 +573,15 @@ static int perf_ibs_check_period(struct perf_event *ev= ent, u64 value) return 0; } =20 +static u64 perf_ibs_adjust_period(struct perf_event *event, u64 period) +{ + struct perf_ibs *perf_ibs =3D container_of(event->pmu, struct perf_ibs, p= mu); + + period &=3D ~0xFULL; + + return period < perf_ibs->min_period ? perf_ibs->min_period : period; +} + /* * We need to initialize with empty group if all attributes in the * group are dynamic. @@ -699,6 +708,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, .check_period =3D perf_ibs_check_period, + .adjust_period =3D perf_ibs_adjust_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSFETCHCTL, @@ -725,6 +735,7 @@ static struct perf_ibs perf_ibs_op =3D { .stop =3D perf_ibs_stop, .read =3D perf_ibs_read, .check_period =3D perf_ibs_check_period, + .adjust_period =3D perf_ibs_adjust_period, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }, .msr =3D MSR_AMD64_IBSOPCTL, diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 1a8942277dda..eca8581d8e5d 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -540,6 +540,11 @@ struct pmu { * Check period value for PERF_EVENT_IOC_PERIOD ioctl. */ int (*check_period) (struct perf_event *event, u64 value); /* optional */ + + /* + * Adjust period value according to pmu constraints. + */ + u64 (*adjust_period) (struct perf_event *event, u64 period); /* optional= */ }; =20 enum perf_addr_filter_action_t { diff --git a/kernel/events/core.c b/kernel/events/core.c index 8a6c6bbcd658..f3de683ec716 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4100,9 +4100,9 @@ static void perf_adjust_period(struct perf_event *eve= nt, u64 nsec, u64 count, bo if (!sample_period) sample_period =3D 1; =20 - hwc->sample_period =3D sample_period; + hwc->sample_period =3D event->pmu->adjust_period(event, sample_period); =20 - if (local64_read(&hwc->period_left) > 8*sample_period) { + if (local64_read(&hwc->period_left) > 8*hwc->sample_period) { if (disable) event->pmu->stop(event, PERF_EF_UPDATE); =20 @@ -11363,6 +11363,11 @@ static int perf_event_nop_int(struct perf_event *e= vent, u64 value) return 0; } =20 +static u64 perf_pmu_nop_adjust_period(struct perf_event *event, u64 period) +{ + return period; +} + static DEFINE_PER_CPU(unsigned int, nop_txn_flags); =20 static void perf_pmu_start_txn(struct pmu *pmu, unsigned int flags) @@ -11641,6 +11646,9 @@ int perf_pmu_register(struct pmu *pmu, const char *= name, int type) if (!pmu->check_period) pmu->check_period =3D perf_event_nop_int; =20 + if (!pmu->adjust_period) + pmu->adjust_period =3D perf_pmu_nop_adjust_period; + if (!pmu->event_idx) pmu->event_idx =3D perf_event_idx_default; =20 --=20 2.46.2