From nobody Wed Nov 27 22:27:37 2024 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F9B41DDA3B for ; Mon, 7 Oct 2024 18:23:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728325387; cv=none; b=KzlQnQe/1uhGg9UdymxDI0IP60SVkRVJ7J02msZBpUiXqs4KUb1WeOCAocd7DAyrfF66sH3LXIpXF0QJXCNhqnMw1DnST4Awbx7VU7iAQtYDWaGISJj4QWPvSpWzbbpQsJKt6n9SC58h1vBbxdtdTxv1WHcP1z2H7BrL38a8YwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728325387; c=relaxed/simple; bh=9i5n6TqCj0k1ThHHBY3k/t7afoVnNGJdMEiA0JI+g9M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nA+skEMgpDoAz98FIvVqpNbL5aXyjP3RWtLkjE8UGEwiYXwkla/KazjnA+gxjKqsJh1EZA8sNyUbUCQMKyv1gwUi/d5yStXLzeP47AgDugwHrDkipCDRd830t+ENsVWxgy1g4IPaOwD5d++iA6GOnsj7v9ZfamAWAvL2pHOvCDw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PsWncHAy; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PsWncHAy" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-5c89f3e8a74so6647990a12.0 for ; Mon, 07 Oct 2024 11:23:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728325382; x=1728930182; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KboijkeIl0WHBQ71mVXnbHN7cxUj6HXnHwgMJMxu0d0=; b=PsWncHAy78X9kYwn9ZRbo+o5tg6U1dGAsWx7cY3LkXVo+0tqR2Qq2u3H4liRQgR3PX kONXEfoRPomZXlpdstHCCQ++GKrjgqOY+fYh39vSNy9RXA55altD14XGGg4RT7Ge15Qu pWuHtSlJVdQj4XqltSZ34BiJVnO8nfDA9wkxD4BR7NcW0i+vhbSG6fEa4p1lrfDNf1Wr Ho8afsJgk5x02GL9jQ/+U657jwgz3SVkRad3bq4wnoqlj4+UlgVxj0wZB6rqxL/5edEu YR19CoOffG82b7tjBvME5txEbHXGVMIRgLyo+qTVrr98zQi+SS1NBBlSB1hMJpdYVUJc Ppyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728325382; x=1728930182; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KboijkeIl0WHBQ71mVXnbHN7cxUj6HXnHwgMJMxu0d0=; b=MiB/Sul5mb1shqxGzXxeS6AgjavoOpe6So1Z+U6doDApUMPSyb65nZq7N+iLXUbP+k cCvZxC9I6pVGVEfWwLfMIO2fC26FdCt8peF38DU/OfvtLdHA07jZa6zRRhFhi6enW44o ZG68jOoOLrDZW9S6PdhuCWveB33teWXKoMWjncwVmu7sGcXTk4oxFXF+fh9cPFzharL3 FueLd6vo2PuaRrlQrL+rBvPdaP/Eu9mnIPvJj6deMrxRSBYFf2l4lxnu+lvWtZrUyADU 8EV51k3+4B7oFVjKAQAM987M6/P6MiWrxru1rHbC3qlSwIoDKlSUOVRSW0XmxsdlTg7i luRQ== X-Forwarded-Encrypted: i=1; AJvYcCVi2LNz8SmpCTMUQe+tOI91ztUfl3HeWJgx4foKHQ6Ac6JXn/5L+Z49CCCLLEi4+XqOJHSQ0q42MVlE6N8=@vger.kernel.org X-Gm-Message-State: AOJu0Yy1MipHMh675mIf17kugXxx1jXSImjtFim9ZEGoc8c+7jNkrrIx zLtiya1J+zMk6daHpy6+IwGGmr/SX6B64ln4WyQ1W+CsCNWGXmIk/wM5MsXiNZg= X-Google-Smtp-Source: AGHT+IG9ePfC+8NUvoRvs49MolyA7tHJU076KVG84tGKTi/fiABzVTM7dNZXMWu0De7eDcpHggXOlg== X-Received: by 2002:a05:6402:518d:b0:5c8:9515:cc1 with SMTP id 4fb4d7f45d1cf-5c8d2e1e315mr10086236a12.7.1728325382059; Mon, 07 Oct 2024 11:23:02 -0700 (PDT) Received: from [127.0.0.2] ([2a02:2454:ff21:ef40:4109:b8c2:873b:4a28]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c8e05eb34csm3452963a12.59.2024.10.07.11.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 11:23:01 -0700 (PDT) From: Stephan Gerhold Date: Mon, 07 Oct 2024 20:22:25 +0200 Subject: [PATCH 1/3] arm64: dts: qcom: x1e80100: Add QUP power domains and OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241007-x1e80100-pwrseq-qcp-v1-1-f7166510ab17@linaro.org> References: <20241007-x1e80100-pwrseq-qcp-v1-0-f7166510ab17@linaro.org> In-Reply-To: <20241007-x1e80100-pwrseq-qcp-v1-0-f7166510ab17@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Bartosz Golaszewski , Srinivas Kandagatla X-Mailer: b4 0.13.0 Add the power domains and OPP tables to all the QUP-related UART/I2C/SPI nodes to ensure that we vote for the necessary performance states. Similar to sm8350.dtsi, the OPPs depend on the QUP instance. The first two instances in each geniqup group need &rpmhpd_opp_svs starting at 120MHz, the others already starting at 100MHz. I2C always runs at a lower clock frequency and therefore uses a fixed vote. Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Tested-by: Johan Hovold --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 178 +++++++++++++++++++++++++++++= ++++ 1 file changed, 178 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 0e6802c1d2d8..06d27c65dc11 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -679,6 +679,34 @@ smem_mem: smem@ffe00000 { }; }; =20 + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible =3D "operating-points-v2"; + + opp-75000000 { + opp-hz =3D /bits/ 64 <75000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + }; + smp2p-adsp { compatible =3D "qcom,smp2p"; =20 @@ -833,6 +861,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -866,6 +897,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -899,6 +933,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -932,6 +969,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -965,6 +1005,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -998,6 +1041,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1031,6 +1077,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1064,6 +1113,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1097,6 +1149,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1130,6 +1185,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1163,6 +1221,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1196,6 +1257,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1226,6 +1290,9 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + pinctrl-0 =3D <&qup_uart21_default>; pinctrl-names =3D "default"; =20 @@ -1251,6 +1318,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_I2C>, <&gpi_dma2 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1284,6 +1354,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_SPI>, <&gpi_dma2 1 6 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1317,6 +1390,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1350,6 +1426,9 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1427,6 +1506,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1460,6 +1542,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1493,6 +1578,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1526,6 +1614,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1559,6 +1650,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1592,6 +1686,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1625,6 +1722,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1658,6 +1758,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1691,6 +1794,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1724,6 +1830,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1757,6 +1866,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1790,6 +1902,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1823,6 +1938,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1856,6 +1974,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1889,6 +2010,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -1922,6 +2046,9 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -1998,6 +2125,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2031,6 +2161,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2064,6 +2197,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2097,6 +2233,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2130,6 +2269,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2160,6 +2302,9 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + pinctrl-0 =3D <&qup_uart2_default>; pinctrl-names =3D "default"; =20 @@ -2185,6 +2330,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2218,6 +2366,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2251,6 +2402,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2284,6 +2438,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2317,6 +2474,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2350,6 +2510,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2383,6 +2546,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2416,6 +2582,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2449,6 +2618,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names =3D "tx", @@ -2482,6 +2654,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names =3D "tx", @@ -2515,6 +2690,9 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; =20 + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names =3D "tx", --=20 2.46.0 From nobody Wed Nov 27 22:27:37 2024 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EFE81DDC26 for ; Mon, 7 Oct 2024 18:23:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728325386; cv=none; b=X5uB7Kl+XRqolwBVsBfnOAmeq36IQZVtxDd2i2qXmaSc3fIR2TqQvS5m9Or9c3uvfShvdhekThOf6VQF8QmC5lSUuk4z3b6YvbaBD1XkE/Zc/AEKXdjVCXshiVTGB7Jc/DQSxIG8tgJBzOmHbPdAwVcJNqgtlYCAp3zgf7dtYwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728325386; c=relaxed/simple; bh=U3MoflWSS4X7ojpD9s6AHdoJKHKG92yadksJttRFSWc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bkx1U3XxhdJD9XZFavcwhVgPytlohD1zDb8EjhEMgXM5T8a2cjGas16ATAKJmgZU/e0AZYjggBQPqs8JXNQF5YFyF69m2v8Y4mLl1hclG3Ic5GVMhG65iek5aqoW0Xd8VYqD0Z/pZXSiuDwL64XJAvs+grgf5wCMWV4AwVtUlPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hwKNY+Mk; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hwKNY+Mk" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-5c87ab540b3so10285970a12.1 for ; Mon, 07 Oct 2024 11:23:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728325383; x=1728930183; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TV6+Hn2cOZip0zLKLF+j4ubTHiIZhcY3cY83jYd7n5I=; b=hwKNY+Mkz+mJvfO68KHlcbfKsOO4xsz2gJ95BPmCquQ85Q+r8go2F10w/4kWclvBdc 46ondUzPmW7N2PweDZc/CISwmowfYVuetBARq9n9vQm44uMlWuRuvoxXTiqPq2FMWzDs 5HVRci7y8AB5ElFwtyfovN6r0Oc5UQRVvxkVDyuHdETW8QrDIkMX1YKpMCdqgGyMeAGj rPK2D22vFprd3v0TtlvsqHPCpMklOmx71Wp8qzwr1Pbgn0bA/f9g14/HA/zjHYZ26qjf 1DGM3GmZH0gXBpAVIUaifBosBRAXG+b0gzLKxki1L1sILU76MOmCWOhRyPxtlrzctrNL z+RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728325383; x=1728930183; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TV6+Hn2cOZip0zLKLF+j4ubTHiIZhcY3cY83jYd7n5I=; b=lywvj4wo/9I1aotoAP2Pg2KwtTQtW6wOcyzcsRaqpEjIrrAQ4kLAL13Hv+8fo1EpAh sQ+fzsbtZWLXH7FnIXXgvcecGtrVhk1nFmbGmZb3VUc2T05BuoHedTe+n2KecZ8UZUb7 pxtth3dRzH9qU8Kx0HoU7o9bvhMG1DtboULRwvJq0q8IoqF27VYWSKOAZ9UGw5B3lX6E EQN3z1K+6XfimerKNlrPX5uD+sph5GcVS82fQ/BF7myogaykx6sK0GUbhj+Pbx/pwh76 /adrCd/YE4yUJZi8sPPzUGEtF7dO6/WuKh/sCPIPfEpaEzJH0hEAR+gB6eDqoKb3W/wZ 9LCA== X-Forwarded-Encrypted: i=1; AJvYcCX1VpZ1IeWQ+mhqM6/X7WbD5dMOtVus7DWDB5LSnMMnG5lMu/nYvIlpIYMZ0puNVaP/He7sxJKpE73JW2I=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6CVwd5+3prVSTCPUSvlsV9GeEb8KublwvGRpbkK3HZludQg4x JCxAx0lWcDfz5SIpCShN/Z12d39x7Clth+h2lX3pfQe1RcQ3xQ23k6/DQ35RiudVVhsH8YovGdk z6Oo= X-Google-Smtp-Source: AGHT+IHeeQ8fqyML5vW9K4B8EifeafJ+qeRRkbLMNV6XhNuUaFFWRAutmIl5tcg/2wYLm2oHU1Fn1Q== X-Received: by 2002:a17:906:f5a4:b0:a77:ab9e:9202 with SMTP id a640c23a62f3a-a9967856408mr51484766b.4.1728325382797; Mon, 07 Oct 2024 11:23:02 -0700 (PDT) Received: from [127.0.0.2] ([2a02:2454:ff21:ef40:4109:b8c2:873b:4a28]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c8e05eb34csm3452963a12.59.2024.10.07.11.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 11:23:02 -0700 (PDT) From: Stephan Gerhold Date: Mon, 07 Oct 2024 20:22:26 +0200 Subject: [PATCH 2/3] arm64: dts: qcom: x1e80100: Add uart14 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241007-x1e80100-pwrseq-qcp-v1-2-f7166510ab17@linaro.org> References: <20241007-x1e80100-pwrseq-qcp-v1-0-f7166510ab17@linaro.org> In-Reply-To: <20241007-x1e80100-pwrseq-qcp-v1-0-f7166510ab17@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Bartosz Golaszewski , Srinivas Kandagatla X-Mailer: b4 0.13.0 Add the uart14 instance for X1E80100 (typically used for Bluetooth). Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Tested-by: Johan Hovold --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 53 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 06d27c65dc11..185bb15c2945 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -1991,6 +1991,31 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, status =3D "disabled"; }; =20 + uart14: serial@a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x00a98000 0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + + pinctrl-0 =3D <&qup_uart14_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + i2c15: i2c@a9c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a9c000 0 0x4000>; @@ -5802,6 +5827,34 @@ rx-pins { }; }; =20 + qup_uart14_default: qup-uart14-default-state { + cts-pins { + pins =3D "gpio56"; + function =3D "qup1_se6"; + bias-bus-hold; + }; + + rts-pins { + pins =3D "gpio57"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + tx-pins { + pins =3D "gpio58"; + function =3D "qup1_se6"; + drive-strength =3D <2>; + bias-disable; + }; + + rx-pins { + pins =3D "gpio59"; + function =3D "qup1_se6"; + bias-pull-up; + }; + }; + qup_uart21_default: qup-uart21-default-state { tx-pins { pins =3D "gpio86"; --=20 2.46.0 From nobody Wed Nov 27 22:27:37 2024 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E1191DDC35 for ; Mon, 7 Oct 2024 18:23:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728325387; cv=none; b=fa9nn3ZY2aYqVEg0xKQQk9i6yVJMbxnXlNkO/Yn2bNMa9O+rUSRgBLINw8/Le89slHU7jbiGcZqklKqmSbTRUe0QQJmbt4dGQ7frBIg1UUZu0ooxzkkQNlaVETcQGpZgZ2nmhz51olmt+JK0aFpmPHJ2eZl5UjHOkAw41q01MHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728325387; c=relaxed/simple; bh=dWW5Fnb/Liw7P7L7ISnv9QYTAfrILqPJeU0hde7wkT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=op1Wne63ShetIh3bA7cJz/cjcnK9cV4rtB8ixd7k9DRvRpJ/iZCWBRYTnw5/67HnjtMQ8PBLeXEEaEpvrEvTdLSpVt9ZYOUT3kAlIN8ydULJBB4vnlSQhVYpTzf7MUvczgQodpGihccJie8twHtTcolaOfYu6V2Xes37aQ3z49o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=w6iKLQjc; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="w6iKLQjc" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-5c40aea5c40so392794a12.0 for ; Mon, 07 Oct 2024 11:23:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728325383; x=1728930183; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=z4ikrsSTudcXDr0qKC7KwQz3JWAw/JPV2vdvD08LgVA=; b=w6iKLQjch54ceU6I/isZqT/5q2UnWhvKdF4/wAEKLANqXfaQBn+lo+h5VncVeaIUhG 5rH8VNiZGDwl7qnxbwVeKE6os7VDcuJLBuF2tPFhg4ALvm6E1jvicWUgog6RFS5+bqDY qsWke/uEbMX1YYJRq2+Eoe62gb/OT7LwAo9HGny3+LVL6Ai2q7lVHTuqN59ipJoP4fdg ruSwXr28MYf5dBGu5tsxYWbMJLr6r3arYFWG3HDkAq9qstWwdmEyANYVbU7cAM2S82Jt RUSdsfQOx1uRG9MLskAm9/1YFpTKBf7w1G1uEJCJpWsQlpVG/FDZWWCdDVsQEhQcun/a VJ1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728325383; x=1728930183; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z4ikrsSTudcXDr0qKC7KwQz3JWAw/JPV2vdvD08LgVA=; b=BMDBQYNsqhqvNb2gPmt9xPBdl55c23MvgGaRu6gToaxgFFJWJnhdPqu2wQ1TKMNN2I vFyOdkaMBmlbRVkh+xQkd1BmI8f+oCXAldVCg15KGq2JB9WIp+isvo3VNyGO/SzW1heH jSwbmelev67Gmc+KL66yuTYBMGUVlsQU35hGUzZXKSWBdgAYrhkGKqYbZDMbVjMXTXKP fhkEg/jQyDxzO1RvbVvWj/oXSgvBRNpdvKeRDuCcS8+LzSqhjgXk2wRphqEUSbBJTddb xW5GQRZ6BZ/0SGPqByaHFjC0xtEkwYVIDojekPl+Rx7fxHFf60EtbGcqueqKbs/SJ8lY lZPQ== X-Forwarded-Encrypted: i=1; AJvYcCUHjvDZWHIbF9C5DsuIufsDywjMalP+5JWd8MgldkKfBGNhFqNfjsZtYFXEoT0Fa4ey2j0CDDk1ssvgapM=@vger.kernel.org X-Gm-Message-State: AOJu0YzDjf4Z/Gy8/9Ii7anMRhBpJCFMVEzEaTvOkK4cTpdMidoN/CtS bOAD3DMLZMYvsJyDYaKWOCIgba9EWjTS8Fcs5cNBIhYDcJ4dWWNVnB/ZHivGioY= X-Google-Smtp-Source: AGHT+IGMt2CHAKZO3Z4jDoLFfrRBZgFLZJ+sQ1ndDRbyE4RI/VUucDsSexodlYL7gvRwzN5a9xwQIw== X-Received: by 2002:a05:6402:278d:b0:5c8:a2b8:cab3 with SMTP id 4fb4d7f45d1cf-5c905cff396mr594317a12.4.1728325383549; Mon, 07 Oct 2024 11:23:03 -0700 (PDT) Received: from [127.0.0.2] ([2a02:2454:ff21:ef40:4109:b8c2:873b:4a28]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c8e05eb34csm3452963a12.59.2024.10.07.11.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 11:23:03 -0700 (PDT) From: Stephan Gerhold Date: Mon, 07 Oct 2024 20:22:27 +0200 Subject: [PATCH 3/3] arm64: dts: qcom: x1e80100-qcp: Add WiFi/BT pwrseq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241007-x1e80100-pwrseq-qcp-v1-3-f7166510ab17@linaro.org> References: <20241007-x1e80100-pwrseq-qcp-v1-0-f7166510ab17@linaro.org> In-Reply-To: <20241007-x1e80100-pwrseq-qcp-v1-0-f7166510ab17@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Bartosz Golaszewski , Srinivas Kandagatla X-Mailer: b4 0.13.0 Add the WiFi/BT nodes for QCP and describe the regulators for the WCN7850 combo chip using the new power sequencing bindings. All voltages are derived from chained fixed regulators controlled using a single GPIO. The same setup also works for CRD (and likely most of the other X1E80100 laptops). However, unlike the QCP they use soldered or removable M.2 cards supplied by a single 3.3V fixed regulator. The other necessary voltages are then derived inside the M.2 card. Describing this properly requires new bindings, so this commit only adds QCP for now. Signed-off-by: Stephan Gerhold --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 144 ++++++++++++++++++++++++++= ++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dt= s/qcom/x1e80100-qcp.dts index 1c3a6a7b3ed6..9977c2a505b9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -17,6 +17,7 @@ / { =20 aliases { serial0 =3D &uart21; + serial1 =3D &uart14; }; =20 wcd938x: audio-codec { @@ -254,6 +255,101 @@ vreg_nvme: regulator-nvme { pinctrl-names =3D "default"; pinctrl-0 =3D <&nvme_reg_en>; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wcn_sw_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_0P95"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <950000>; + + vin-supply =3D <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_WCN_1P9"; + regulator-min-microvolt =3D <1900000>; + regulator-max-microvolt =3D <1900000>; + + vin-supply =3D <&vreg_wcn_3p3>; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + vdd-supply =3D <&vreg_wcn_0p95>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_wcn_0p95>; + vdddig-supply =3D <&vreg_wcn_0p95>; + vddrfa1p2-supply =3D <&vreg_wcn_1p9>; + vddrfa1p8-supply =3D <&vreg_wcn_1p9>; + + wlan-enable-gpios =3D <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&wcn_wlan_bt_en>; + pinctrl-names =3D "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; }; =20 &apps_rsc { @@ -684,6 +780,23 @@ &pcie4_phy { status =3D "okay"; }; =20 +&pcie4_port0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie6a { perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -877,6 +990,37 @@ wcd_default: wcd-reset-n-active-state { bias-disable; output-low; }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins =3D "gpio116", "gpio117"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins =3D "gpio214"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + max-speed =3D <3200000>; + + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + }; }; =20 &uart21 { --=20 2.46.0