From nobody Wed Nov 27 23:48:15 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3A82193061; Mon, 7 Oct 2024 23:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728343030; cv=none; b=tYs5mU9Lzhw5QMPs6eOg2f4M6gN56WId3d0zXxjW3PwjMHREgpCf5THJ/h2nJ46raGfA45TCCXXjdcZuZx2cX+k82XXvprJfNw2R3LDLGZSZB7PUUu7kXEWd4rgSZ0ZvxJbV5hb2Mrv973z/9Q1fzoaR8H+OQqBnnR2duYwYNdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728343030; c=relaxed/simple; bh=iHoLyoaIkoFsO5+y1rXRFvxeSq4aKirIeeBFVTC39RU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dVzYZWYVCo00tw733zVgvBXXlNfMLhnEET9AUxD1Jt8QrHhs6hoaZMELhacBCc6qjTqfx34ffOZN98keX0TIWXLwFvUeHDGxJMhqourWMP6bgWXrKZJsz9fs7MrOujIAv4EssOT+b336byJXWj7ew6cxajMbqW5F1D79yhrGtME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SwS4lnXD; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SwS4lnXD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728343029; x=1759879029; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=iHoLyoaIkoFsO5+y1rXRFvxeSq4aKirIeeBFVTC39RU=; b=SwS4lnXDMkNNdQfe+X2gy29V4pMBz9o6z8rttwg/YKtutXODB/lOLwii XjDk9O55hWfpgAPho2WIZiC4FnMi28pds4iXrZf+gbGNHUU1Xehz7wOU4 qQOkTgKrNmEbJYxebFm1InkTlvh5xZ9Ra2UEXl/5EIztHY/lf0xhPnoRT SSpHmXSXzz36VrpQUIOrEImndRkniSrhAMXtFSGJ0KjB25hlPcfKelx8G Ci/pRQyqDN5cHR5TjAGOCalQ67tJoAptR4TagiONs7NQkXvhyvlZWyRoG mZuu6Dw/kmrJNBhXreZsTS8gLEfH1TgNn5nAo9GpXwVAb5+WlDOWztjKE w==; X-CSE-ConnectionGUID: bsy5TSOTQX2VJr+A6Zb/uw== X-CSE-MsgGUID: mBtfLUsHSIemAa6alfGr/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11218"; a="45036877" X-IronPort-AV: E=Sophos;i="6.11,185,1725346800"; d="scan'208";a="45036877" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2024 16:16:41 -0700 X-CSE-ConnectionGUID: gJalLDanQ/OTPzjve5wJig== X-CSE-MsgGUID: 1gB1MhI5QvS3Wnr3tSzmxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,185,1725346800"; d="scan'208";a="75309009" Received: from ldmartin-desk2.corp.intel.com (HELO localhost) ([10.125.110.112]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2024 16:16:38 -0700 From: ira.weiny@intel.com Date: Mon, 07 Oct 2024 18:16:15 -0500 Subject: [PATCH v4 09/28] cxl/core: Separate region mode from decoder mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241007-dcd-type2-upstream-v4-9-c261ee6eeded@intel.com> References: <20241007-dcd-type2-upstream-v4-0-c261ee6eeded@intel.com> In-Reply-To: <20241007-dcd-type2-upstream-v4-0-c261ee6eeded@intel.com> To: Dave Jiang , Fan Ni , Jonathan Cameron , Navneet Singh , Jonathan Corbet , Andrew Morton Cc: Dan Williams , Davidlohr Bueso , Alison Schofield , Vishal Verma , Ira Weiny , linux-btrfs@vger.kernel.org, linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org, nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org, Jonathan Cameron X-Mailer: b4 0.15-dev-37811 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728342968; l=10441; i=ira.weiny@intel.com; s=20221211; h=from:subject:message-id; bh=CV5/YMLMX9Gi6IaP+3LlGUtW4y/Qwz2Pk94dwvlv0aI=; b=rW3YK9ij6rfiSfDUHyYEbCENifLriaf/M8FuwPgKq6FrxX50KZ24EdtBVjNWMMEN8tuNjMXkm svsnfmAv9CrAIx8kSWD7dHypHHPhxYkVZU20LoOANr8bhJfEI4lYjQi X-Developer-Key: i=ira.weiny@intel.com; a=ed25519; pk=noldbkG+Wp1qXRrrkfY1QJpDf7QsOEthbOT7vm0PqsE= From: Navneet Singh Until now region modes and decoder modes were equivalent in that both modes were either PMEM or RAM. The addition of Dynamic Capacity partitions defines up to 8 DC partitions per device. The region mode is thus no longer equivalent to the endpoint decoder mode. IOW the endpoint decoders may have modes of DC0-DC7 while the region mode is simply DC. Define a new region mode enumeration which applies to regions separate from the decoder mode. Adjust the code to process these modes independently. There is no equal to decoder mode dead in region modes. Avoid constructing regions with decoders which have been flagged as dead. Suggested-by: Jonathan Cameron Signed-off-by: Navneet Singh Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- Changes: [iweiny: rebase] [Jonathan: remove dead code] [Jonathan: clarify commit message] --- drivers/cxl/core/cdat.c | 6 ++-- drivers/cxl/core/region.c | 75 ++++++++++++++++++++++++++++++++++---------= ---- drivers/cxl/cxl.h | 26 ++++++++++++++-- 3 files changed, 82 insertions(+), 25 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 438869df241a..bd50bb655741 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -571,17 +571,17 @@ static bool dpa_perf_contains(struct cxl_dpa_perf *pe= rf, } =20 static struct cxl_dpa_perf *cxled_get_dpa_perf(struct cxl_endpoint_decoder= *cxled, - enum cxl_decoder_mode mode) + enum cxl_region_mode mode) { struct cxl_memdev *cxlmd =3D cxled_to_memdev(cxled); struct cxl_memdev_state *mds =3D to_cxl_memdev_state(cxlmd->cxlds); struct cxl_dpa_perf *perf; =20 switch (mode) { - case CXL_DECODER_RAM: + case CXL_REGION_RAM: perf =3D &mds->ram_perf; break; - case CXL_DECODER_PMEM: + case CXL_REGION_PMEM: perf =3D &mds->pmem_perf; break; default: diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index e701e4b04032..f3a56003edc1 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -144,7 +144,7 @@ static ssize_t uuid_show(struct device *dev, struct dev= ice_attribute *attr, rc =3D down_read_interruptible(&cxl_region_rwsem); if (rc) return rc; - if (cxlr->mode !=3D CXL_DECODER_PMEM) + if (cxlr->mode !=3D CXL_REGION_PMEM) rc =3D sysfs_emit(buf, "\n"); else rc =3D sysfs_emit(buf, "%pUb\n", &p->uuid); @@ -457,7 +457,7 @@ static umode_t cxl_region_visible(struct kobject *kobj,= struct attribute *a, * Support tooling that expects to find a 'uuid' attribute for all * regions regardless of mode. */ - if (a =3D=3D &dev_attr_uuid.attr && cxlr->mode !=3D CXL_DECODER_PMEM) + if (a =3D=3D &dev_attr_uuid.attr && cxlr->mode !=3D CXL_REGION_PMEM) return 0444; return a->mode; } @@ -620,7 +620,7 @@ static ssize_t mode_show(struct device *dev, struct dev= ice_attribute *attr, { struct cxl_region *cxlr =3D to_cxl_region(dev); =20 - return sysfs_emit(buf, "%s\n", cxl_decoder_mode_name(cxlr->mode)); + return sysfs_emit(buf, "%s\n", cxl_region_mode_name(cxlr->mode)); } static DEVICE_ATTR_RO(mode); =20 @@ -646,7 +646,7 @@ static int alloc_hpa(struct cxl_region *cxlr, resource_= size_t size) =20 /* ways, granularity and uuid (if PMEM) need to be set before HPA */ if (!p->interleave_ways || !p->interleave_granularity || - (cxlr->mode =3D=3D CXL_DECODER_PMEM && uuid_is_null(&p->uuid))) + (cxlr->mode =3D=3D CXL_REGION_PMEM && uuid_is_null(&p->uuid))) return -ENXIO; =20 div64_u64_rem(size, (u64)SZ_256M * p->interleave_ways, &remainder); @@ -1863,6 +1863,17 @@ static int cxl_region_sort_targets(struct cxl_region= *cxlr) return rc; } =20 +static bool cxl_modes_compatible(enum cxl_region_mode rmode, + enum cxl_decoder_mode dmode) +{ + if (rmode =3D=3D CXL_REGION_RAM && dmode =3D=3D CXL_DECODER_RAM) + return true; + if (rmode =3D=3D CXL_REGION_PMEM && dmode =3D=3D CXL_DECODER_PMEM) + return true; + + return false; +} + static int cxl_region_attach(struct cxl_region *cxlr, struct cxl_endpoint_decoder *cxled, int pos) { @@ -1882,9 +1893,11 @@ static int cxl_region_attach(struct cxl_region *cxlr, return rc; } =20 - if (cxled->mode !=3D cxlr->mode) { - dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n", - dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode); + if (!cxl_modes_compatible(cxlr->mode, cxled->mode)) { + dev_dbg(&cxlr->dev, "%s region mode: %s mismatch decoder: %s\n", + dev_name(&cxled->cxld.dev), + cxl_region_mode_name(cxlr->mode), + cxl_decoder_mode_name(cxled->mode)); return -EINVAL; } =20 @@ -2446,7 +2459,7 @@ static int cxl_region_calculate_adistance(struct noti= fier_block *nb, * devm_cxl_add_region - Adds a region to a decoder * @cxlrd: root decoder * @id: memregion id to create, or memregion_free() on failure - * @mode: mode for the endpoint decoders of this region + * @mode: mode of this region * @type: select whether this is an expander or accelerator (type-2 or typ= e-3) * * This is the second step of region initialization. Regions exist within = an @@ -2457,7 +2470,7 @@ static int cxl_region_calculate_adistance(struct noti= fier_block *nb, */ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxl= rd, int id, - enum cxl_decoder_mode mode, + enum cxl_region_mode mode, enum cxl_decoder_type type) { struct cxl_port *port =3D to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); @@ -2511,16 +2524,17 @@ static ssize_t create_ram_region_show(struct device= *dev, } =20 static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd, - enum cxl_decoder_mode mode, int id) + enum cxl_region_mode mode, int id) { int rc; =20 switch (mode) { - case CXL_DECODER_RAM: - case CXL_DECODER_PMEM: + case CXL_REGION_RAM: + case CXL_REGION_PMEM: break; default: - dev_err(&cxlrd->cxlsd.cxld.dev, "unsupported mode %d\n", mode); + dev_err(&cxlrd->cxlsd.cxld.dev, "unsupported mode %s\n", + cxl_region_mode_name(mode)); return ERR_PTR(-EINVAL); } =20 @@ -2548,7 +2562,7 @@ static ssize_t create_pmem_region_store(struct device= *dev, if (rc !=3D 1) return -EINVAL; =20 - cxlr =3D __create_region(cxlrd, CXL_DECODER_PMEM, id); + cxlr =3D __create_region(cxlrd, CXL_REGION_PMEM, id); if (IS_ERR(cxlr)) return PTR_ERR(cxlr); =20 @@ -2568,7 +2582,7 @@ static ssize_t create_ram_region_store(struct device = *dev, if (rc !=3D 1) return -EINVAL; =20 - cxlr =3D __create_region(cxlrd, CXL_DECODER_RAM, id); + cxlr =3D __create_region(cxlrd, CXL_REGION_RAM, id); if (IS_ERR(cxlr)) return PTR_ERR(cxlr); =20 @@ -3215,6 +3229,22 @@ static int match_region_by_range(struct device *dev,= void *data) return rc; } =20 +static enum cxl_region_mode +cxl_decoder_to_region_mode(enum cxl_decoder_mode mode) +{ + switch (mode) { + case CXL_DECODER_NONE: + return CXL_REGION_NONE; + case CXL_DECODER_RAM: + return CXL_REGION_RAM; + case CXL_DECODER_PMEM: + return CXL_REGION_PMEM; + case CXL_DECODER_MIXED: + default: + return CXL_REGION_MIXED; + } +} + /* Establish an empty region covering the given HPA range */ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, struct cxl_endpoint_decoder *cxled) @@ -3223,12 +3253,17 @@ static struct cxl_region *construct_region(struct c= xl_root_decoder *cxlrd, struct cxl_port *port =3D cxlrd_to_port(cxlrd); struct range *hpa =3D &cxled->cxld.hpa_range; struct cxl_region_params *p; + enum cxl_region_mode mode; struct cxl_region *cxlr; struct resource *res; int rc; =20 + if (cxled->mode =3D=3D CXL_DECODER_DEAD) + return ERR_PTR(-EINVAL); + + mode =3D cxl_decoder_to_region_mode(cxled->mode); do { - cxlr =3D __create_region(cxlrd, cxled->mode, + cxlr =3D __create_region(cxlrd, mode, atomic_read(&cxlrd->region_id)); } while (IS_ERR(cxlr) && PTR_ERR(cxlr) =3D=3D -EBUSY); =20 @@ -3431,9 +3466,9 @@ static int cxl_region_probe(struct device *dev) return rc; =20 switch (cxlr->mode) { - case CXL_DECODER_PMEM: + case CXL_REGION_PMEM: return devm_cxl_add_pmem_region(cxlr); - case CXL_DECODER_RAM: + case CXL_REGION_RAM: /* * The region can not be manged by CXL if any portion of * it is already online as 'System RAM' @@ -3445,8 +3480,8 @@ static int cxl_region_probe(struct device *dev) return 0; return devm_cxl_add_dax_region(cxlr); default: - dev_dbg(&cxlr->dev, "unsupported region mode: %d\n", - cxlr->mode); + dev_dbg(&cxlr->dev, "unsupported region mode: %s\n", + cxl_region_mode_name(cxlr->mode)); return -ENXIO; } } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 0d8b810a51f0..5d74eb4ffab3 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -388,6 +388,27 @@ static inline const char *cxl_decoder_mode_name(enum c= xl_decoder_mode mode) return "mixed"; } =20 +enum cxl_region_mode { + CXL_REGION_NONE, + CXL_REGION_RAM, + CXL_REGION_PMEM, + CXL_REGION_MIXED, +}; + +static inline const char *cxl_region_mode_name(enum cxl_region_mode mode) +{ + static const char * const names[] =3D { + [CXL_REGION_NONE] =3D "none", + [CXL_REGION_RAM] =3D "ram", + [CXL_REGION_PMEM] =3D "pmem", + [CXL_REGION_MIXED] =3D "mixed", + }; + + if (mode >=3D CXL_REGION_NONE && mode <=3D CXL_REGION_MIXED) + return names[mode]; + return "mixed"; +} + /* * Track whether this decoder is reserved for region autodiscovery, or * free for userspace provisioning. @@ -515,7 +536,8 @@ struct cxl_region_params { * struct cxl_region - CXL region * @dev: This region's device * @id: This region's id. Id is globally unique across all regions - * @mode: Endpoint decoder allocation / access mode + * @mode: Region mode which defines which endpoint decoder modes the regio= n is + * compatible with * @type: Endpoint decoder target type * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge @@ -528,7 +550,7 @@ struct cxl_region_params { struct cxl_region { struct device dev; int id; - enum cxl_decoder_mode mode; + enum cxl_region_mode mode; enum cxl_decoder_type type; struct cxl_nvdimm_bridge *cxl_nvb; struct cxl_pmem_region *cxlr_pmem; --=20 2.46.0