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AJvYcCU39c9Qd8c5MEhekTcJLXMlE+03XFJIzAfpH1aUJVeOa25qttJWRuSz9mM6X6T+GAIMmW+SLR4XYdgv@vger.kernel.org, AJvYcCXoMq52xSSGnhT2tVydlZv5NmVp4aFh+0TnCTw9GG5bnYmJQlYeH0t7V12FRWRdvx+3sDme2UdGpNFhKik=@vger.kernel.org X-Gm-Message-State: AOJu0YzpvFabDVNZyWSvOvH6q5wWae5RbcJX3AXtRBaklfxlvEQL0cQS hORMUbnMpZ4KF3gX2cbSCjoVrZnrOunBM7L5SX9AhZZZLUq/l3XE X-Google-Smtp-Source: AGHT+IFUey3b+n+xgvsk3A3QkIQivs73Fk+cCDp0br0nrKsufgy8h7LMMcoUdhX14sv9BvrRhEbW3g== X-Received: by 2002:a17:90b:4a4a:b0:2e0:b741:cdbe with SMTP id 98e67ed59e1d1-2e1e631e2d4mr11196672a91.26.1728239106336; Sun, 06 Oct 2024 11:25:06 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.221]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e1e85c905esm5458471a91.17.2024.10.06.11.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Oct 2024 11:25:06 -0700 (PDT) From: Anand Moon To: Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , linux-pci@vger.kernel.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-rockchip@lists.infradead.org (open list:PCIE DRIVER FOR ROCKCHIP), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v6 RESET 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Date: Sun, 6 Oct 2024 23:54:36 +0530 Message-ID: <20241006182445.3713-2-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241006182445.3713-1-linux.amoon@gmail.com> References: <20241006182445.3713-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. Signed-off-by: Anand Moon --- v6: None. v5: switch to use use devm_clk_bulk_get_all()? gets rid of hardcoding the clock names in driver. v4: use dev_err_probe for error patch. v3: Fix typo in commit message, dropped reported by. v2: Fix compilation error reported by Intel test robot. --- drivers/pci/controller/pcie-rockchip.c | 65 +++----------------------- drivers/pci/controller/pcie-rockchip.h | 7 ++- 2 files changed, 10 insertions(+), 62 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controlle= r/pcie-rockchip.c index c07d7129f1c7..2777ef0cb599 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -127,29 +127,9 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockc= hip) "failed to get ep GPIO\n"); } =20 - rockchip->aclk_pcie =3D devm_clk_get(dev, "aclk"); - if (IS_ERR(rockchip->aclk_pcie)) { - dev_err(dev, "aclk clock not found\n"); - return PTR_ERR(rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie =3D devm_clk_get(dev, "aclk-perf"); - if (IS_ERR(rockchip->aclk_perf_pcie)) { - dev_err(dev, "aclk_perf clock not found\n"); - return PTR_ERR(rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie =3D devm_clk_get(dev, "hclk"); - if (IS_ERR(rockchip->hclk_pcie)) { - dev_err(dev, "hclk clock not found\n"); - return PTR_ERR(rockchip->hclk_pcie); - } - - rockchip->clk_pcie_pm =3D devm_clk_get(dev, "pm"); - if (IS_ERR(rockchip->clk_pcie_pm)) { - dev_err(dev, "pm clock not found\n"); - return PTR_ERR(rockchip->clk_pcie_pm); - } + rockchip->num_clks =3D devm_clk_bulk_get_all(dev, &rockchip->clks); + if (rockchip->num_clks < 0) + return dev_err_probe(dev, err, "failed to get clocks\n"); =20 return 0; } @@ -372,39 +352,11 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie = *rockchip) struct device *dev =3D rockchip->dev; int err; =20 - err =3D clk_prepare_enable(rockchip->aclk_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_pcie clock\n"); - return err; - } - - err =3D clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); - goto err_aclk_perf_pcie; - } - - err =3D clk_prepare_enable(rockchip->hclk_pcie); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_hclk_pcie; - } - - err =3D clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) { - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); - goto err_clk_pcie_pm; - } + err =3D clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks); + if (err) + return dev_err_probe(dev, err, "failed to enable clocks\n"); =20 return 0; - -err_clk_pcie_pm: - clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: - clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: - clk_disable_unprepare(rockchip->aclk_pcie); - return err; } EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); =20 @@ -412,10 +364,7 @@ void rockchip_pcie_disable_clocks(void *data) { struct rockchip_pcie *rockchip =3D data; =20 - clk_disable_unprepare(rockchip->clk_pcie_pm); - clk_disable_unprepare(rockchip->hclk_pcie); - clk_disable_unprepare(rockchip->aclk_perf_pcie); - clk_disable_unprepare(rockchip->aclk_pcie); + clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks); } EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); =20 diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index 6111de35f84c..bebab80c9553 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -11,6 +11,7 @@ #ifndef _PCIE_ROCKCHIP_H #define _PCIE_ROCKCHIP_H =20 +#include #include #include #include @@ -299,10 +300,8 @@ struct rockchip_pcie { struct reset_control *pm_rst; struct reset_control *aclk_rst; struct reset_control *pclk_rst; - struct clk *aclk_pcie; - struct clk *aclk_perf_pcie; - struct clk *hclk_pcie; - struct clk *clk_pcie_pm; + struct clk_bulk_data *clks; + int num_clks; struct regulator *vpcie12v; /* 12V power supply */ struct regulator *vpcie3v3; /* 3.3V power supply */ struct regulator *vpcie1v8; /* 1.8V power supply */ --=20 2.44.0