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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-539aff2904csm512749e87.304.2024.10.06.06.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Oct 2024 06:06:06 -0700 (PDT) From: Marcus Folkesson Date: Sun, 06 Oct 2024 15:05:46 +0200 Subject: [PATCH v4 1/2] mtd: nand: davinci: add support for on-die ECC engine type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241006-ondie-v4-1-ff9b9fd9a81d@gmail.com> References: <20241006-ondie-v4-0-ff9b9fd9a81d@gmail.com> In-Reply-To: <20241006-ondie-v4-0-ff9b9fd9a81d@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=PDm1f5NEBuhwxeXGvwzqxiOMHTZXe7TWbR431qOgkS4=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBnAoswOJ1pZOzYvme7rOBZkvdBMKiY6lb2UMKMQ hfdLyGcOKWJAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZwKLMAAKCRCIgE5vWV1S MkpiD/0ZNPL/5fjeuikolIZe2d2NTBwIUOMM6jr9VPfQYdO5KNWn85H9ZqKMwTCMpi6wauqElni XeAnDHP1eTfyoyqiGbf709Og0pvZAY8ONQ8WBNAnto5DkzH3/TPDMKR/Rqhn+jJpDE9BTDSADs3 kUHaIzA72NnB//pgJksJ3UzzTxOvTzVuc+LD8SviYB6sTz+iQNH+/KOCQsAr9maaycHBsXeI5U1 UE74yq4j7z/uRf+ND/Pr2w/c0OqUKP+qskMgE2bWrKblSGOls/NOMMRI5swdW+PxCEFEZwwjEkk RbWJILBS/ccypyYqEVfYPPoCFu48TGGyMY2bObxDPpvZAScXt5V6mRqmA8ELywuUvR1EGCnCSRd AYwmi42jTlw8a65wBx6GzGo5mK2j0/EjIgsu2wZhT8FPdygS74pw78Be2TxIAWysokUgEC/WToG PIQoslNpne7CRMj67QhMUEfgoZGuivXlm9UQpj/j8IcDolY78ZXhLD57G2aprw5ePsBo/2viwo8 2TqnfZcmTNnCTT549VaFwUVI2b+oB+CcLhy47CDYpzOmKUfQlVi8cvcxP5p1LQvzVclqdAL1m0r pdlnm1XNW5bVEcJ9Cj2eVZbdOCUWfZTnZIRHAqX9oplgEU08ivX1gRbi+sfT5QYKiou0syu6WXk Rk/6u/lw2z0/s5A== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Some chips, e.g. Micron MT29F1G08ABBFAH4, has a mandatory on-die ECC. Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- drivers/mtd/nand/raw/davinci_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36b20b42c1827eee8203dc2e41889a..79e768d337ae12f6e8d7f21f1ac= d4e259f4f3020 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -66,6 +66,7 @@ struct davinci_nand_pdata { =20 /* none =3D=3D NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) * soft =3D=3D NAND_ECC_ENGINE_TYPE_SOFT + * on-die =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE * else =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits * * All DaVinci-family chips support 1-bit hardware ECC. @@ -524,6 +525,8 @@ static struct davinci_nand_pdata pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; if (!strncmp("hw", mode, 2)) pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_HOST; + if (!strncmp("on-die", mode, 6)) + pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_DIE; } if (!of_property_read_u32(pdev->dev.of_node, "ti,davinci-ecc-bits", &prop)) @@ -580,6 +583,7 @@ static int davinci_nand_attach_chip(struct nand_chip *c= hip) =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_ON_DIE: pdata->ecc_bits =3D 0; break; case NAND_ECC_ENGINE_TYPE_SOFT: @@ -914,4 +918,3 @@ module_platform_driver(nand_davinci_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Texas Instruments"); MODULE_DESCRIPTION("Davinci NAND flash driver"); - --=20 2.46.0