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Sun, 06 Oct 2024 09:48:07 -0700 (PDT) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-539aff1d0e9sm570759e87.181.2024.10.06.09.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Oct 2024 09:48:06 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 06 Oct 2024 19:47:56 +0300 Subject: [PATCH] arm64: dts: qcom: sm8450 fix PIPE clock specification for pcie1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241006-fix-sm8450-pcie1-v1-1-4f227c9082ed@linaro.org> X-B4-Tracking: v=1; b=H4sIADu/AmcC/x2MQQqAIBAAvxJ7bkFNRfpKdMhaaw+ZKEQQ/j3pO DAzLxTKTAXG7oVMNxe+YgPZd7AeS9wJeWsMSigthbAY+MFyOm0EppVJovakBnI+SGOhZSlTc/7 lNNf6AaxyKONiAAAA To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1531; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Gu7LB3UGHKQJrsQedCSEt4sdbmh9d8FC6ZwZTDLlCQ4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnAr9EijfXLHgWl6HDcvQREsHqimYB0cXLp1elN 6zZLjjjlVyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZwK/RAAKCRCLPIo+Aiko 1at+B/9m2SCcQOVg4KJHbS3n7DiLGeETatz8q6D9PUMzY4p9qWkqwBhI7HBF67a6X4dZ+5rQznh JnO7Smr4VilAJ0aio24UohY+svOficAoHlX4l4QYQSKpEuMgZElxywZ1HotvDRLfTy/6l1mmsro yR0BKQVbMM8bRdc2IxyZsjPFUrOuEMC0ljESDXIGbImDTjdxIypd+RbuwaaXGADpR6biEE9E98J TWJZK8Uck/vsksloB2QJOVqHdXjpjwuQDi94pG4X8w5xS7Kbxv87n7iwbRvFtFtYPPTfSyFkURf DlCwDQetvfeTZXF8n6+gddiJvfNwAPy8VJ+iU69vcJO9p4ew X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A For historical reasons on SM8450 the second PCIe host (pcie1) also keeps a reference to the PIPE clock coming from the PHY. Commit e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks inputs to gcc") has updated the PHY to use #clock-cells =3D <1>, making just <&pcie1_phy> clock specification invalid. Update corresponding clock entry in the PCIe1 host node. /soc@0/pcie@1c08000: Failed to get clk index: 2 ret: -22 qcom-pcie 1c08000.pcie: Failed to get clocks qcom-pcie 1c08000.pcie: probe with driver qcom-pcie failed with error -22 Fixes: e76862840660 ("arm64: dts: qcom: sm8450: correct pcie1 phy clocks in= puts to gcc") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 9bafb3b350ff..38cb524cc568 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1973,7 +1973,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_phy>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, --- base-commit: 58ca61c1a866bfdaa5e19fb19a2416764f847d75 change-id: 20241006-fix-sm8450-pcie1-4be23e8bf156 Best regards, --=20 Dmitry Baryshkov