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Signed-off-by: Sibi Sankar Acked-by: Rob Herring (Arm) --- v2: * Fix Ghz -> GHz [Jeff] * Pick up Ab tag from Rob. Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 5cb54d69af0b..6a8fc031e51f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1049,6 +1049,12 @@ properties: - qcom,sm8650-qrd - const: qcom,sm8650 =20 + - items: + - enum: + - qcom,x1e001de-devkit + - const: qcom,x1e001de + - const: qcom,x1e80100 + - items: - enum: - lenovo,thinkpad-t14s --=20 2.34.1 From nobody Thu Nov 28 01:32:35 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7E3D15A85B; Sat, 5 Oct 2024 18:23:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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Sat, 05 Oct 2024 18:23:30 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 495INQA5001402 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 5 Oct 2024 18:23:26 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 5 Oct 2024 11:23:21 -0700 From: Sibi Sankar To: , , , , CC: , , , , , , , Subject: [PATCH V2 2/2] arm64: dts: qcom: Add X1E001DE Snapdragon Devkit for Windows Date: Sat, 5 Oct 2024 23:52:50 +0530 Message-ID: <20241005182250.788272-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241005182250.788272-1-quic_sibis@quicinc.com> References: <20241005182250.788272-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: A_ZVFL07Qhvs33kcxpzzIWrkP1c5U2F- X-Proofpoint-GUID: A_ZVFL07Qhvs33kcxpzzIWrkP1c5U2F- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410050135 Content-Type: text/plain; charset="utf-8" Add initial support for x1e001de devkit platform. This includes: -DSPs -Ethernet (RTL8125BG) over the pcie 5 instance. -NVme -Wifi -USB-C ports Link: https://www.qualcomm.com/news/releases/2024/05/qualcomm-accelerates-d= evelopment-for-copilot--pcs-with-snapdrago Signed-off-by: Sibi Sankar --- v2: * Fix Ghz -> GHz [Jeff] * Pick up Ab tag from Rob. * Use Vendor in ADSP/CDSP firmware path [Dmitry] * Fix reserved gpios [Dmitry] * Only port0 supports DRD update the dt accordingly [Dmitry] arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 811 +++++++++++++++++++ 2 files changed, 812 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e001de-devkit.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index ae002c7cf126..1cbc7b91389d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -268,6 +268,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk-display-card.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D x1e001de-devkit.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e78100-lenovo-thinkpad-t14s.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-asus-vivobook-s15.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot= /dts/qcom/x1e001de-devkit.dts new file mode 100644 index 000000000000..afd718c25be7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -0,0 +1,811 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Win= dows"; + compatible =3D "qcom,x1e001de-devkit", "qcom,x1e001de", "qcom,x1e80100"; + + aliases { + serial0 =3D &uart21; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + pmic-glink { + compatible =3D "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Back panel port closer to the RJ45 connector */ + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Back panel port closer to the audio jack */ + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "host"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + /* Front panel port */ + connector@2 { + compatible =3D "usb-c-connector"; + reg =3D <2>; + power-role =3D "dual"; + data-role =3D "host"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_NVME_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nvme_reg_en>; + }; + + vreg_wwan: regulator-wwan { + compatible =3D "regulator-fixed"; + + regulator-name =3D "SDX_VPH_PWR"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&wwan_sw_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob2>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l12-supply =3D <&vreg_s5j_1p2>; + vdd-l15-supply =3D <&vreg_s4c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name =3D "vreg_l5b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name =3D "vreg_l7b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name =3D "vreg_l8b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name =3D "vreg_l12b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name =3D "vreg_l14b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name =3D "vreg_l16b_2p9"; + regulator-min-microvolt =3D <2912000>; + regulator-max-microvolt =3D <2912000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name =3D "vreg_s4c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name =3D "vreg_l2c_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name =3D "vreg_l3c_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s4c_1p8>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name =3D "vreg_l1d_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name =3D "vreg_l2d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name =3D "vreg_l3d_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name =3D "vreg_l2e_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name =3D "vreg_s1f_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name =3D "vreg_l1f_1p0"; + regulator-min-microvolt =3D <1024000>; + regulator-max-microvolt =3D <1024000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name =3D "vreg_l2f_1p0"; + regulator-min-microvolt =3D <1024000>; + regulator-max-microvolt =3D <1024000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name =3D "vreg_l3f_1p0"; + regulator-min-microvolt =3D <1024000>; + regulator-max-microvolt =3D <1024000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "i"; + + vdd-l1-supply =3D <&vreg_s4c_1p8>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name =3D "vreg_s1i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name =3D "vreg_s2i_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name =3D "vreg_l1i_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name =3D "vreg_l3i_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "j"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name =3D "vreg_s5j_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name =3D "vreg_l1j_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name =3D "vreg_l2j_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name =3D "vreg_l3j_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&pcie4 { + perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie5 { + perst-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply =3D <&vreg_wwan>; + + pinctrl-0 =3D <&pcie5_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie5_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie6a { + perst-gpios =3D <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply =3D <&vreg_nvme>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie6a_default>; + + status =3D "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply =3D <&vreg_l1d_0p8>; + vdda-pll-supply =3D <&vreg_l2j_1p2>; + + status =3D "okay"; +}; + +&qupv3_0 { + status =3D "okay"; +}; + +&qupv3_1 { + status =3D "okay"; +}; + +&qupv3_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/x1e80100/THUNDERCOMM/DEVKIT/qcadsp8380.mbn", + "qcom/x1e80100/THUNDERCOMM/DEVKIT/adsp_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/x1e80100/THUNDERCOMM/DEVKIT/qccdsp8380.mbn", + "qcom/x1e80100/THUNDERCOMM/DEVKIT/cdsp_dtbs.elf"; + + status =3D "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status =3D "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l8b_3p0>; +}; + +&tlmm { + gpio-reserved-ranges =3D <44 4>; /* SPI (TPM) */ + + nvme_reg_en: nvme-reg-en-state { + pins =3D "gpio18"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins =3D "gpio150"; + function =3D "pcie5_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio149"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins =3D "gpio153"; + function =3D "pcie6a_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio152"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio154"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + wwan_sw_en: wwan-sw-en-state { + pins =3D "gpio221"; + function =3D "gpio"; + drive-strength =3D <4>; + bias-disable; + }; +}; + +&uart21 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +&usb_1_ss0_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_0_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l1j_0p8>; + + status =3D "okay"; +}; + +&usb_1_ss0 { + status =3D "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_1_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p9>; + + status =3D "okay"; +}; + +&usb_1_ss1 { + status =3D "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_2_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p9>; + + status =3D "okay"; +}; + +&usb_1_ss2 { + status =3D "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss2_ss_in>; +}; --=20 2.34.1