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charset="utf-8" The CFE bootloader places a stub program in the first page of physical memory to hold the secondary CPUs until the boot CPU writes the release address, but does not splice a /reserved-memory node into the FDT to protect it. If Linux overwrites this program before execution reaches smp_prepare_cpus(), the secondary CPUs may become inaccessible. This is only a problem with CFE, and then only until the secondary CPUs are brought online. Ideally, there would be some hypothetical mechanism we could use to indicate that this area of memory is sensitive only during boot. But as there is none, and since it is such a small amount of memory, it is easiest to reserve it unconditionally. Therefore, add a /reserved-memory node to bcm4908.dtsi to protect the first 4KiB of physical memory. Signed-off-by: Sam Edwards --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/= boot/dts/broadcom/bcmbca/bcm4908.dtsi index 8b924812322c..c51b92387fad 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -68,6 +68,16 @@ l2: l2-cache0 { }; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cfe-stub@0 { + reg =3D <0x0 0x0 0x0 0x1000>; + }; + }; + axi@81000000 { compatible =3D "simple-bus"; #address-cells =3D <1>; --=20 2.44.2 From nobody Thu Nov 28 02:49:43 2024 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29C5740C15; Sat, 5 Oct 2024 05:04:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Oct 2024 22:04:40 -0700 (PDT) Received: from celestia.turtle.lan ([2601:1c2:c184:dc00:ed3:4cda:b368:ce98]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e1e85db34fsm2625744a91.33.2024.10.04.22.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 22:04:39 -0700 (PDT) From: Sam Edwards X-Google-Original-From: Sam Edwards To: Florian Fainelli , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , William Zhang , Anand Gore , Kursad Oney Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Broadcom internal kernel review list , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sam Edwards Subject: [PATCH v2 2/2] arm64: dts: broadcom: bcmbca: bcm4908: Protect cpu-release-addr Date: Fri, 4 Oct 2024 22:01:55 -0700 Message-ID: <20241005050155.61103-3-CFSworks@gmail.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241005050155.61103-1-CFSworks@gmail.com> References: <20241005050155.61103-1-CFSworks@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The `cpu-release-addr` property is relevant only when the "spin-table" enable method is used. It is the physical address where the bootloader expects Linux to write the secondary CPU entry point's physical address. On this platform, only the CFE bootloader uses this method: U-Boot uses PSCI instead. CFE actually walks the FDT to learn this address, so we're free to put it wherever we want. We only need to make sure that it goes in a reserved-memory block so that writing to it during early boot does not risk conflicting with an unrelated memory allocation: this was not done. Since the previous patch reserved the first page of memory for CFE's secondary-CPU init stub, which is actually much smaller than a page, just put this address at the end of that page and it shall be so protected. Signed-off-by: Sam Edwards --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/= boot/dts/broadcom/bcmbca/bcm4908.dtsi index c51b92387fad..613ba7ee43d6 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -30,7 +30,7 @@ cpu0: cpu@0 { compatible =3D "brcm,brahma-b53"; reg =3D <0x0>; enable-method =3D "spin-table"; - cpu-release-addr =3D <0x0 0xfff8>; + cpu-release-addr =3D <0x0 0xff8>; next-level-cache =3D <&l2>; }; =20 @@ -39,7 +39,7 @@ cpu1: cpu@1 { compatible =3D "brcm,brahma-b53"; reg =3D <0x1>; enable-method =3D "spin-table"; - cpu-release-addr =3D <0x0 0xfff8>; + cpu-release-addr =3D <0x0 0xff8>; next-level-cache =3D <&l2>; }; =20 @@ -48,7 +48,7 @@ cpu2: cpu@2 { compatible =3D "brcm,brahma-b53"; reg =3D <0x2>; enable-method =3D "spin-table"; - cpu-release-addr =3D <0x0 0xfff8>; + cpu-release-addr =3D <0x0 0xff8>; next-level-cache =3D <&l2>; }; =20 @@ -57,7 +57,7 @@ cpu3: cpu@3 { compatible =3D "brcm,brahma-b53"; reg =3D <0x3>; enable-method =3D "spin-table"; - cpu-release-addr =3D <0x0 0xfff8>; + cpu-release-addr =3D <0x0 0xff8>; next-level-cache =3D <&l2>; }; =20 --=20 2.44.2