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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2faf9b3a88esm1857711fa.125.2024.10.05.01.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Oct 2024 01:26:43 -0700 (PDT) From: Marcus Folkesson Date: Sat, 05 Oct 2024 10:26:11 +0200 Subject: [PATCH v3 1/2] mtd: nand: davinci: add support for on-die ECC engine type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241005-ondie-v3-1-459d9c32225c@gmail.com> References: <20241005-ondie-v3-0-459d9c32225c@gmail.com> In-Reply-To: <20241005-ondie-v3-0-459d9c32225c@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=PDm1f5NEBuhwxeXGvwzqxiOMHTZXe7TWbR431qOgkS4=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBnAPgxCpGkVQjrQwxeY7yelCHPP4Knt13Zym1Ok Mdnp/0SIeqJAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZwD4MQAKCRCIgE5vWV1S MkiDEACc732NOWaYcnSMRquMSA/lGhB49H478+wBt9qie+3WcgpwB5JT+mC2G4iPmmYRQK3nGVG dHotjDqMC6Iw4S59OS3uHUIPItzhaBP+Yv+yE7ds30pRyVrW3ELjACNIbM1/l+krxjgt3HMp97P uRYBx/zN/ClslaVSKoExd9DG+o2u8n+OSb0mjKskVnn3qGnOm/Rx17dMSLVSs1Y7uonitNUhPWm JNz9epjEfNBtV9Neh9KjmctakSNua8O0Mt7Vfq/uHbVePn1Nof/kbRElO/fFZiTifpOrZJ6Fxk+ 8W8m8Z1Ag0Uz+v7jTo0lIbZdpM9E+GL7sORwtlzVVTtf9ZCDKEci+2drsq4oZWJ+akDkqE8/akz rG8LbEGztQunNugJhLaepROxbusYOJoK8KY9Q6IYlh9CBINFRXbB9OItX8LTwtpezUrudj3Sw3V 7zi0r9JC6/slryo6exmc1GnokhP/ww3MUFflwqRO/EqXm3vzmfcXd+9CqGaohFfaFhU7S0Dg5/j 6E3a+BMYisHWJK+tV5yyWRqWBAsZYhfGxbD+CNh3Kt/yIXiZRJq9jA4vLp1pXvGloAMSWWiLFQR uicjj8xkP3jOVrPfpXz+3RlZBnSGptba9lUVVyisN3kYSDc8AWhMXiyymGcf4RUN8erfFSzI3Fg 9qPUeZD7pDCOnXA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Some chips, e.g. Micron MT29F1G08ABBFAH4, has a mandatory on-die ECC. Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- drivers/mtd/nand/raw/davinci_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36b20b42c1827eee8203dc2e41889a..79e768d337ae12f6e8d7f21f1ac= d4e259f4f3020 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -66,6 +66,7 @@ struct davinci_nand_pdata { =20 /* none =3D=3D NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) * soft =3D=3D NAND_ECC_ENGINE_TYPE_SOFT + * on-die =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE * else =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits * * All DaVinci-family chips support 1-bit hardware ECC. @@ -524,6 +525,8 @@ static struct davinci_nand_pdata pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; if (!strncmp("hw", mode, 2)) pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_HOST; + if (!strncmp("on-die", mode, 6)) + pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_DIE; } if (!of_property_read_u32(pdev->dev.of_node, "ti,davinci-ecc-bits", &prop)) @@ -580,6 +583,7 @@ static int davinci_nand_attach_chip(struct nand_chip *c= hip) =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_ON_DIE: pdata->ecc_bits =3D 0; break; case NAND_ECC_ENGINE_TYPE_SOFT: @@ -914,4 +918,3 @@ module_platform_driver(nand_davinci_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Texas Instruments"); MODULE_DESCRIPTION("Davinci NAND flash driver"); - --=20 2.46.0