From nobody Thu Nov 28 05:38:34 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3DD2A212F11; Fri, 4 Oct 2024 15:30:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728055859; cv=none; b=fnDjt7XLYCoM1vDjKN0ozGFZSzoU2ez11G75+MiOqgc1F743NkSwVx6/PVdRbAxuwVUdNTENSZjYh7LfNKLAMmKZFAVuOmdckwg/iKblIBXtLiBfwPqfYgBFcKXU6r2spPnp9TZ+c6OPHs+Uv7EdTtBvMAE+4HSX3ruVEiuKI68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728055859; c=relaxed/simple; bh=0Lg6Fqb83zJbob4szAJWamiYdPgZsSO8seOcty87xUQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Os8BzyuEGiYKkgM0S8x213Tv25IaurdXVmUHJx908KarAcUxBeA4f4QpfzItNFsIaWazBpwmiOFUIPw7N0iCA9aspqhiWhcSPUwGJkG1X1vmOF6e4tcg2BMGNfpEP57fPmteQeG5DPygyh8EmxG1XJ2eYuATX2gDZilzq0dWzts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 563791063; Fri, 4 Oct 2024 08:31:27 -0700 (PDT) Received: from e122027.cambridge.arm.com (unknown [10.1.25.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 037443F640; Fri, 4 Oct 2024 08:30:53 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Steven Price Subject: [PATCH v5 35/43] arm64: RME: Propagate number of breakpoints and watchpoints to userspace Date: Fri, 4 Oct 2024 16:27:56 +0100 Message-Id: <20241004152804.72508-36-steven.price@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004152804.72508-1-steven.price@arm.com> References: <20241004152804.72508-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The RMM describes the maximum number of BPs/WPs available to the guest in the Feature Register 0. Propagate those numbers into ID_AA64DFR0_EL1, which is visible to userspace. A VMM needs this information in order to set up realm parameters. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price --- arch/arm64/include/asm/kvm_rme.h | 1 + arch/arm64/kvm/rme.c | 22 ++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 2 +- 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_rme.h b/arch/arm64/include/asm/kvm_= rme.h index f3ef166e0755..2b454ad633a6 100644 --- a/arch/arm64/include/asm/kvm_rme.h +++ b/arch/arm64/include/asm/kvm_rme.h @@ -88,6 +88,7 @@ struct realm_rec { =20 void kvm_init_rme(void); u32 kvm_realm_ipa_limit(void); +u64 kvm_realm_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, u64 val); =20 bool kvm_rme_supports_sve(void); =20 diff --git a/arch/arm64/kvm/rme.c b/arch/arm64/kvm/rme.c index 9a4d0299e56a..87f466e5b548 100644 --- a/arch/arm64/kvm/rme.c +++ b/arch/arm64/kvm/rme.c @@ -286,6 +286,28 @@ u32 kvm_realm_ipa_limit(void) return u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_S2SZ); } =20 +u64 kvm_realm_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, u64 val) +{ + u32 bps =3D u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_BPS); + u32 wps =3D u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_WPS); + u32 ctx_cmps; + + if (!kvm_is_realm(vcpu->kvm)) + return val; + + /* Ensure CTX_CMPs is still valid */ + ctx_cmps =3D FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, val); + ctx_cmps =3D min(bps, ctx_cmps); + + val &=3D ~(ID_AA64DFR0_EL1_BRPs_MASK | ID_AA64DFR0_EL1_WRPs_MASK | + ID_AA64DFR0_EL1_CTX_CMPs); + val |=3D FIELD_PREP(ID_AA64DFR0_EL1_BRPs_MASK, bps) | + FIELD_PREP(ID_AA64DFR0_EL1_WRPs_MASK, wps) | + FIELD_PREP(ID_AA64DFR0_EL1_CTX_CMPs, ctx_cmps); + + return val; +} + static int realm_create_rd(struct kvm *kvm) { struct realm *realm =3D &kvm->arch.realm; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 10949f3318ed..a73e0eb5dd85 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1746,7 +1746,7 @@ static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_= vcpu *vcpu, /* Hide SPE from guests */ val &=3D ~ID_AA64DFR0_EL1_PMSVer_MASK; =20 - return val; + return kvm_realm_reset_id_aa64dfr0_el1(vcpu, val); } =20 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, --=20 2.34.1