From nobody Thu Nov 28 04:38:11 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 54D911DD864; Fri, 4 Oct 2024 15:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728055845; cv=none; b=O/+76OmzjvTM2bcCEBGFi/CnfYnqu1uR7Alud1Hu/DOv14+3DfB5bV331iW3VvQSHmEMCInPjzMcrqToC2rlpO10bBIueUkiKFrLxnlNdqRHyNqCPb456m90nNSJmiRNGX/UnH3UQsR9pRpsrPb3bO9T1Ty1BiGwwoBSU1wS06A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728055845; c=relaxed/simple; bh=SiD9AMLfQ2FkivtgVtWn59/TCn0V/7bfhdab0dkQrAY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Qbda7FO6Tarp2/F5BT7hIUfikkmhi4GOE4lT0IjRpWp1AaIFmXyCLkHs46B4SbaSdCAqAQrnc/XPXfyXfaAunlINBuPRmsUk2jgg/LQaaKwNPYBwctZmyQGvI9tBFXMF+FnLHsz+h0F1AyXgYXPXKs2kuXCTh9FkMKIjnWr+Jdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7C2FE150C; Fri, 4 Oct 2024 08:31:13 -0700 (PDT) Received: from e122027.cambridge.arm.com (unknown [10.1.25.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BE2103F640; Fri, 4 Oct 2024 08:30:39 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" Subject: [PATCH v5 32/43] arm_pmu: Provide a mechanism for disabling the physical IRQ Date: Fri, 4 Oct 2024 16:27:53 +0100 Message-Id: <20241004152804.72508-33-steven.price@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004152804.72508-1-steven.price@arm.com> References: <20241004152804.72508-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Arm CCA assigns the physical PMU device to the guest running in realm world, however the IRQs are routed via the host. To enter a realm guest while a PMU IRQ is pending it is necessary to block the physical IRQ to prevent an immediate exit. Provide a mechanism in the PMU driver for KVM to control the physical IRQ. Signed-off-by: Steven Price --- v3: Add a dummy function for the !CONFIG_ARM_PMU case. --- drivers/perf/arm_pmu.c | 15 +++++++++++++++ include/linux/perf/arm_pmu.h | 5 +++++ 2 files changed, 20 insertions(+) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 398cce3d76fc..2cdcdda8f638 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -735,6 +735,21 @@ static int arm_perf_teardown_cpu(unsigned int cpu, str= uct hlist_node *node) return 0; } =20 +void arm_pmu_set_phys_irq(bool enable) +{ + int cpu =3D get_cpu(); + struct arm_pmu *pmu =3D per_cpu(cpu_armpmu, cpu); + int irq; + + irq =3D armpmu_get_cpu_irq(pmu, cpu); + if (irq && !enable) + per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq); + else if (irq && enable) + per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq); + + put_cpu(); +} + #ifdef CONFIG_CPU_PM static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd) { diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 4b5b83677e3f..6c2631e2cbd7 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -172,6 +172,7 @@ void kvm_host_pmu_init(struct arm_pmu *pmu); #endif =20 bool arm_pmu_irq_is_nmi(void); +void arm_pmu_set_phys_irq(bool enable); =20 /* Internal functions only for core arm_pmu code */ struct arm_pmu *armpmu_alloc(void); @@ -182,6 +183,10 @@ void armpmu_free_irq(int irq, int cpu); =20 #define ARMV8_PMU_PDEV_NAME "armv8-pmu" =20 +#else /* CONFIG_ARM_PMU */ + +static inline void arm_pmu_set_phys_irq(bool enable) {} + #endif /* CONFIG_ARM_PMU */ =20 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1" --=20 2.34.1