From nobody Thu Nov 28 04:32:41 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C8E321C19F; Fri, 4 Oct 2024 15:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728055773; cv=none; b=DiHM3a/At1z2g7Qiv7ShiHga8ffY/BLtn+GlQBGLDTFzGbLhZuHkTIJ/vRmuQl1eSprRw4Jk5L3+IPlTaTIZwWa0pEDpYYaeFiXioGioARpukYCoz4cZhVVYNqt8j4M+huooE4yI5m9qYLJOuA0j+LbuoLgbF5q8GiTfsvJ7bAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728055773; c=relaxed/simple; bh=tZ7PxKhu8cgK5uZWqxu2isZdR1iyM4Xv6DtrqOx4yKc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UI6t1+/yXc0hwuECEvzj5MAqsbgPe3pNlK9kPvmYFUBKkuNDRL1OYe15ePssPJFwcLvHMMB1wtas1Bo2U9LsYG99RSUIhqKUMTd48fbSNla9ymy8JHDIqVuM2xFmrUp1JzW+IOBxHc1I2icSUx0sZU5SRS3sonecxY5cGlLDHc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 787FB1063; Fri, 4 Oct 2024 08:30:00 -0700 (PDT) Received: from e122027.cambridge.arm.com (unknown [10.1.25.25]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11F8A3F640; Fri, 4 Oct 2024 08:29:26 -0700 (PDT) From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" Subject: [PATCH v5 16/43] KVM: arm64: Support timers in realm RECs Date: Fri, 4 Oct 2024 16:27:37 +0100 Message-Id: <20241004152804.72508-17-steven.price@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004152804.72508-1-steven.price@arm.com> References: <20241004152804.72508-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM keeps track of the timer while the realm REC is running, but on exit to the normal world KVM is responsible for handling the timers. A later patch adds the support for propagating the timer values from the exit data structure and calling kvm_realm_timers_update(). Signed-off-by: Steven Price --- arch/arm64/kvm/arch_timer.c | 45 ++++++++++++++++++++++++++++++++---- include/kvm/arm_arch_timer.h | 2 ++ 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 879982b1cc73..0b2be34a9ba3 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -162,6 +162,13 @@ static void timer_set_cval(struct arch_timer_context *= ctxt, u64 cval) =20 static void timer_set_offset(struct arch_timer_context *ctxt, u64 offset) { + struct kvm_vcpu *vcpu =3D ctxt->vcpu; + + if (kvm_is_realm(vcpu->kvm)) { + WARN_ON(offset); + return; + } + if (!ctxt->offset.vm_offset) { WARN(offset, "timer %ld\n", arch_timer_ctx_index(ctxt)); return; @@ -460,6 +467,21 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu= , bool new_level, } } =20 +void kvm_realm_timers_update(struct kvm_vcpu *vcpu) +{ + struct arch_timer_cpu *arch_timer =3D &vcpu->arch.timer_cpu; + int i; + + for (i =3D 0; i < NR_KVM_EL0_TIMERS; i++) { + struct arch_timer_context *timer =3D &arch_timer->timers[i]; + bool status =3D timer_get_ctl(timer) & ARCH_TIMER_CTRL_IT_STAT; + bool level =3D kvm_timer_irq_can_fire(timer) && status; + + if (level !=3D timer->irq.level) + kvm_timer_update_irq(vcpu, level, timer); + } +} + /* Only called for a fully emulated timer */ static void timer_emulate(struct arch_timer_context *ctx) { @@ -831,6 +853,8 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; =20 + kvm_timer_unblocking(vcpu); + get_timer_map(vcpu, &map); =20 if (static_branch_likely(&has_gic_active_state)) { @@ -844,8 +868,6 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) kvm_timer_vcpu_load_nogic(vcpu); } =20 - kvm_timer_unblocking(vcpu); - timer_restore_state(map.direct_vtimer); if (map.direct_ptimer) timer_restore_state(map.direct_ptimer); @@ -988,7 +1010,9 @@ static void timer_context_init(struct kvm_vcpu *vcpu, = int timerid) =20 ctxt->vcpu =3D vcpu; =20 - if (timerid =3D=3D TIMER_VTIMER) + if (kvm_is_realm(vcpu->kvm)) + ctxt->offset.vm_offset =3D NULL; + else if (timerid =3D=3D TIMER_VTIMER) ctxt->offset.vm_offset =3D &kvm->arch.timer_data.voffset; else ctxt->offset.vm_offset =3D &kvm->arch.timer_data.poffset; @@ -1011,13 +1035,19 @@ static void timer_context_init(struct kvm_vcpu *vcp= u, int timerid) void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) { struct arch_timer_cpu *timer =3D vcpu_timer(vcpu); + u64 cntvoff; =20 for (int i =3D 0; i < NR_KVM_TIMERS; i++) timer_context_init(vcpu, i); =20 + if (kvm_is_realm(vcpu->kvm)) + cntvoff =3D 0; + else + cntvoff =3D kvm_phys_timer_read(); + /* Synchronize offsets across timers of a VM if not already provided */ if (!test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { - timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read()); + timer_set_offset(vcpu_vtimer(vcpu), cntvoff); timer_set_offset(vcpu_ptimer(vcpu), 0); } =20 @@ -1525,6 +1555,13 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) return -EINVAL; } =20 + /* + * We don't use mapped IRQs for Realms because the RMI doesn't allow + * us setting the LR.HW bit in the VGIC. + */ + if (vcpu_is_rec(vcpu)) + return 0; + get_timer_map(vcpu, &map); =20 ret =3D kvm_vgic_map_phys_irq(vcpu, diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index c819c5d16613..d8ab297560d0 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -112,6 +112,8 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struc= t kvm_device_attr *attr); int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *= attr); int kvm_arm_timer_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *= attr); =20 +void kvm_realm_timers_update(struct kvm_vcpu *vcpu); + u64 kvm_phys_timer_read(void); =20 void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu); --=20 2.34.1