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charset="utf-8" From: Lad Prabhakar On the RZ/V2H(P) SoC we can configure the 'input-schmitt-{enable,disable}' , 'drive-open-drain' and 'drive-push-pull' of multiplexed pins. Update the binding documentation to include these properties. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven --- Hi Rob, I have dropped your Ack from v1 as I have updated the commit message and included `drive-push-pull` property in v2. Cheers, Prabhakar v1->v2 - Added `drive-push-pull` property --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 56d90c8e1fa3..a1805b6e3f63 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -119,6 +119,10 @@ additionalProperties: bias-disable: true bias-pull-down: true bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + drive-open-drain: true + drive-push-pull: true renesas,output-impedance: description: Output impedance for pins on the RZ/V2H(P) SoC. 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charset="utf-8" From: Lad Prabhakar Add support for enabling and disabling open-drain outputs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea --- v1->v2 - Implemented PIN_CONFIG_DRIVE_OPEN_DRAIN to disable open drain --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index b2d309f742af..8d576cc74003 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -139,6 +139,7 @@ #define IEN(off) (0x1800 + (off) * 8) #define PUPD(off) (0x1C00 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) +#define NOD(off) (0x3000 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) @@ -160,6 +161,7 @@ #define IOLH_MASK 0x03 #define SR_MASK 0x01 #define PUPD_MASK 0x03 +#define NOD_MASK 0x01 =20 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -1337,6 +1339,18 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_= dev *pctldev, break; } =20 + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!(cfg & PIN_CFG_NOD)) + return -EINVAL; + + arg =3D rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); + if (!arg && param !=3D PIN_CONFIG_DRIVE_PUSH_PULL) + return -EINVAL; + if (arg && param !=3D PIN_CONFIG_DRIVE_OPEN_DRAIN) + return -EINVAL; + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; @@ -1466,6 +1480,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_= dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; =20 + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (!(cfg & PIN_CFG_NOD)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, + param =3D=3D PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; --=20 2.43.0 From nobody Thu Nov 28 03:50:54 2024 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 395A31D45E2; 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Fri, 04 Oct 2024 05:37:15 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9910285ad0sm221601166b.34.2024.10.04.05.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 05:37:14 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/3] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Date: Fri, 4 Oct 2024 13:36:58 +0100 Message-ID: <20241004123658.764557-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241004123658.764557-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241004123658.764557-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for configuring the multiplexed pins as schmitt-trigger inputs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea --- v1->v2 - Included RB tag --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 8d576cc74003..13708c71f938 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -140,6 +140,7 @@ #define PUPD(off) (0x1C00 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define NOD(off) (0x3000 + (off) * 8) +#define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) @@ -162,6 +163,7 @@ #define SR_MASK 0x01 #define PUPD_MASK 0x03 #define NOD_MASK 0x01 +#define SMT_MASK 0x01 =20 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -1351,6 +1353,15 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_= dev *pctldev, return -EINVAL; break; =20 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + arg =3D rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); + if (!arg) + return -EINVAL; + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; @@ -1489,6 +1500,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_= dev *pctldev, param =3D=3D PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); break; =20 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; --=20 2.43.0