From nobody Thu Nov 28 08:03:13 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22CC9137903; Fri, 4 Oct 2024 10:29:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037755; cv=none; b=bsLe9XnS0HBHVvsy/O7CPd0BJ6qGXxGokfBCT5HvMaDZhf/ncpX4bUZSygPm1wxlxl9VZAY9UFeyRqi0k2n/9SAC//getPNQSwQa1E15Ve3DtTCBtohGErf8Q/QM5v+VKYE5JtGSowyM5uL58wqD4RY1OGnIsTMmoPK/RYx/SIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037755; c=relaxed/simple; bh=zC0pzXFkZLfu1dvUKLlr/A0EPafZUj9zxvMS5wrt0jM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PI3gxed1MSpTQmk9ZtCiisDaNSWLmm49R/Aggg1diu+lCYxMDWsYhIDx8ciIZ/BrXR7xNWbFAIQJbTIX8vrSlt2nJ+8ct9K5SwK0Hvkw50IY5caSOfPiCW33HnmYMVy1Og2NY5mcL12/RK85ZUXwGpI5iBfG7rnFGxneb4o/3AE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=RRmmJ98H; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RRmmJ98H" X-UUID: 7cfc3a34823b11ef8b96093e013ec31c-20241004 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=HgwbjxT4BnONX80gnaJTuLk+hJpQVXjT4Dp2LdkD1yQ=; b=RRmmJ98HFdiSzBm0ZBhkuCSokeDa01qx5hvRefjNTqzRPU+bBeHBVCuvK708/7zMyH0mFornRsUtaHsojUxclURGs/LhxqopYqBrn9TZ04y6nfU3COwBw69bjKgZ8WxZYWThF0mcSO9n/hpa+zbIG+S994bGvi9RrkxHSo8FpRo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:c13f0e92-001d-4595-82f7-7a0e7bd6d6a6,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:db164a26-5902-4533-af4f-d0904aa89b3c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 7cfc3a34823b11ef8b96093e013ec31c-20241004 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1538793620; Fri, 04 Oct 2024 18:29:08 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 4 Oct 2024 18:29:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 4 Oct 2024 18:29:07 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next 6/9] net: phy: mediatek: Hook LED helper functions in mtk-ge.c Date: Fri, 4 Oct 2024 18:24:10 +0800 Message-ID: <20241004102413.5838-7-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241004102413.5838-1-SkyLake.Huang@mediatek.com> References: <20241004102413.5838-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "SkyLake.Huang" We have mtk-phy-lib.c now so that we can use LED helper functions in mtk-ge.c(mt7531 part). It also means that mt7531/mt7981/mt7988's Giga ethernet phys share almost the same HW LED controller design. Also, add probe function for mt7531 so that it can initialize LED state. Signed-off-by: SkyLake.Huang --- drivers/net/phy/mediatek/mtk-ge.c | 100 ++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/net/phy/mediatek/mtk-ge.c b/drivers/net/phy/mediatek/m= tk-ge.c index 9122899..18f6988 100644 --- a/drivers/net/phy/mediatek/mtk-ge.c +++ b/drivers/net/phy/mediatek/mtk-ge.c @@ -13,6 +13,10 @@ #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 =20 +struct mtk_gephy_priv { + unsigned long led_state; +}; + static void mtk_gephy_config_init(struct phy_device *phydev) { /* Enable HW auto downshift */ @@ -57,6 +61,96 @@ static int mt7531_phy_config_init(struct phy_device *phy= dev) return 0; } =20 +static int mt7531_phy_probe(struct phy_device *phydev) +{ + struct mtk_gephy_priv *priv; + + priv =3D devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_gephy_priv), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + phydev->priv =3D priv; + + mtk_phy_leds_state_init(phydev); + + return 0; +} + +static int mt753x_phy_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + struct mtk_gephy_priv *priv =3D phydev->priv; + bool blinking =3D false; + int err =3D 0; + + err =3D mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); + if (err < 0) + return err; + + err =3D mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, + blinking); + if (err) + return err; + + return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state, + MTK_GPHY_LED_ON_MASK, false); +} + +static int mt753x_phy_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + struct mtk_gephy_priv *priv =3D phydev->priv; + int err; + + err =3D mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, false); + if (err) + return err; + + return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state, + MTK_GPHY_LED_ON_MASK, (value !=3D LED_OFF)); +} + +static const unsigned long supported_triggers =3D + BIT(TRIGGER_NETDEV_FULL_DUPLEX) | + BIT(TRIGGER_NETDEV_HALF_DUPLEX) | + BIT(TRIGGER_NETDEV_LINK) | + BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_RX) | + BIT(TRIGGER_NETDEV_TX); + +static int mt753x_phy_led_hw_is_supported(struct phy_device *phydev, u8 in= dex, + unsigned long rules) +{ + return mtk_phy_led_hw_is_supported(phydev, index, rules, + supported_triggers); +} + +static int mt753x_phy_led_hw_control_get(struct phy_device *phydev, u8 ind= ex, + unsigned long *rules) +{ + struct mtk_gephy_priv *priv =3D phydev->priv; + + return mtk_phy_led_hw_ctrl_get(phydev, index, rules, &priv->led_state, + MTK_GPHY_LED_ON_SET, + MTK_GPHY_LED_RX_BLINK_SET, + MTK_GPHY_LED_TX_BLINK_SET); +}; + +static int mt753x_phy_led_hw_control_set(struct phy_device *phydev, u8 ind= ex, + unsigned long rules) +{ + struct mtk_gephy_priv *priv =3D phydev->priv; + + return mtk_phy_led_hw_ctrl_set(phydev, index, rules, &priv->led_state, + MTK_GPHY_LED_ON_SET, + MTK_GPHY_LED_RX_BLINK_SET, + MTK_GPHY_LED_TX_BLINK_SET); +}; + static struct phy_driver mtk_gephy_driver[] =3D { { PHY_ID_MATCH_EXACT(0x03a29412), @@ -75,6 +169,7 @@ static struct phy_driver mtk_gephy_driver[] =3D { { PHY_ID_MATCH_EXACT(0x03a29441), .name =3D "MediaTek MT7531 PHY", + .probe =3D mt7531_phy_probe, .config_init =3D mt7531_phy_config_init, /* Interrupts are handled by the switch, not the PHY * itself. @@ -85,6 +180,11 @@ static struct phy_driver mtk_gephy_driver[] =3D { .resume =3D genphy_resume, .read_page =3D mtk_phy_read_page, .write_page =3D mtk_phy_write_page, + .led_blink_set =3D mt753x_phy_led_blink_set, + .led_brightness_set =3D mt753x_phy_led_brightness_set, + .led_hw_is_supported =3D mt753x_phy_led_hw_is_supported, + .led_hw_control_set =3D mt753x_phy_led_hw_control_set, + .led_hw_control_get =3D mt753x_phy_led_hw_control_get, }, }; =20 --=20 2.45.2