From nobody Thu Nov 28 08:46:24 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2911D15666B; Fri, 4 Oct 2024 10:25:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037545; cv=none; b=MvOKuKh4Poc9ElasFdvlnp5L/fZYM5tnCii8YQZyUg2DPVy9TjJFpeWwLvIbt1cj6zoKg3DV+eeWadrmTwzHc1FCs9nxcHILARGu0eAsYU/+yr94vmvToGMuvMcd53QMbGDpWxXR361LxeO2FuBFloKRfvR6oY1nJil9tqIBs3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037545; c=relaxed/simple; bh=i56urSGA77O30gKxSkdxT//7k0PfwRRUL0UwgRJNFgM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=esVVxoCgl9g6+uvNqSjvSHrhXPaaaoAkAvNjVsyGTme3mkp4OPc4SMijW9o9Hn9pkYYAo9pk5iaYHYPxIdb+xQKcnl7aqVmulau81LsIvpMy9pMKAS0vV7iWhRd6ndwvtvKbPMC9vPToY9NUbj4XT8nQbITpybXpBxtDWUJqUwU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=NG7IT+TG; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="NG7IT+TG" X-UUID: ff05811c823a11efb66947d174671e26-20241004 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=wer5ECKcvtPnhShkDN59yy5gHBjUtTENiisrwOY3oqA=; b=NG7IT+TG/gnxEZnZcnC5fEFSDRlS1Eo4mudAiqIIPw61+52wTxSRwy32zTulcas5za3qEi7ZM4oL1xp+KKRfMhr63a3iUaTgL6oEn6CeHrtPgkKGmYPNJH4Jo1S7Wk2tC9G+16D+JJK/18lE3iJoanfwjqK/CihxmT+doL7Smzs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:d56162eb-29f2-488e-82e5-6b036d4170c2,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:c3a3be64-444a-4b47-a99a-591ade3b04b2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ff05811c823a11efb66947d174671e26-20241004 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 632572102; Fri, 04 Oct 2024 18:25:37 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 4 Oct 2024 18:25:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 4 Oct 2024 18:25:33 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next 3/9] net: phy: mediatek: Move LED helper functions into mtk phy lib Date: Fri, 4 Oct 2024 18:24:07 +0800 Message-ID: <20241004102413.5838-4-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241004102413.5838-1-SkyLake.Huang@mediatek.com> References: <20241004102413.5838-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.098700-8.000000 X-TMASE-MatchedRID: 00/V74AkYY80Z9sXcK7F6W3NvezwBrVmK2i9pofGVSvvSbc8qoHu0Ypb wG9fIuITgn1a0E4VtJ7x8wGpucGjY++Qm7Tg9jG3i/b+LxU2p45dymZBcuGGREYvSDWdWaRhrW4 1+BBqq+82sd63g/m4nT2buOMU1Fv7kKjL2IOi2LAVglQa/gMvfDQAp53S718HRQ0dAChl/lzeTU cydIM+R1+2TZ8bogGe7SSpJucKGx9G2s3FJ9V4+SYRREGYqtmU5Y0kb0hqatw0QmmUihPzrAaTa lM8C773iLwCGMQswxCNXPSEO7vJlR9tyJCN9GW1dAg4yd14qAR9LQinZ4QefPcjNeVeWlqY+gtH j7OwNO0gCYMnfcK3PL27MCjRJvBtxUEWXsyHuxhhGjb0b0grVqPDywq2AuKHuthZE2Ft11o= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.098700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 225A4930ABB919784B78C61A84F70B7AA6F607E82E0722F5ED34EB9BD1C7167F2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "SkyLake.Huang" This patch creates mtk-phy-lib.c & mtk-phy.h and integrates mtk-ge-soc.c's LED helper functions so that we can use those helper functions in other MTK's ethernet phy driver. Signed-off-by: SkyLake.Huang --- MAINTAINERS | 2 + drivers/net/phy/mediatek/Kconfig | 5 + drivers/net/phy/mediatek/Makefile | 1 + drivers/net/phy/mediatek/mtk-ge-soc.c | 262 +++---------------------- drivers/net/phy/mediatek/mtk-phy-lib.c | 251 +++++++++++++++++++++++ drivers/net/phy/mediatek/mtk.h | 82 ++++++++ 6 files changed, 368 insertions(+), 235 deletions(-) create mode 100644 drivers/net/phy/mediatek/mtk-phy-lib.c create mode 100644 drivers/net/phy/mediatek/mtk.h diff --git a/MAINTAINERS b/MAINTAINERS index 6deaf94..e58e05c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13794,7 +13794,9 @@ M: SkyLake Huang L: netdev@vger.kernel.org S: Maintained F: drivers/net/phy/mediatek/mtk-ge-soc.c +F: drivers/net/phy/mediatek/mtk-phy-lib.c F: drivers/net/phy/mediatek/mtk-ge.c +F: drivers/net/phy/mediatek/mtk.h F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c =20 MEDIATEK I2C CONTROLLER DRIVER diff --git a/drivers/net/phy/mediatek/Kconfig b/drivers/net/phy/mediatek/Kc= onfig index 6839ea6..448bc20 100644 --- a/drivers/net/phy/mediatek/Kconfig +++ b/drivers/net/phy/mediatek/Kconfig @@ -1,6 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only +config MTK_NET_PHYLIB + tristate + config MEDIATEK_GE_PHY tristate "MediaTek Gigabit Ethernet PHYs" + select MTK_NET_PHYLIB help Supports the MediaTek non-built-in Gigabit Ethernet PHYs. =20 @@ -13,6 +17,7 @@ config MEDIATEK_GE_SOC_PHY tristate "MediaTek SoC Ethernet PHYs" depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST select NVMEM_MTK_EFUSE + select MTK_NET_PHYLIB help Supports MediaTek SoC built-in Gigabit Ethernet PHYs. =20 diff --git a/drivers/net/phy/mediatek/Makefile b/drivers/net/phy/mediatek/M= akefile index 005bde2..814879d 100644 --- a/drivers/net/phy/mediatek/Makefile +++ b/drivers/net/phy/mediatek/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_MTK_NET_PHYLIB) +=3D mtk-phy-lib.o obj-$(CONFIG_MEDIATEK_GE_PHY) +=3D mtk-ge.o obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) +=3D mtk-ge-soc.o diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediat= ek/mtk-ge-soc.c index 0eb5395..970bf35 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -8,6 +8,8 @@ #include #include =20 +#include "mtk.h" + #define MTK_GPHY_ID_MT7981 0x03a29461 #define MTK_GPHY_ID_MT7988 0x03a29481 =20 @@ -210,41 +212,6 @@ #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 =20 /* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) -#define MTK_PHY_LED_ON_LINK1000 BIT(0) -#define MTK_PHY_LED_ON_LINK100 BIT(1) -#define MTK_PHY_LED_ON_LINK10 BIT(2) -#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\ - MTK_PHY_LED_ON_LINK100 |\ - MTK_PHY_LED_ON_LINK1000) -#define MTK_PHY_LED_ON_LINKDOWN BIT(3) -#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ -#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ -#define MTK_PHY_LED_ON_FORCE_ON BIT(6) -#define MTK_PHY_LED_ON_POLARITY BIT(14) -#define MTK_PHY_LED_ON_ENABLE BIT(15) - -#define MTK_PHY_LED0_BLINK_CTRL 0x25 -#define MTK_PHY_LED1_BLINK_CTRL 0x27 -#define MTK_PHY_LED_BLINK_1000TX BIT(0) -#define MTK_PHY_LED_BLINK_1000RX BIT(1) -#define MTK_PHY_LED_BLINK_100TX BIT(2) -#define MTK_PHY_LED_BLINK_100RX BIT(3) -#define MTK_PHY_LED_BLINK_10TX BIT(4) -#define MTK_PHY_LED_BLINK_10RX BIT(5) -#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\ - MTK_PHY_LED_BLINK_100RX |\ - MTK_PHY_LED_BLINK_1000RX) -#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\ - MTK_PHY_LED_BLINK_100TX |\ - MTK_PHY_LED_BLINK_1000TX) -#define MTK_PHY_LED_BLINK_COLLISION BIT(6) -#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) -#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) -#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) - #define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) =20 #define MTK_PHY_RG_BG_RASEL 0x115 @@ -299,10 +266,6 @@ enum CAL_MODE { SW_M }; =20 -#define MTK_PHY_LED_STATE_FORCE_ON 0 -#define MTK_PHY_LED_STATE_FORCE_BLINK 1 -#define MTK_PHY_LED_STATE_NETDEV 2 - struct mtk_socphy_priv { unsigned long led_state; }; @@ -1131,84 +1094,39 @@ static int mt798x_phy_config_init(struct phy_device= *phydev) return mt798x_phy_calibration(phydev); } =20 -static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index, - bool on) -{ - unsigned int bit_on =3D MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); - struct mtk_socphy_priv *priv =3D phydev->priv; - bool changed; - - if (on) - changed =3D !test_and_set_bit(bit_on, &priv->led_state); - else - changed =3D !!test_and_clear_bit(bit_on, &priv->led_state); - - changed |=3D !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + - (index ? 16 : 0), &priv->led_state); - if (changed) - return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? - MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED_ON_MASK, - on ? MTK_PHY_LED_ON_FORCE_ON : 0); - else - return 0; -} - -static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, - bool blinking) -{ - unsigned int bit_blink =3D MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : = 0); - struct mtk_socphy_priv *priv =3D phydev->priv; - bool changed; - - if (blinking) - changed =3D !test_and_set_bit(bit_blink, &priv->led_state); - else - changed =3D !!test_and_clear_bit(bit_blink, &priv->led_state); - - changed |=3D !!test_bit(MTK_PHY_LED_STATE_NETDEV + - (index ? 16 : 0), &priv->led_state); - if (changed) - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? - MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL, - blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0); - else - return 0; -} - static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, unsigned long *delay_on, unsigned long *delay_off) { + struct mtk_socphy_priv *priv =3D phydev->priv; bool blinking =3D false; int err =3D 0; =20 - if (index > 1) - return -EINVAL; - - if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { - blinking =3D true; - *delay_on =3D 50; - *delay_off =3D 50; - } + err =3D mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); + if (err < 0) + return err; =20 - err =3D mt798x_phy_hw_led_blink_set(phydev, index, blinking); + err =3D mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, + blinking); if (err) return err; =20 - return mt798x_phy_hw_led_on_set(phydev, index, false); + return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state, + MTK_GPHY_LED_ON_MASK, false); } =20 static int mt798x_phy_led_brightness_set(struct phy_device *phydev, u8 index, enum led_brightness value) { + struct mtk_socphy_priv *priv =3D phydev->priv; int err; =20 - err =3D mt798x_phy_hw_led_blink_set(phydev, index, false); + err =3D mtk_phy_hw_led_blink_set(phydev, index, &priv->led_state, false); if (err) return err; =20 - return mt798x_phy_hw_led_on_set(phydev, index, (value !=3D LED_OFF)); + return mtk_phy_hw_led_on_set(phydev, index, &priv->led_state, + MTK_GPHY_LED_ON_MASK, (value !=3D LED_OFF)); } =20 static const unsigned long supported_triggers =3D (BIT(TRIGGER_NETDEV_FULL= _DUPLEX) | @@ -1223,148 +1141,30 @@ static const unsigned long supported_triggers =3D = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 in= dex, unsigned long rules) { - if (index > 1) - return -EINVAL; - - /* All combinations of the supported triggers are allowed */ - if (rules & ~supported_triggers) - return -EOPNOTSUPP; - - return 0; -}; + return mtk_phy_led_hw_is_supported(phydev, index, rules, + supported_triggers); +} =20 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 ind= ex, unsigned long *rules) { - unsigned int bit_blink =3D MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : = 0); - unsigned int bit_netdev =3D MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); - unsigned int bit_on =3D MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); struct mtk_socphy_priv *priv =3D phydev->priv; - int on, blink; - - if (index > 1) - return -EINVAL; - - on =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, - index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); - - if (on < 0) - return -EIO; - - blink =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, - index ? MTK_PHY_LED1_BLINK_CTRL : - MTK_PHY_LED0_BLINK_CTRL); - if (blink < 0) - return -EIO; - - if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | - MTK_PHY_LED_ON_LINKDOWN)) || - (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX))) - set_bit(bit_netdev, &priv->led_state); - else - clear_bit(bit_netdev, &priv->led_state); - - if (on & MTK_PHY_LED_ON_FORCE_ON) - set_bit(bit_on, &priv->led_state); - else - clear_bit(bit_on, &priv->led_state); - - if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) - set_bit(bit_blink, &priv->led_state); - else - clear_bit(bit_blink, &priv->led_state); - - if (!rules) - return 0; - - if (on & MTK_PHY_LED_ON_LINK) - *rules |=3D BIT(TRIGGER_NETDEV_LINK); - - if (on & MTK_PHY_LED_ON_LINK10) - *rules |=3D BIT(TRIGGER_NETDEV_LINK_10); - - if (on & MTK_PHY_LED_ON_LINK100) - *rules |=3D BIT(TRIGGER_NETDEV_LINK_100); =20 - if (on & MTK_PHY_LED_ON_LINK1000) - *rules |=3D BIT(TRIGGER_NETDEV_LINK_1000); - - if (on & MTK_PHY_LED_ON_FDX) - *rules |=3D BIT(TRIGGER_NETDEV_FULL_DUPLEX); - - if (on & MTK_PHY_LED_ON_HDX) - *rules |=3D BIT(TRIGGER_NETDEV_HALF_DUPLEX); - - if (blink & MTK_PHY_LED_BLINK_RX) - *rules |=3D BIT(TRIGGER_NETDEV_RX); - - if (blink & MTK_PHY_LED_BLINK_TX) - *rules |=3D BIT(TRIGGER_NETDEV_TX); - - return 0; + return mtk_phy_led_hw_ctrl_get(phydev, index, rules, &priv->led_state, + MTK_GPHY_LED_ON_SET, + MTK_GPHY_LED_RX_BLINK_SET, + MTK_GPHY_LED_TX_BLINK_SET); }; =20 static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 ind= ex, unsigned long rules) { - unsigned int bit_netdev =3D MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); struct mtk_socphy_priv *priv =3D phydev->priv; - u16 on =3D 0, blink =3D 0; - int ret; - - if (index > 1) - return -EINVAL; - - if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) - on |=3D MTK_PHY_LED_ON_FDX; =20 - if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) - on |=3D MTK_PHY_LED_ON_HDX; - - if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) - on |=3D MTK_PHY_LED_ON_LINK10; - - if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) - on |=3D MTK_PHY_LED_ON_LINK100; - - if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) - on |=3D MTK_PHY_LED_ON_LINK1000; - - if (rules & BIT(TRIGGER_NETDEV_RX)) { - blink |=3D (on & MTK_PHY_LED_ON_LINK) ? - (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) | - ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) | - ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) : - MTK_PHY_LED_BLINK_RX; - } - - if (rules & BIT(TRIGGER_NETDEV_TX)) { - blink |=3D (on & MTK_PHY_LED_ON_LINK) ? - (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) | - ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) | - ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) : - MTK_PHY_LED_BLINK_TX; - } - - if (blink || on) - set_bit(bit_netdev, &priv->led_state); - else - clear_bit(bit_netdev, &priv->led_state); - - ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? - MTK_PHY_LED1_ON_CTRL : - MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED_ON_FDX | - MTK_PHY_LED_ON_HDX | - MTK_PHY_LED_ON_LINK, - on); - - if (ret) - return ret; - - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? - MTK_PHY_LED1_BLINK_CTRL : - MTK_PHY_LED0_BLINK_CTRL, blink); + return mtk_phy_led_hw_ctrl_set(phydev, index, rules, &priv->led_state, + MTK_GPHY_LED_ON_SET, + MTK_GPHY_LED_RX_BLINK_SET, + MTK_GPHY_LED_TX_BLINK_SET); }; =20 static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led= _num) @@ -1438,14 +1238,6 @@ static int mt7988_phy_probe_shared(struct phy_device= *phydev) return 0; } =20 -static void mt798x_phy_leds_state_init(struct phy_device *phydev) -{ - int i; - - for (i =3D 0; i < 2; ++i) - mt798x_phy_led_hw_control_get(phydev, i, NULL); -} - static int mt7988_phy_probe(struct phy_device *phydev) { struct mtk_socphy_shared *shared; @@ -1471,7 +1263,7 @@ static int mt7988_phy_probe(struct phy_device *phydev) =20 phydev->priv =3D priv; =20 - mt798x_phy_leds_state_init(phydev); + mtk_phy_leds_state_init(phydev); =20 err =3D mt7988_phy_fix_leds_polarities(phydev); if (err) @@ -1498,7 +1290,7 @@ static int mt7981_phy_probe(struct phy_device *phydev) =20 phydev->priv =3D priv; =20 - mt798x_phy_leds_state_init(phydev); + mtk_phy_leds_state_init(phydev); =20 return mt798x_phy_calibration(phydev); } diff --git a/drivers/net/phy/mediatek/mtk-phy-lib.c b/drivers/net/phy/media= tek/mtk-phy-lib.c new file mode 100644 index 0000000..e1fbeff --- /dev/null +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +#include + +#include "mtk.h" + +int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules, + unsigned long supported_triggers) +{ + if (index > 1) + return -EINVAL; + + /* All combinations of the supported triggers are allowed */ + if (rules & ~supported_triggers) + return -EOPNOTSUPP; + + return 0; +} +EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported); + +int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, + unsigned long *rules, unsigned long *led_state, + u16 on_set, u16 rx_blink_set, u16 tx_blink_set) +{ + unsigned int bit_blink =3D MTK_PHY_LED_STATE_FORCE_BLINK + + (index ? 16 : 0); + unsigned int bit_netdev =3D MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); + unsigned int bit_on =3D MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); + int on, blink; + + if (index > 1) + return -EINVAL; + + on =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, + index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL); + + if (on < 0) + return -EIO; + + blink =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, + index ? MTK_PHY_LED1_BLINK_CTRL : + MTK_PHY_LED0_BLINK_CTRL); + if (blink < 0) + return -EIO; + + if ((on & (on_set | MTK_PHY_LED_ON_FDX | + MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) || + (blink & (rx_blink_set | tx_blink_set))) + set_bit(bit_netdev, led_state); + else + clear_bit(bit_netdev, led_state); + + if (on & MTK_PHY_LED_ON_FORCE_ON) + set_bit(bit_on, led_state); + else + clear_bit(bit_on, led_state); + + if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK) + set_bit(bit_blink, led_state); + else + clear_bit(bit_blink, led_state); + + if (!rules) + return 0; + + if (on & on_set) + *rules |=3D BIT(TRIGGER_NETDEV_LINK); + + if (on & MTK_PHY_LED_ON_LINK10) + *rules |=3D BIT(TRIGGER_NETDEV_LINK_10); + + if (on & MTK_PHY_LED_ON_LINK100) + *rules |=3D BIT(TRIGGER_NETDEV_LINK_100); + + if (on & MTK_PHY_LED_ON_LINK1000) + *rules |=3D BIT(TRIGGER_NETDEV_LINK_1000); + + if (on & MTK_PHY_LED_ON_LINK2500) + *rules |=3D BIT(TRIGGER_NETDEV_LINK_2500); + + if (on & MTK_PHY_LED_ON_FDX) + *rules |=3D BIT(TRIGGER_NETDEV_FULL_DUPLEX); + + if (on & MTK_PHY_LED_ON_HDX) + *rules |=3D BIT(TRIGGER_NETDEV_HALF_DUPLEX); + + if (blink & rx_blink_set) + *rules |=3D BIT(TRIGGER_NETDEV_RX); + + if (blink & tx_blink_set) + *rules |=3D BIT(TRIGGER_NETDEV_TX); + + return 0; +} +EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get); + +int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, + unsigned long rules, unsigned long *led_state, + u16 on_set, u16 rx_blink_set, u16 tx_blink_set) +{ + unsigned int bit_netdev =3D MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0); + u16 on =3D 0, blink =3D 0; + int ret; + + if (index > 1) + return -EINVAL; + + if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX)) + on |=3D MTK_PHY_LED_ON_FDX; + + if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX)) + on |=3D MTK_PHY_LED_ON_HDX; + + if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) + on |=3D MTK_PHY_LED_ON_LINK10; + + if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) + on |=3D MTK_PHY_LED_ON_LINK100; + + if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) + on |=3D MTK_PHY_LED_ON_LINK1000; + + if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) + on |=3D MTK_PHY_LED_ON_LINK2500; + + if (rules & BIT(TRIGGER_NETDEV_RX)) { + blink |=3D (on & on_set) ? + (((on & MTK_PHY_LED_ON_LINK10) ? + MTK_PHY_LED_BLINK_10RX : 0) | + ((on & MTK_PHY_LED_ON_LINK100) ? + MTK_PHY_LED_BLINK_100RX : 0) | + ((on & MTK_PHY_LED_ON_LINK1000) ? + MTK_PHY_LED_BLINK_1000RX : 0) | + ((on & MTK_PHY_LED_ON_LINK2500) ? + MTK_PHY_LED_BLINK_2500RX : 0)) : + rx_blink_set; + } + + if (rules & BIT(TRIGGER_NETDEV_TX)) { + blink |=3D (on & on_set) ? + (((on & MTK_PHY_LED_ON_LINK10) ? + MTK_PHY_LED_BLINK_10TX : 0) | + ((on & MTK_PHY_LED_ON_LINK100) ? + MTK_PHY_LED_BLINK_100TX : 0) | + ((on & MTK_PHY_LED_ON_LINK1000) ? + MTK_PHY_LED_BLINK_1000TX : 0) | + ((on & MTK_PHY_LED_ON_LINK2500) ? + MTK_PHY_LED_BLINK_2500TX : 0)) : + tx_blink_set; + } + + if (blink || on) + set_bit(bit_netdev, led_state); + else + clear_bit(bit_netdev, led_state); + + ret =3D phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? + MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, + MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set, + on); + + if (ret) + return ret; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? + MTK_PHY_LED1_BLINK_CTRL : + MTK_PHY_LED0_BLINK_CTRL, blink); +} +EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set); + +int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, + unsigned long *delay_off, bool *blinking) +{ + if (index > 1) + return -EINVAL; + + if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) { + *blinking =3D true; + *delay_on =3D 50; + *delay_off =3D 50; + } + + return 0; +} +EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg); + +int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, + unsigned long *led_state, u16 led_on_mask, bool on) +{ + unsigned int bit_on =3D MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0); + bool changed; + + if (on) + changed =3D !test_and_set_bit(bit_on, led_state); + else + changed =3D !!test_and_clear_bit(bit_on, led_state); + + changed |=3D !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV + + (index ? 16 : 0), led_state); + if (changed) + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? + MTK_PHY_LED1_ON_CTRL : + MTK_PHY_LED0_ON_CTRL, + led_on_mask, + on ? MTK_PHY_LED_ON_FORCE_ON : 0); + else + return 0; +} +EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set); + +int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *led_state, bool blinking) +{ + unsigned int bit_blink =3D MTK_PHY_LED_STATE_FORCE_BLINK + + (index ? 16 : 0); + bool changed; + + if (blinking) + changed =3D !test_and_set_bit(bit_blink, led_state); + else + changed =3D !!test_and_clear_bit(bit_blink, led_state); + + changed |=3D !!test_bit(MTK_PHY_LED_STATE_NETDEV + + (index ? 16 : 0), led_state); + if (changed) + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? + MTK_PHY_LED1_BLINK_CTRL : + MTK_PHY_LED0_BLINK_CTRL, + blinking ? + MTK_PHY_LED_BLINK_FORCE_BLINK : 0); + else + return 0; +} +EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set); + +void mtk_phy_leds_state_init(struct phy_device *phydev) +{ + int i; + + for (i =3D 0; i < 2; ++i) + phydev->drv->led_hw_control_get(phydev, i, NULL); +} +EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init); + +MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common"); +MODULE_AUTHOR("Sky Huang "); +MODULE_AUTHOR("Daniel Golle "); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/phy/mediatek/mtk.h b/drivers/net/phy/mediatek/mtk.h new file mode 100644 index 0000000..2fc89e3 --- /dev/null +++ b/drivers/net/phy/mediatek/mtk.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Common definition for Mediatek Ethernet PHYs + * Author: SkyLake Huang + * Copyright (c) 2024 MediaTek Inc. + */ + +#ifndef _MTK_EPHY_H_ +#define _MTK_EPHY_H_ + +#define MTK_EXT_PAGE_ACCESS 0x1f + +/* Registers on MDIO_MMD_VEND2 */ +#define MTK_PHY_LED0_ON_CTRL 0x24 +#define MTK_PHY_LED1_ON_CTRL 0x26 +#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0) +#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0) +#define MTK_PHY_LED_ON_LINK1000 BIT(0) +#define MTK_PHY_LED_ON_LINK100 BIT(1) +#define MTK_PHY_LED_ON_LINK10 BIT(2) +#define MTK_PHY_LED_ON_LINKDOWN BIT(3) +#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ +#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ +#define MTK_PHY_LED_ON_FORCE_ON BIT(6) +#define MTK_PHY_LED_ON_LINK2500 BIT(7) +#define MTK_PHY_LED_ON_POLARITY BIT(14) +#define MTK_PHY_LED_ON_ENABLE BIT(15) + +#define MTK_PHY_LED0_BLINK_CTRL 0x25 +#define MTK_PHY_LED1_BLINK_CTRL 0x27 +#define MTK_PHY_LED_BLINK_1000TX BIT(0) +#define MTK_PHY_LED_BLINK_1000RX BIT(1) +#define MTK_PHY_LED_BLINK_100TX BIT(2) +#define MTK_PHY_LED_BLINK_100RX BIT(3) +#define MTK_PHY_LED_BLINK_10TX BIT(4) +#define MTK_PHY_LED_BLINK_10RX BIT(5) +#define MTK_PHY_LED_BLINK_COLLISION BIT(6) +#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) +#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) +#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) +#define MTK_PHY_LED_BLINK_2500TX BIT(10) +#define MTK_PHY_LED_BLINK_2500RX BIT(11) + +#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \ + MTK_PHY_LED_ON_LINK100 | \ + MTK_PHY_LED_ON_LINK10) +#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ + MTK_PHY_LED_BLINK_100RX | \ + MTK_PHY_LED_BLINK_10RX) +#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ + MTK_PHY_LED_BLINK_100RX | \ + MTK_PHY_LED_BLINK_10RX) + +#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \ + MTK_GPHY_LED_ON_SET) +#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ + MTK_GPHY_LED_RX_BLINK_SET) +#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ + MTK_GPHY_LED_TX_BLINK_SET) + +#define MTK_PHY_LED_STATE_FORCE_ON 0 +#define MTK_PHY_LED_STATE_FORCE_BLINK 1 +#define MTK_PHY_LED_STATE_NETDEV 2 + +int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules, + unsigned long supported_triggers); +int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, + unsigned long rules, unsigned long *led_state, + u16 on_set, u16 rx_blink_set, u16 tx_blink_set); +int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, + unsigned long *rules, unsigned long *led_state, + u16 on_set, u16 rx_blink_set, u16 tx_blink_set); +int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, + unsigned long *delay_off, bool *blinking); +int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, + unsigned long *led_state, u16 led_on_mask, bool on); +int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *led_state, bool blinking); +void mtk_phy_leds_state_init(struct phy_device *phydev); + +#endif /* _MTK_EPHY_H_ */ --=20 2.45.2