From nobody Thu Nov 28 04:46:45 2024 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5AC914659C for ; Fri, 4 Oct 2024 09:09:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728032977; cv=none; b=WzgoyPIXsRT1fBBJzhfQC+xqBXXJ5e2mGo16AifHll2AqPU15Q5Ta0dPF52lrfLfsRLPvK6o+mB2X/tqi9hexLX8brcQltq4aa41ZHeKW1ItnwmqLs9YR6iH91L+zAOSi+Ec7v3yN5fRCG8HZE8RpGQY6IAgb3ptcT0NqBqpJJU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728032977; c=relaxed/simple; bh=V+RixZSjGrTzxO9wVeJtMYL3mAuDqMaHU7I7qNk6B/c=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=R71Tg7HVJOyAXzaMH919nsvSlZgdxlDB7sNxaNVe8ouZrxYqA+iiN//JZPJFQHdXzog2wo21cBxFXr/7Pdv/gcX78rhQY7mhWNI+M4tHlVePikwKvB9r5JsBw2dwX2Zec+uDBGcIh4Vc5xxP2XhRqZvPd/5GEDxtU9pIcNgQ7wo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=crzufK7X; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="crzufK7X" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1728032974; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=KeAMh0T1DMYBfSkg4rMFIKsLXbl/1FZfHzQE7MzILB0=; b=crzufK7XCQ3n/PFg8dY/tMRiXN+kj101bXZ6e1HhDS9BDQDsn59tQkkI77kV5CejGt9Xpe fJdjVuJzRrHkJJAEvj5NvcvRYdB/jqZYsOvaKeaJf7gMqU3VypyyPpeC8/V9M7zGN4lfzp B5qkKN7DbZsGxbyypvBr3TD5YpWh3g4= Received: from mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-632-srQA7pafMfuBXjA6m1retg-1; Fri, 04 Oct 2024 05:09:29 -0400 X-MC-Unique: srQA7pafMfuBXjA6m1retg-1 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 7FB9619560AF; Fri, 4 Oct 2024 09:09:24 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.39.192.229]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1B6401956054; Fri, 4 Oct 2024 09:09:16 +0000 (UTC) From: Jocelyn Falempe To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Aurabindo Pillai , Melissa Wen , Joshua Ashton , =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= , Jocelyn Falempe , Hersen Wu , Tom Chung , Roman Li , Bhuvana Chandra Pinninti , Alvin Lee , Sung Joon Kim , Duncan Ma , Hamza Mahfooz , Lu Yao , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amdgpu: Add dcn30 drm_panic support Date: Fri, 4 Oct 2024 11:07:54 +0200 Message-ID: <20241004090850.460668-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Content-Type: text/plain; charset="utf-8" Add support for the drm_panic module, which displays a pretty user friendly message on the screen when a Linux kernel panic occurs. It should work on all readeon using amdgpu_dm_plane.c, when the framebuffer is linear (like when in a VT). For tiled framebuffer, it will only work on radeon with dcn30. It should be easy to add support for dcn20 or dcn31, but I can't test it. I've tested it on a Radeon W6400 pro. Signed-off-by: Jocelyn Falempe --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 137 +++++++++++++++++- .../amd/display/dc/hubp/dcn30/dcn30_hubp.c | 17 +++ .../amd/display/dc/hubp/dcn30/dcn30_hubp.h | 2 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 + 4 files changed, 155 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 25f63b2e7a8e2..a62b197ab6833 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -26,7 +26,9 @@ =20 #include #include +#include "drm/drm_framebuffer.h" #include +#include #include #include #include @@ -36,6 +38,7 @@ #include "amdgpu_display.h" #include "amdgpu_dm_trace.h" #include "amdgpu_dm_plane.h" +#include "bif/bif_4_1_d.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" =20 @@ -1420,6 +1423,125 @@ static void amdgpu_dm_plane_atomic_async_update(str= uct drm_plane *plane, amdgpu_dm_plane_handle_cursor_update(plane, old_state); } =20 +/* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used i= n amdgpu_dm_set_pixel() + * they are called from the panic handler, and no race condition can occur= s. + */ +static struct amdgpu_bo *panic_abo; + +/* Use the indirect MMIO to write each pixel to the GPU VRAM, + * This is a simplified version of amdgpu_device_mm_access() + */ +static void amdgpu_dm_set_pixel(struct drm_scanout_buffer *sb, + unsigned int x, + unsigned int y, + u32 color) +{ + struct amdgpu_res_cursor cursor; + unsigned long offset; + struct amdgpu_bo *abo =3D panic_abo; + struct amdgpu_device *adev =3D amdgpu_ttm_adev(abo->tbo.bdev); + uint32_t tmp; + + offset =3D x * 4 + y * sb->pitch[0]; + amdgpu_res_first(abo->tbo.resource, offset, 4, &cursor); + + tmp =3D cursor.start >> 31; + WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t) cursor.start) | 0x80000000); + if (tmp !=3D 0xffffffff) + WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); + WREG32_NO_KIQ(mmMM_DATA, color); +} + +static int amdgpu_dm_plane_disable_tiling(struct dc_plane_state *dc_plane_= state) +{ + struct dc_state *dc_state; + int i; + + if (!dc_plane_state) + return -EINVAL; + + dc_state =3D dc_plane_state->ctx->dc->current_state; + if (!dc_state) + return -EINVAL; + + for (i =3D 0; i < dc_plane_state->ctx->dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx =3D &dc_state->res_ctx.pipe_ctx[i]; + struct hubp *hubp; + + if (!pipe_ctx) + continue; + + hubp =3D pipe_ctx->plane_res.hubp; + if (!hubp) + continue; + + if (!hubp->funcs->hubp_clear_tiling) + return -EINVAL; + + hubp->funcs->hubp_clear_tiling(hubp); + hubp->funcs->hubp_program_surface_flip_and_addr(hubp, + &dc_plane_state->address, + dc_plane_state->flip_immediate); + } + return 0; +} + +static int amdgpu_dm_plane_get_scanout_buffer(struct drm_plane *plane, + struct drm_scanout_buffer *sb) +{ + struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(plane->state); + struct amdgpu_bo *abo; + struct drm_framebuffer *fb =3D plane->state->fb; + + if (!fb) + return -EINVAL; + + DRM_DEBUG_KMS("Framebuffer %dx%d %p4cc\n", fb->width, fb->height, &fb->fo= rmat->format); + + abo =3D gem_to_amdgpu_bo(fb->obj[0]); + if (!abo) + return -EINVAL; + + /* disable tiling */ + if (fb->modifier && amdgpu_dm_plane_disable_tiling(dm_plane_state->dc_sta= te)) + return -EINVAL; + + sb->width =3D fb->width; + sb->height =3D fb->height; + /* Use the generic linear format, because we just disabled tiling */ + sb->format =3D drm_format_info(fb->format->format); + if (!sb->format) + return -EINVAL; + + sb->pitch[0] =3D fb->pitches[0]; + + if (abo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) { + if (abo->tbo.resource->mem_type !=3D TTM_PL_VRAM) { + DRM_WARN("amdgpu panic, framebuffer not in VRAM\n"); + return -EINVAL; + } + /* Only handle 32bits format, to simplify mmio access */ + if (fb->format->cpp[0] !=3D 4) { + DRM_WARN("amdgpu panic, pixel format is not 32bits\n"); + return -EINVAL; + } + sb->set_pixel =3D amdgpu_dm_set_pixel; + panic_abo =3D abo; + return 0; + } + if (!abo->kmap.virtual && + ttm_bo_kmap(&abo->tbo, 0, PFN_UP(abo->tbo.base.size), &abo->kmap)) { + DRM_WARN("amdgpu bo map failed, panic won't be displayed\n"); + return -ENOMEM; + } + if (abo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK) + iosys_map_set_vaddr_iomem(&sb->map[0], abo->kmap.virtual); + else + iosys_map_set_vaddr(&sb->map[0], abo->kmap.virtual); + + return 0; +} + static const struct drm_plane_helper_funcs dm_plane_helper_funcs =3D { .prepare_fb =3D amdgpu_dm_plane_helper_prepare_fb, .cleanup_fb =3D amdgpu_dm_plane_helper_cleanup_fb, @@ -1428,6 +1550,15 @@ static const struct drm_plane_helper_funcs dm_plane_= helper_funcs =3D { .atomic_async_update =3D amdgpu_dm_plane_atomic_async_update }; =20 +static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = =3D { + .prepare_fb =3D amdgpu_dm_plane_helper_prepare_fb, + .cleanup_fb =3D amdgpu_dm_plane_helper_cleanup_fb, + .atomic_check =3D amdgpu_dm_plane_atomic_check, + .atomic_async_check =3D amdgpu_dm_plane_atomic_async_check, + .atomic_async_update =3D amdgpu_dm_plane_atomic_async_update, + .get_scanout_buffer =3D amdgpu_dm_plane_get_scanout_buffer, +}; + static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state =3D NULL; @@ -1854,7 +1985,10 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manag= er *dm, plane->type !=3D DRM_PLANE_TYPE_CURSOR) drm_plane_enable_fb_damage_clips(plane); =20 - drm_plane_helper_add(plane, &dm_plane_helper_funcs); + if (plane->type =3D=3D DRM_PLANE_TYPE_PRIMARY) + drm_plane_helper_add(plane, &dm_primary_plane_helper_funcs); + else + drm_plane_helper_add(plane, &dm_plane_helper_funcs); =20 #ifdef AMD_PRIVATE_COLOR dm_atomic_plane_attach_color_mgmt_properties(dm, plane); @@ -1876,4 +2010,3 @@ bool amdgpu_dm_plane_is_video_format(uint32_t format) =20 return false; } - diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drive= rs/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 60a64d2903527..3b16c3cda2c3e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -334,6 +334,22 @@ void hubp3_program_tiling( =20 } =20 +void hubp3_clear_tiling(struct hubp *hubp) +{ + struct dcn20_hubp *hubp2 =3D TO_DCN20_HUBP(hubp); + + REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0); + REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR); + + REG_UPDATE_6(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_DCC_EN, 0, + PRIMARY_SURFACE_DCC_IND_BLK, 0, + PRIMARY_SURFACE_DCC_IND_BLK_C, 0, + SECONDARY_SURFACE_DCC_EN, 0, + SECONDARY_SURFACE_DCC_IND_BLK, 0, + SECONDARY_SURFACE_DCC_IND_BLK_C, 0); +} + void hubp3_dcc_control(struct hubp *hubp, bool enable, enum hubp_ind_block_size blk_size) { @@ -512,6 +528,7 @@ static struct hubp_funcs dcn30_hubp_funcs =3D { .hubp_in_blank =3D hubp1_in_blank, .hubp_soft_reset =3D hubp1_soft_reset, .hubp_set_flip_int =3D hubp1_set_flip_int, + .hubp_clear_tiling =3D hubp3_clear_tiling, }; =20 bool hubp3_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h b/drive= rs/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h index b010531a7fe88..cfb01bf340a1a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h @@ -297,6 +297,8 @@ void hubp3_read_state(struct hubp *hubp); =20 void hubp3_init(struct hubp *hubp); =20 +void hubp3_clear_tiling(struct hubp *hubp); + #endif /* __DC_HUBP_DCN30_H__ */ =20 =20 diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm= /amd/display/dc/inc/hw/hubp.h index 16580d6242789..d0878fc0cc948 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -275,6 +275,7 @@ struct hubp_funcs { enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + void (*hubp_clear_tiling)(struct hubp *hubp); }; =20 #endif base-commit: a5c2320151ff7cdf9ec50630d638a417ff927e31 --=20 2.46.1