From nobody Thu Nov 28 06:31:52 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FCA01474B7 for ; Fri, 4 Oct 2024 08:13:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029584; cv=none; b=tFY3ZHgDIVsNtmdZ6zIkUHTNmDPXkl9/jwAgXaqOhYtcieTvNUA/jZQQwN57MN7VjtYO/cNt8ddHLtkPhSX/W081yfinyFD8w/F5tAMap4pNEbtnY29BqzdBc5Ben19IjUBfOeLGn91XY3+hgC7YsHusxsxwu9a7+la+xsgu9ek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029584; c=relaxed/simple; bh=gvVSDsvyo1TmaScObCUC5qR6lwDSPViFk48MxY3oFVE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DQn75aqJls66N73xhOaXwplHcoXsKmdUVtjoomExfkHVofKFky3oBrrziZbqbWXSJfwwfIEX3gDuFkxTsS2Xb2nkS7hB4JNCynd1MuuSkWo8l2mVm2yHBzqKY7fPUE/+HKRWRnqD7ccanT3YFhD9rSV78DoUCuxXKR2FIy4w7n4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=Nl2v8GlW; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Nl2v8GlW" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-20b95359440so16238235ad.0 for ; Fri, 04 Oct 2024 01:13:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1728029582; x=1728634382; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k//ttICUIKEcy1fghMc4lQEx1N5cieQ1nYBPymANuBw=; b=Nl2v8GlWdT39McF3R5zZJknU4pEPh6xwRqLVz2/EwVNw0BUDMtgtE9LXuk2qxhFvbl eH5qTig6vcGvDNuBSo2dqSxSLZ2s4PoQzVjPxZmlcVNziRkoLSCEHkGhN6OlL8/MfpqV ltI+7VB1FLxdb2dJ4bZ4mThzLSSSiX8jQmeh0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728029582; x=1728634382; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k//ttICUIKEcy1fghMc4lQEx1N5cieQ1nYBPymANuBw=; b=YxIox7FkJHLXD9UeRlqEmh4z4fTvOMDSMeseFfdQ/0m5+aqZOUfy6H9X4gydRgQyx4 64IYLcJvybTufDxqDOIJiGoZ2LPkknFK9/GMXekERfd5qRHOStFKTHuYr3qBO6qFmZAI i0QNBWLyU0ykpI/3SOPphUJPoH0jMoJnDrwIRdseg0TkfazYDisvwXslODTHyUGmnK8Y r+I0tRH+DvfdxnKFrnM6WVXCqUIOMkBt20WJobPNOqYqGeY20X6qzdEGRMbhAbSxdeTF YtkF+FueBe2UmgpRJ5fTs4p23qCqQQA8iREz9f8I+GfiBXniPT5wTPBrtwOAWOimsNrq jaCw== X-Forwarded-Encrypted: i=1; AJvYcCVeJNN8or1himVH/4Dktqlkh/SsiQ6TbGVjyks85LVgeRgX/xHZ+zfQRlxwhoTP/dOefURqA2rzV4Vskc8=@vger.kernel.org X-Gm-Message-State: AOJu0YxonRAYVlIkFEUsVbTfeXCWVIQdakvGKgcPwIjLWPJISEvEcfwj CJ9v08+LNePRU3Y1RBnudZn1splhyzuJPK83z8xPeFc6YFyqHHnby6gBW1hXJg== X-Google-Smtp-Source: AGHT+IFRHqV6FfLFLe0okyQ++IPPIBtfxC3jtLsdN6L+JoOkwSnY0IC0bdlRq6YlFFz//4dbVriVWw== X-Received: by 2002:a17:903:18a:b0:20b:7d09:8c86 with SMTP id d9443c01a7336-20bfe49666fmr31501485ad.38.1728029582533; Fri, 04 Oct 2024 01:13:02 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:73bb:cecf:e651:2ce6]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20beefad264sm19401305ad.205.2024.10.04.01.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 01:13:01 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 6/9] arm64: dts: mediatek: mt8188: Add display nodes for vdosys0 Date: Fri, 4 Oct 2024 16:11:58 +0800 Message-ID: <20241004081218.55962-7-fshao@chromium.org> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog In-Reply-To: <20241004081218.55962-1-fshao@chromium.org> References: <20241004081218.55962-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdosys0 display nodes to support the internal display pipeline. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index a6a5d9cc875b..dae1cda42a14 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ / { aliases { gce0 =3D &gce0; gce1 =3D &gce1; + mutex0 =3D &mutex0; }; =20 cpus { @@ -2361,6 +2362,71 @@ jpeg_decoder: jpeg-decoder@1a040000 { power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; }; =20 + ovl0: ovl@1c000000 { + compatible =3D "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg =3D <0 0x1c000000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible =3D "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg =3D <0 0x1c002000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible =3D "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x1c003000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_COLOR0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible =3D "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccor= r"; + reg =3D <0 0x1c004000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_CCORR0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible =3D "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1c005000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_AAL0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible =3D "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamm= a"; + reg =3D <0 0x1c006000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible =3D "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x1c007000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_DITHER0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + disp_dsi0: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; @@ -2391,6 +2457,26 @@ disp_dsi1: dsi@1c012000 { status =3D "disabled"; }; =20 + mutex0: mutex@1c016000 { + compatible =3D "mediatek,mt8188-disp-mutex"; + reg =3D <0 0x1c016000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; + mediatek,gce-events =3D ; + }; + + postmask0: postmask@1c01a000 { + compatible =3D "mediatek,mt8188-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1c01a000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + }; + vdosys0: syscon@1c01d000 { compatible =3D "mediatek,mt8188-vdosys0", "syscon"; reg =3D <0 0x1c01d000 0 0x1000>; --=20 2.47.0.rc0.187.ge670bccf7e-goog