From nobody Thu Nov 28 06:38:36 2024 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79B3C145336 for ; Fri, 4 Oct 2024 08:12:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029579; cv=none; b=u8Yitt7rnRXsEFrwhd3UR0yjXJSzKZO4mnVvQJJyZBMntPZdQ2iOflxa5TBRNHcCSVHalJhkm54fUdFCI8W33I71yRKZEjZVZDcXZY1WJ8q1/R2xQSYvx/Rqj7BE8jysDOzZjN69i5nl+r/swfCWaw+6XPTuH6t713meX8IXfJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728029579; c=relaxed/simple; bh=oZFTAG6lDI9lg40xZBURgNdD7hUBbVyQ+nrJ2VEi5e4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R4iWVRn8QXOwzLnaHZeV8g8mbHYYZ1kueOraJX/iKoFYQTcrYFCi3Jzt6vnQhyZ18UOMdav7Qr1ISYUa6yK18veT4L3DbjgKHSw0GyQq8EOtDewsYdGJVlLjtzM/RyQyldif5HJgdYtbypee87JCxgQSaIEqcyqD2fK/RJS8HSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=X8+rmPGr; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="X8+rmPGr" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-20b64584fd4so18066995ad.1 for ; Fri, 04 Oct 2024 01:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1728029577; x=1728634377; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A9Y5BBz/AMy1C39cpZcaU1QFTTwbKgNIYIKdfEI0/z0=; b=X8+rmPGrvcm3NE5ydt7l3lkwGMnUd+ute0dGJedtAx9//DlfOEKRHfhQE+bKNLRv4s Ya22wYzT7x+komj5KP1ZUPFYpeo9ZYHzRG7TWIY7vlRud9Y9aDfon5Bav/mflfc8Vkof x+QlLzBhZ3l9TCxjtoDdWMzH/MNKeIT83LYh4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728029577; x=1728634377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A9Y5BBz/AMy1C39cpZcaU1QFTTwbKgNIYIKdfEI0/z0=; b=hwXH9Rm/UwvLqdpE+Ze6v03cZl9Ttpbn/ZuQ77ZpkTKev2x5pYnxPFrtvug9kpRvh1 K/r4QpJNe0OGFIWHxiWjyHSgo6cLtew609xqDM1OsL/HGSsUu9VlHgieuTNEVbke3pKf OfmuWJvvVSXaWT4/tBEj++A0UUt+rm8woDR3ENbZXwBInkfJuxwQmaEzKzToE5OldlGo 0BMh+NZJBcAqjKeCmwN0yI+L34j/zkNFGx2vPZFLOxQSQ/X2reLTYfqBIfLA9/QT4Cdn dqjuDPHbMFOrDmpF939ykzW3x9AXBeofM9qIUv2CK3uQeFcoeOpKDKR+ZVxl+OxQNufK j32w== X-Forwarded-Encrypted: i=1; AJvYcCVrYkMM1PpMmFouFu8Tz68BAEBs3o7nPv7ZTDemiIm2Yz+Lc7H9EnpN2fMyShv1vXsyg1oXyjPIwLsBhUo=@vger.kernel.org X-Gm-Message-State: AOJu0YyE9vZOs8RgG+B+iULoYoHwDMigUuDqsx5y2YvulLChDZp9wtA2 jdm5sB+EIB6rpqI0KaxXMxbc04ZXYSXSPheItwW0sFPGiy96skVoJ5lx7x5KQg== X-Google-Smtp-Source: AGHT+IFFL+xgmMgpwjPIMHZbqjcE9gF5N+ymzlSutBv/A9q8eic7+p3jY6kxs1URdAFCMFiCsPOt1g== X-Received: by 2002:a17:903:2452:b0:205:6552:1099 with SMTP id d9443c01a7336-20bfe022cd9mr20180335ad.8.1728029576897; Fri, 04 Oct 2024 01:12:56 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:73bb:cecf:e651:2ce6]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20beefad264sm19401305ad.205.2024.10.04.01.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 01:12:56 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 4/9] arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes Date: Fri, 4 Oct 2024 16:11:56 +0800 Message-ID: <20241004081218.55962-5-fshao@chromium.org> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog In-Reply-To: <20241004081218.55962-1-fshao@chromium.org> References: <20241004081218.55962-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index d39940ed6f5c..bb07d2629e08 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2198,6 +2198,64 @@ ccusys: clock-controller@17200000 { #clock-cells =3D <1>; }; =20 + video_decoder: video-decoder@18000000 { + compatible =3D "mediatek,mt8188-vcodec-dec"; + reg =3D <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges =3D <0 0 0 0x18000000 0 0x26000>; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + mediatek,scp =3D <&scp>; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x10000 0 0x800>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + larb23: smi@1800d000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1800d000 0 0x1000>; @@ -2249,6 +2307,31 @@ larb19: smi@1a010000 { mediatek,smi =3D <&vdo_smi_common>; }; =20 + video_encoder: video-encoder@1a020000 { + compatible =3D "mediatek,mt8188-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks =3D <&vencsys CLK_VENC1_VENC>; + clock-names =3D "venc_sel"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,scp =3D <&scp>; + }; + disp_dsi0: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; --=20 2.47.0.rc0.187.ge670bccf7e-goog