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AJvYcCVGvgtcXA1gpLGAd1K3axWdo4xk/w85i7E4v4vgtOmIF6UM9sJe/kYf11SmtGNiC17fbHTOKLCG/+wfN+hh@vger.kernel.org, AJvYcCWcgm63QwGv3lhIgZqu/0DpjiO/xzzZMWOIsknfuLVFHQTsXEFu20QVy0kXyqyR9C6X/dBn/vc70DVw@vger.kernel.org X-Gm-Message-State: AOJu0Yx2GrjDHoyh7wn0dIt7Kgd1S665WN67QHCH3gJuQtkpENWxwND+ WTH6PQ3Yz3XD/HgUk3QPlHO1Y38H3KvWvt8XoWX+28dHrA9oCC8c X-Google-Smtp-Source: AGHT+IELUKe6yfSED3d2riw0GkuDfFvQjLbY9zF5jW+IyaNrLOoL3ohm/AHnRCoVb/dkQ4mGPps5uw== X-Received: by 2002:a05:6a20:c997:b0:1d1:1795:4b43 with SMTP id adf61e73a8af0-1d6dfa476cemr3067956637.26.1728029195546; Fri, 04 Oct 2024 01:06:35 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71de9473894sm601482b3a.211.2024.10.04.01.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 01:06:35 -0700 (PDT) From: Inochi Amaoto To: Chen Wang , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Inochi Amaoto , Guo Ren , Lad Prabhakar , Hal Feng , Heikki Krogerus , Geert Uytterhoeven Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver Date: Fri, 4 Oct 2024 16:05:56 +0800 Message-ID: <20241004080557.2262872-3-inochiama@gmail.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004080557.2262872-1-inochiama@gmail.com> References: <20241004080557.2262872-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an enhanced implementation of the RISC-V ACLINT SSWI specification. This device allows the system to send ipi via fast device interface. Signed-off-by: Inochi Amaoto --- drivers/irqchip/Kconfig | 10 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-thead-c900-aclint-sswi.c | 169 +++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 181 insertions(+) create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 341cd9ca5a05..32671385cbb7 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -611,6 +611,16 @@ config STARFIVE_JH8100_INTC If you don't know what to do here, say Y. +config THEAD_C900_ACLINT_SSWI + bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + help + This enables support for T-HEAD specific ACLINT SSWI device + support. + + If you don't know what to do here, say Y. + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e3679ec2b9f7..583418261253 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi= .o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o +obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) +=3D irq-thead-c900-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o obj-$(CONFIG_IMX_MU_MSI) +=3D irq-imx-mu-msi.o diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip= /irq-thead-c900-aclint-sswi.c new file mode 100644 index 000000000000..7bd06369b409 --- /dev/null +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Inochi Amaoto + */ + +#define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ACLINT_xSWI_REGISTER_SIZE 4 + +struct aclint_sswi_cpu_config { + void __iomem *reg; + u32 offset; +}; + +static int sswi_ipi_virq __ro_after_init; +static DEFINE_PER_CPU(struct aclint_sswi_cpu_config, sswi_cpus); + +static void thead_aclint_sswi_ipi_send(unsigned int cpu) +{ + struct aclint_sswi_cpu_config *config =3D per_cpu_ptr(&sswi_cpus, cpu); + + writel_relaxed(0x1, config->reg + config->offset); +} + +static void thead_aclint_sswi_ipi_clear(void) +{ + unsigned int cpu =3D smp_processor_id(); + struct aclint_sswi_cpu_config *config =3D per_cpu_ptr(&sswi_cpus, cpu); + + writel_relaxed(0x0, config->reg + config->offset); +} + +static void thead_aclint_sswi_ipi_handle(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + csr_clear(CSR_IP, IE_SIE); + thead_aclint_sswi_ipi_clear(); + + ipi_mux_process(); + + chained_irq_exit(chip, desc); +} + +static int aclint_sswi_ipi_starting_cpu(unsigned int cpu) +{ + enable_percpu_irq(sswi_ipi_virq, irq_get_trigger_type(sswi_ipi_virq)); + return 0; +} + +static int aclint_sswi_parse_irq(struct fwnode_handle *fwnode, + void __iomem *reg) +{ + struct of_phandle_args parent; + unsigned long hartid; + u32 contexts, i; + int rc, cpu; + struct aclint_sswi_cpu_config *config; + + contexts =3D of_irq_count(to_of_node(fwnode)); + if (WARN_ON(!(contexts))) { + pr_err("%pfwP: no ACLINT SSWI context available\n", fwnode); + return -EINVAL; + } + + for (i =3D 0; i < contexts; i++) { + rc =3D of_irq_parse_one(to_of_node(fwnode), i, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, &hartid); + if (rc) + return rc; + + if (parent.args[0] !=3D RV_IRQ_SOFT) + return -ENOTSUPP; + + cpu =3D riscv_hartid_to_cpuid(hartid); + config =3D per_cpu_ptr(&sswi_cpus, cpu); + + config->offset =3D i * ACLINT_xSWI_REGISTER_SIZE; + config->reg =3D reg; + } + + pr_info("%pfwP: register %u CPU\n", fwnode, contexts); + + return 0; +} + +static int __init aclint_sswi_probe(struct fwnode_handle *fwnode) +{ + void __iomem *reg; + struct irq_domain *domain; + int virq, rc; + + if (!is_of_node(fwnode)) + return -EINVAL; + + reg =3D of_iomap(to_of_node(fwnode), 0); + if (!reg) + return -ENOMEM; + + /* Parse SSWI setting */ + rc =3D aclint_sswi_parse_irq(fwnode, reg); + if (rc < 0) + return rc; + + /* If mulitple SSWI devices are present, do not register irq again */ + if (sswi_ipi_virq) + return 0; + + /* Find and create irq domain */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_A= NY); + if (!domain) { + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); + return -ENOENT; + } + + sswi_ipi_virq =3D irq_create_mapping(domain, RV_IRQ_SOFT); + if (!sswi_ipi_virq) { + pr_err("unable to create ACLINT SSWI IRQ mapping\n"); + return -ENOMEM; + } + + /* Register SSWI irq and handler */ + virq =3D ipi_mux_create(BITS_PER_BYTE, thead_aclint_sswi_ipi_send); + if (virq <=3D 0) { + pr_err("unable to create muxed IPIs\n"); + irq_dispose_mapping(sswi_ipi_virq); + return virq < 0 ? virq : -ENOMEM; + } + + irq_set_chained_handler(sswi_ipi_virq, thead_aclint_sswi_ipi_handle); + + cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, + "irqchip/thead-aclint-sswi:starting", + aclint_sswi_ipi_starting_cpu, NULL); + + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + + /* Announce that SSWI is providing IPIs */ + pr_info("providing IPIs using THEAD ACLINT SSWI\n"); + + return 0; +} + +static int __init aclint_sswi_early_probe(struct device_node *node, + struct device_node *parent) +{ + return aclint_sswi_probe(&node->fwnode); +} + +IRQCHIP_DECLARE(thead_aclint_sswi, "thead,c900-aclint-sswi", aclint_sswi_e= arly_probe); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 2361ed4d2b15..799052249c7b 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -147,6 +147,7 @@ enum cpuhp_state { CPUHP_AP_IRQ_EIOINTC_STARTING, CPUHP_AP_IRQ_AVECINTC_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY, -- 2.46.2