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Fri, 04 Oct 2024 02:06:44 -0700 (PDT) Received: from [127.0.1.1] ([82.77.84.93]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d081f7006sm2833945f8f.13.2024.10.04.02.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Oct 2024 02:06:44 -0700 (PDT) From: Abel Vesa Date: Fri, 04 Oct 2024 12:06:33 +0300 Subject: [PATCH v2] arm64: dts: qcom: x1e80100: Switch PCIe 6a to 4 lanes mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241004-x1e80100-dts-fixes-pcie6a-v2-1-3af9ff7a5a71@linaro.org> X-B4-Tracking: v=1; b=H4sIABiw/2YC/32NwQ6CQAxEf4X0bM12EVFP/ofhsAsFmhiW7BKCI fvvVj7A27yZznSHxFE4waPYIfIqScKkYE8FtKObBkbplMEaeyFjStyIb0YVdkvCXjZOOLfCV4f +3hPVGneVB+3PkY9c669GeZS0hPg5Xq30c49VU5X0Z3UltEhVXbJvHevZ8y2Ti+Ec4gBNzvkLd 9wGRsMAAAA= X-Change-ID: 20241003-x1e80100-dts-fixes-pcie6a-b9f1171e8d5b To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The PCIe 6a controller and PHY can be configured in 4-lanes mode or 2-lanes mode. For 4-lanes mode, it fetches the lanes provided by PCIe 6b. For 2-lanes mode, PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. Configure it in 4-lane mode and then each board can configure it depending on the design. Both the QCP and CRD boards, currently upstream, use PCIe 6a for NVMe in 4-lane mode. Mark the controller as 4-lane as well. This is the last change needed in order to support NVMe with Gen4 4-lanes on all existing X Elite boards. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- Changes in v2: - Re-worded the commit message according to Johan's suggestions - Dropped the clocks changes. - Dropped the fixes tag as this relies on the Gen4 4-lanes stability patchset which has been only merged in 6.12, so backporting this patch would break NVMe support for all platforms. - Link to v1: https://lore.kernel.org/r/20240531-x1e80100-dts-fixes-pcie6a-= v1-2-1573ebcae1e8@linaro.org --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a36076e3c56b5b8815eb41ec55e2e1e5bd878201..4ec712cb7a26d8fe434631cf159= 49524fd22c7d9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2931,7 +2931,7 @@ pcie6a: pci@1bf8000 { dma-coherent; =20 linux,pci-domain =3D <6>; - num-lanes =3D <2>; + num-lanes =3D <4>; =20 interrupts =3D , , @@ -2997,8 +2997,9 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, }; =20 pcie6a_phy: phy@1bfc000 { - compatible =3D "qcom,x1e80100-qmp-gen4x2-pcie-phy"; - reg =3D <0 0x01bfc000 0 0x2000>; + compatible =3D "qcom,x1e80100-qmp-gen4x4-pcie-phy"; + reg =3D <0 0x01bfc000 0 0x2000>, + <0 0x01bfe000 0 0x2000>; =20 clocks =3D <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, @@ -3021,6 +3022,8 @@ pcie6a_phy: phy@1bfc000 { =20 power-domains =3D <&gcc GCC_PCIE_6_PHY_GDSC>; =20 + qcom,4ln-config-sel =3D <&tcsr 0x1a000 0>; + #clock-cells =3D <0>; clock-output-names =3D "pcie6a_pipe_clk"; =20 --- base-commit: c02d24a5af66a9806922391493205a344749f2c4 change-id: 20241003-x1e80100-dts-fixes-pcie6a-b9f1171e8d5b Best regards, --=20 Abel Vesa