From nobody Thu Nov 28 04:49:09 2024 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7807C1D0B8B for ; Thu, 3 Oct 2024 23:43:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727999024; cv=none; b=Cp8UEWcczJFRUMeU/RJqA0S3VeES2yho80ZeGQG9d6z90J1JgeKLsiR2bzrBO4ajOQ+3rqfHZONe7iwHiYOe1b87hhHIfeubzj7x6keIRxzmKdJZTiFlwKh2fVyxGTcCEd48Ondci2Iho2loVO2mZ4jjCMnxO3nP7bvndy7I8oI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727999024; c=relaxed/simple; bh=dCT8bXCAqzzFJVCOs7D2QLba2AuX/LxeOumRe2jwP14=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=cfNusvtWESDnNzpvUSAdvkkztqRB9EngwmnCqekd38SIu7cU/bNqWnqIQ1YcqzjnQbV04tHVs+cML8itdXsLSM2fiw9/A9BVDOUnrqg6atBXGmROJutZve1h3jgVX6OOmSgo9MWdUuWaTeBrED9Jn3M5P1lAYE0g6lgHZqbOnKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=j/DfmBlF; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="j/DfmBlF" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-20b6a967007so12296365ad.2 for ; Thu, 03 Oct 2024 16:43:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1727999023; x=1728603823; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=6V2q4amWCHB6J/4atN9JkqFjKadmMrC6jiYsYmH9GeA=; b=j/DfmBlF0XueeTAUmTobLtoKu+JuPt3/lsv58+IYI2kNwnKRXj85Qmei653K0dtRNf colbLIEw0mms1FjK9K/MxrF8oeaHfmvxzUWqwNdJsJLyu0Poff5pgEy6RU5cp/LfKwbi qQqDqGIdRmLWlB3OmywPAvK1bYQ0ceKcbI+YwL7iXgrkUGfdps7nCQOcygJw17KNqHnm zytZ1H6lhiR4zd7F+Y0WJLorGOjAnX/YQ5ZurmyDC2swCdQAiK++iOuIA5I13ZoKi9Sc 3GiCpmN0aelB2i4OvVb3Gde2mKCsLejr9dYySL+cpe2OdOYs1sAtkJp4Pm7QHrjwirak BbfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727999023; x=1728603823; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6V2q4amWCHB6J/4atN9JkqFjKadmMrC6jiYsYmH9GeA=; b=klzfntqx0D3RX5Thk9NOdX/pPGB6naOI6H4covZToO5zOFERtDA2sCfoStcO1WrIDJ KJBw1Ib0KqOYX4NV5dyTDSUipa4T1fzRL5DXG7XWo/F+dhzwc7twH1vAcU5C7t/nu8F0 hzfWGtTa8iKMNe3dmL577xgTd2KTL+gAQAvfsmZ5/BiPd+oQU5rv53wDqlNlgTWFTDjy lBbbZ4xiTBi7OHCNlpYSg/DznPLqQ7zc2WL2egVmaxy+yFK0MdJljc8nXfqC/hZwVSRE UAgSPV6h9UGmWw6OAWkYjyze7ICBeum4O60Rr7iLs0q/xXiunmEQ3gJxcVON2Sl92Jb2 fojQ== X-Forwarded-Encrypted: i=1; AJvYcCWl7QsB94N4vcPlMj72uOTQmntwmIbjy3qZeO3373izQo93ueZVZ2XIRmJUxpPiSVkG7OoOrU5oTxO33W0=@vger.kernel.org X-Gm-Message-State: AOJu0YzOHOx8dSEH5QBiexEGh4ryjzLlxEC87I5mbxj9/+Ic5Xlh3sbk xD6Haym7knX0UE4WVFDKF895RGCT9IlmvACBHghCjc4gGsFFteapqiYwYjsOGhwwBUW4YYCJ+yz 3KA== X-Google-Smtp-Source: AGHT+IFaPFq1x4myrDRmgES6KGTmO/IX8Xo50bZDsQhg0x5tM5p7famkM2K8G8qgEWxTrXonLa0y6KUkJmc= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:e80c:b0:20b:9df1:54a3 with SMTP id d9443c01a7336-20bff1dfc9fmr8035ad.8.1727999022648; Thu, 03 Oct 2024 16:43:42 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:27 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-2-seanjc@google.com> Subject: [PATCH 01/11] KVM: selftests: Fix out-of-bounds reads in CPUID test's array lookups From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When looking for a "mangled", i.e. dynamic, CPUID entry, terminate the walk based on the number of array _entries_, not the size in bytes of the array. Iterating based on the total size of the array can result in false passes, e.g. if the random data beyond the array happens to match a CPUID entry's function and index. Fixes: fb18d053b7f8 ("selftest: kvm: x86: test KVM_GET_CPUID2 and guest vis= ible CPUIDs against KVM_GET_SUPPORTED_CPUID") Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/cpuid_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86_64/cpuid_test.c b/tools/testin= g/selftests/kvm/x86_64/cpuid_test.c index 8c579ce714e9..fec03b11b059 100644 --- a/tools/testing/selftests/kvm/x86_64/cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/cpuid_test.c @@ -60,7 +60,7 @@ static bool is_cpuid_mangled(const struct kvm_cpuid_entry= 2 *entrie) { int i; =20 - for (i =3D 0; i < sizeof(mangled_cpuids); i++) { + for (i =3D 0; i < ARRAY_SIZE(mangled_cpuids); i++) { if (mangled_cpuids[i].function =3D=3D entrie->function && mangled_cpuids[i].index =3D=3D entrie->index) return true; --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DC1C1D0E39 for ; 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Thu, 03 Oct 2024 16:43:44 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:28 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-3-seanjc@google.com> Subject: [PATCH 02/11] KVM: selftests: Precisely mask off dynamic fields in CPUID test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When comparing vCPU CPUID entries against KVM's supported CPUID, mask off only the dynamic fields/bits instead of skipping the entire entry. Precisely masking bits isn't meaningfully more difficult than skipping entire entries, and will be necessary to maintain test coverage when a future commit enables OSXSAVE by default, i.e. makes one bit in all of CPUID.0x1 dynamic. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- .../testing/selftests/kvm/x86_64/cpuid_test.c | 61 +++++++++++-------- 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/cpuid_test.c b/tools/testin= g/selftests/kvm/x86_64/cpuid_test.c index fec03b11b059..f7fdcef5fa59 100644 --- a/tools/testing/selftests/kvm/x86_64/cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/cpuid_test.c @@ -12,17 +12,16 @@ #include "kvm_util.h" #include "processor.h" =20 -/* CPUIDs known to differ */ -struct { - u32 function; - u32 index; -} mangled_cpuids[] =3D { - /* - * These entries depend on the vCPU's XCR0 register and IA32_XSS MSR, - * which are not controlled for by this test. - */ - {.function =3D 0xd, .index =3D 0}, - {.function =3D 0xd, .index =3D 1}, +struct cpuid_mask { + union { + struct { + u32 eax; + u32 ebx; + u32 ecx; + u32 edx; + }; + u32 regs[4]; + }; }; =20 static void test_guest_cpuids(struct kvm_cpuid2 *guest_cpuid) @@ -56,17 +55,23 @@ static void guest_main(struct kvm_cpuid2 *guest_cpuid) GUEST_DONE(); } =20 -static bool is_cpuid_mangled(const struct kvm_cpuid_entry2 *entrie) +static struct cpuid_mask get_const_cpuid_mask(const struct kvm_cpuid_entry= 2 *entry) { - int i; + struct cpuid_mask mask; =20 - for (i =3D 0; i < ARRAY_SIZE(mangled_cpuids); i++) { - if (mangled_cpuids[i].function =3D=3D entrie->function && - mangled_cpuids[i].index =3D=3D entrie->index) - return true; + memset(&mask, 0xff, sizeof(mask)); + + switch (entry->function) { + case 0xd: + /* + * CPUID.0xD.{0,1}.EBX enumerate XSAVE size based on the current + * XCR0 and IA32_XSS MSR values. + */ + if (entry->index < 2) + mask.ebx =3D 0; + break; } - - return false; + return mask; } =20 static void compare_cpuids(const struct kvm_cpuid2 *cpuid1, @@ -79,6 +84,8 @@ static void compare_cpuids(const struct kvm_cpuid2 *cpuid= 1, "CPUID nent mismatch: %d vs. %d", cpuid1->nent, cpuid2->nent); =20 for (i =3D 0; i < cpuid1->nent; i++) { + struct cpuid_mask mask; + e1 =3D &cpuid1->entries[i]; e2 =3D &cpuid2->entries[i]; =20 @@ -88,15 +95,19 @@ static void compare_cpuids(const struct kvm_cpuid2 *cpu= id1, i, e1->function, e1->index, e1->flags, e2->function, e2->index, e2->flags); =20 - if (is_cpuid_mangled(e1)) - continue; + /* Mask off dynamic bits, e.g. OSXSAVE, when comparing entries. */ + mask =3D get_const_cpuid_mask(e1); =20 - TEST_ASSERT(e1->eax =3D=3D e2->eax && e1->ebx =3D=3D e2->ebx && - e1->ecx =3D=3D e2->ecx && e1->edx =3D=3D e2->edx, + TEST_ASSERT((e1->eax & mask.eax) =3D=3D (e2->eax & mask.eax) && + (e1->ebx & mask.ebx) =3D=3D (e2->ebx & mask.ebx) && + (e1->ecx & mask.ecx) =3D=3D (e2->ecx & mask.ecx) && + (e1->edx & mask.edx) =3D=3D (e2->edx & mask.edx), "CPUID 0x%x.%x differ: 0x%x:0x%x:0x%x:0x%x vs 0x%x:0x%x:0x%x:0x%x", e1->function, e1->index, - e1->eax, e1->ebx, e1->ecx, e1->edx, - e2->eax, e2->ebx, e2->ecx, e2->edx); + e1->eax & mask.eax, e1->ebx & mask.ebx, + e1->ecx & mask.ecx, e1->edx & mask.edx, + e2->eax & mask.eax, e2->ebx & mask.ebx, + e2->ecx & mask.ecx, e2->edx & mask.edx); } } =20 --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69F601D14EC for ; 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Thu, 03 Oct 2024 16:43:46 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:29 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-4-seanjc@google.com> Subject: [PATCH 03/11] KVM: selftests: Mask off OSPKE and OSXSAVE when comparing CPUID entries From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Mask off OSPKE and OSXSAVE, which are toggled based on corresponding CR4 enabling bits, when comparing vCPU CPUID against KVM's supported CPUID. This will allow setting OSXSAVE by default when creating vCPUs, without causing test failures (KVM doesn't enumerate OSXSAVE=3D1). Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/cpuid_test.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/cpuid_test.c b/tools/testin= g/selftests/kvm/x86_64/cpuid_test.c index f7fdcef5fa59..7b3fda6842bc 100644 --- a/tools/testing/selftests/kvm/x86_64/cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/cpuid_test.c @@ -62,6 +62,12 @@ static struct cpuid_mask get_const_cpuid_mask(const stru= ct kvm_cpuid_entry2 *ent memset(&mask, 0xff, sizeof(mask)); =20 switch (entry->function) { + case 0x1: + mask.regs[X86_FEATURE_OSXSAVE.reg] &=3D ~BIT(X86_FEATURE_OSXSAVE.bit); + break; + case 0x7: + mask.regs[X86_FEATURE_OSPKE.reg] &=3D ~BIT(X86_FEATURE_OSPKE.bit); + break; case 0xd: /* * CPUID.0xD.{0,1}.EBX enumerate XSAVE size based on the current --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2815B1D1E60 for ; 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Thu, 03 Oct 2024 16:43:48 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:30 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-5-seanjc@google.com> Subject: [PATCH 04/11] KVM: selftests: Rework OSXSAVE CR4=>CPUID test to play nice with AVX insns From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rework the CR4/CPUID sync test to clear CR4.OSXSAVE, do CPUID, and restore CR4.OSXSAVE in assembly, so that there is zero chance of AVX instructions being executed while CR4.OSXSAVE is disabled. This will allow enabling CR4.OSXSAVE by default for selftests vCPUs as a general means of playing nice with AVX instructions. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- .../kvm/x86_64/cr4_cpuid_sync_test.c | 46 +++++++++++++------ 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c b/too= ls/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c index 624dc725e14d..da818afb7031 100644 --- a/tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c +++ b/tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c @@ -19,15 +19,14 @@ #include "kvm_util.h" #include "processor.h" =20 -static inline bool cr4_cpuid_is_sync(void) -{ - uint64_t cr4 =3D get_cr4(); - - return (this_cpu_has(X86_FEATURE_OSXSAVE) =3D=3D !!(cr4 & X86_CR4_OSXSAVE= )); -} +#define MAGIC_HYPERCALL_PORT 0x80 =20 static void guest_code(void) { + u32 regs[4] =3D { + [KVM_CPUID_EAX] =3D X86_FEATURE_OSXSAVE.function, + [KVM_CPUID_ECX] =3D X86_FEATURE_OSXSAVE.index, + }; uint64_t cr4; =20 /* turn on CR4.OSXSAVE */ @@ -36,13 +35,29 @@ static void guest_code(void) set_cr4(cr4); =20 /* verify CR4.OSXSAVE =3D=3D CPUID.OSXSAVE */ - GUEST_ASSERT(cr4_cpuid_is_sync()); + GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); =20 - /* notify hypervisor to change CR4 */ - GUEST_SYNC(0); + /* + * Notify hypervisor to clear CR4.0SXSAVE, do CPUID and save output, + * and then restore CR4. Do this all in assembly to ensure no AVX + * instructions are executed while OSXSAVE=3D0. + */ + asm volatile ( + "out %%al, $" __stringify(MAGIC_HYPERCALL_PORT) "\n\t" + "cpuid\n\t" + "mov %%rdi, %%cr4\n\t" + : "+a" (regs[KVM_CPUID_EAX]), + "=3Db" (regs[KVM_CPUID_EBX]), + "+c" (regs[KVM_CPUID_ECX]), + "=3Dd" (regs[KVM_CPUID_EDX]) + : "D" (get_cr4()) + ); =20 - /* check again */ - GUEST_ASSERT(cr4_cpuid_is_sync()); + /* Verify KVM cleared OSXSAVE in CPUID when it was cleared in CR4. */ + GUEST_ASSERT(!(regs[X86_FEATURE_OSXSAVE.reg] & BIT(X86_FEATURE_OSXSAVE.bi= t))); + + /* Verify restoring CR4 also restored OSXSAVE in CPUID. */ + GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); =20 GUEST_DONE(); } @@ -62,13 +77,16 @@ int main(int argc, char *argv[]) vcpu_run(vcpu); TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); =20 - switch (get_ucall(vcpu, &uc)) { - case UCALL_SYNC: + if (vcpu->run->io.port =3D=3D MAGIC_HYPERCALL_PORT && + vcpu->run->io.direction =3D=3D KVM_EXIT_IO_OUT) { /* emulate hypervisor clearing CR4.OSXSAVE */ vcpu_sregs_get(vcpu, &sregs); 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charset="utf-8" To play nice with compilers generating AVX instructions, set CR4.OSXSAVE and configure XCR0 by default when creating selftests vCPUs. Some distros have switched gcc to '-march=3Dx86-64-v3' by default, and while it's hard to find a CPU which doesn't support AVX today, many KVM selftests fail with =3D=3D=3D=3D Test Assertion Failure =3D=3D=3D=3D lib/x86_64/processor.c:570: Unhandled exception in guest pid=3D72747 tid=3D72747 errno=3D4 - Interrupted system call Unhandled exception '0x6' at guest RIP '0x4104f7' due to selftests not enabling AVX by default for the guest. The failure is easy to reproduce elsewhere with: $ make clean && CFLAGS=3D'-march=3Dx86-64-v3' make -j && ./x86_64/kvm_pv= _test E.g. gcc-13 with -march=3Dx86-64-v3 compiles this chunk from selftests' kvm_fixup_exception(): regs->rip =3D regs->r11; regs->r9 =3D regs->vector; regs->r10 =3D regs->error_code; into this monstronsity (which is clever, but oof): 405313: c4 e1 f9 6e c8 vmovq %rax,%xmm1 405318: 48 89 68 08 mov %rbp,0x8(%rax) 40531c: 48 89 e8 mov %rbp,%rax 40531f: c4 c3 f1 22 c4 01 vpinsrq $0x1,%r12,%xmm1,%xmm0 405325: 49 89 6d 38 mov %rbp,0x38(%r13) 405329: c5 fa 7f 45 00 vmovdqu %xmm0,0x0(%rbp) Alternatively, KVM selftests could explicitly restrict the compiler to -march=3Dx86-64-v2, but odds are very good that punting on AVX enabling will simply result in tests that "need" AVX doing their own thing, e.g. there are already three or so additional cleanups that can be done on top. Reported-by: Vitaly Kuznetsov Closes: https://lore.kernel.org/all/20240920154422.2890096-1-vkuznets@redha= t.com Signed-off-by: Sean Christopherson --- .../selftests/kvm/include/x86_64/processor.h | 5 ++++ .../selftests/kvm/lib/x86_64/processor.c | 24 +++++++++++++++++++ .../selftests/kvm/x86_64/xcr0_cpuid_test.c | 6 ++--- 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools= /testing/selftests/kvm/include/x86_64/processor.h index e247f99e0473..645200e95f89 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -1049,6 +1049,11 @@ static inline void vcpu_set_cpuid(struct kvm_vcpu *v= cpu) vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); } =20 +static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) +{ + vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); +} + void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, struct kvm_x86_cpu_property property, uint32_t value); diff --git a/tools/testing/selftests/kvm/lib/x86_64/processor.c b/tools/tes= ting/selftests/kvm/lib/x86_64/processor.c index 974bcd2df6d7..636b29ba8985 100644 --- a/tools/testing/selftests/kvm/lib/x86_64/processor.c +++ b/tools/testing/selftests/kvm/lib/x86_64/processor.c @@ -506,6 +506,8 @@ static void vcpu_init_sregs(struct kvm_vm *vm, struct k= vm_vcpu *vcpu) =20 sregs.cr0 =3D X86_CR0_PE | X86_CR0_NE | X86_CR0_PG; sregs.cr4 |=3D X86_CR4_PAE | X86_CR4_OSFXSR; + if (kvm_cpu_has(X86_FEATURE_XSAVE)) + sregs.cr4 |=3D X86_CR4_OSXSAVE; sregs.efer |=3D (EFER_LME | EFER_LMA | EFER_NX); =20 kvm_seg_set_unusable(&sregs.ldt); @@ -519,6 +521,20 @@ static void vcpu_init_sregs(struct kvm_vm *vm, struct = kvm_vcpu *vcpu) vcpu_sregs_set(vcpu, &sregs); } =20 +static void vcpu_init_xcrs(struct kvm_vm *vm, struct kvm_vcpu *vcpu) +{ + struct kvm_xcrs xcrs =3D { + .nr_xcrs =3D 1, + .xcrs[0].xcr =3D 0, + .xcrs[0].value =3D kvm_cpu_supported_xcr0(), + }; + + if (!kvm_cpu_has(X86_FEATURE_XSAVE)) + return; + + vcpu_xcrs_set(vcpu, &xcrs); +} + static void set_idt_entry(struct kvm_vm *vm, int vector, unsigned long add= r, int dpl, unsigned short selector) { @@ -675,6 +691,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, ui= nt32_t vcpu_id) vcpu =3D __vm_vcpu_add(vm, vcpu_id); vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid()); vcpu_init_sregs(vm, vcpu); + vcpu_init_xcrs(vm, vcpu); =20 /* Setup guest general purpose registers */ vcpu_regs_get(vcpu, ®s); @@ -686,6 +703,13 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u= int32_t vcpu_id) mp_state.mp_state =3D 0; vcpu_mp_state_set(vcpu, &mp_state); =20 + /* + * Refresh CPUID after setting SREGS and XCR0, so that KVM's "runtime" + * updates to guest CPUID, e.g. for OSXSAVE and XSAVE state size, are + * reflected into selftests' vCPU CPUID cache, i.e. so that the cache + * is consistent with vCPU state. + */ + vcpu_get_cpuid(vcpu); return vcpu; } =20 diff --git a/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c b/tools/t= esting/selftests/kvm/x86_64/xcr0_cpuid_test.c index 95ce192d0753..a4aecdc77da5 100644 --- a/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c @@ -48,16 +48,16 @@ do { \ =20 static void guest_code(void) { - uint64_t xcr0_reset; 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charset="utf-8" Now that KVM selftests enable all supported XCR0 features by default, add a testcase to the XCR0 vs. CPUID test to verify that the guest can disable everything except the legacy FPU in XCR0, and then re-enable the full feature set, which is kinda sorta what the test did before XCR0 was setup by default. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c b/tools/t= esting/selftests/kvm/x86_64/xcr0_cpuid_test.c index a4aecdc77da5..c8a5c5e51661 100644 --- a/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/xcr0_cpuid_test.c @@ -79,6 +79,11 @@ static void guest_code(void) ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, XFEATURE_MASK_XTILE); =20 + vector =3D xsetbv_safe(0, XFEATURE_MASK_FP); + __GUEST_ASSERT(!vector, + "Expected success on XSETBV(FP), got vector '0x%x'", + vector); + vector =3D xsetbv_safe(0, supported_xcr0); __GUEST_ASSERT(!vector, "Expected success on XSETBV(0x%lx), got vector '0x%x'", --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 487E61D26FF for ; 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Thu, 03 Oct 2024 16:43:53 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:33 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-8-seanjc@google.com> Subject: [PATCH 07/11] KVM: selftests: Drop manual CR4.OSXSAVE enabling from CR4/CPUID sync test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that CR4.OSXSAVE is enabled by default, drop the manual enabling from CR4/CPUID sync test and instead assert that CR4.OSXSAVE is enabled. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c b/too= ls/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c index da818afb7031..28cc66454601 100644 --- a/tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c +++ b/tools/testing/selftests/kvm/x86_64/cr4_cpuid_sync_test.c @@ -27,12 +27,9 @@ static void guest_code(void) [KVM_CPUID_EAX] =3D X86_FEATURE_OSXSAVE.function, [KVM_CPUID_ECX] =3D X86_FEATURE_OSXSAVE.index, }; - uint64_t cr4; =20 - /* turn on CR4.OSXSAVE */ - cr4 =3D get_cr4(); - cr4 |=3D X86_CR4_OSXSAVE; - set_cr4(cr4); + /* CR4.OSXSAVE should be enabled by default (for selftests vCPUs). */ + GUEST_ASSERT(get_cr4() & X86_CR4_OSXSAVE); =20 /* verify CR4.OSXSAVE =3D=3D CPUID.OSXSAVE */ GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8295E1CF7C9 for ; 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Thu, 03 Oct 2024 16:43:55 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:34 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-9-seanjc@google.com> Subject: [PATCH 08/11] KVM: selftests: Drop manual XCR0 configuration from AMX test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that CR4.OSXSAVE and XCR0 are setup by default, drop the manual enabling of OXSAVE and XTILE from the AMX test. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/amx_test.c | 23 ++++--------------- 1 file changed, 4 insertions(+), 19 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/= selftests/kvm/x86_64/amx_test.c index 903940c54d2d..f4ce5a185a7d 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -86,6 +86,8 @@ static inline void __xsavec(struct xstate *xstate, uint64= _t rfbm) =20 static void check_xtile_info(void) { + GUEST_ASSERT((xgetbv(0) & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTILE= ); + GUEST_ASSERT(this_cpu_has_p(X86_PROPERTY_XSTATE_MAX_SIZE_XCR0)); GUEST_ASSERT(this_cpu_property(X86_PROPERTY_XSTATE_MAX_SIZE_XCR0) <=3D XS= AVE_SIZE); =20 @@ -122,29 +124,12 @@ static void set_tilecfg(struct tile_config *cfg) } } =20 -static void init_regs(void) -{ - uint64_t cr4, xcr0; - - GUEST_ASSERT(this_cpu_has(X86_FEATURE_XSAVE)); - - /* turn on CR4.OSXSAVE */ - cr4 =3D get_cr4(); - cr4 |=3D X86_CR4_OSXSAVE; - set_cr4(cr4); - GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); - - xcr0 =3D xgetbv(0); - xcr0 |=3D XFEATURE_MASK_XTILE; - xsetbv(0x0, xcr0); - GUEST_ASSERT((xgetbv(0) & XFEATURE_MASK_XTILE) =3D=3D XFEATURE_MASK_XTILE= ); -} - static void __attribute__((__flatten__)) guest_code(struct tile_config *am= x_cfg, struct tile_data *tiledata, struct xstate *xstate) { - init_regs(); + GUEST_ASSERT(this_cpu_has(X86_FEATURE_XSAVE) && + this_cpu_has(X86_FEATURE_OSXSAVE)); check_xtile_info(); GUEST_SYNC(1); =20 --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE251D0941 for ; Thu, 3 Oct 2024 23:43:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; 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Thu, 03 Oct 2024 16:43:57 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:35 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-10-seanjc@google.com> Subject: [PATCH 09/11] KVM: selftests: Drop manual XCR0 configuration from state test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that CR4.OSXSAVE and XCR0 are setup by default, drop the manual enabling from the state test, which is fully redundant with the default behavior. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/state_test.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/state_test.c b/tools/testin= g/selftests/kvm/x86_64/state_test.c index 1c756db329e5..141b7fc0c965 100644 --- a/tools/testing/selftests/kvm/x86_64/state_test.c +++ b/tools/testing/selftests/kvm/x86_64/state_test.c @@ -145,11 +145,6 @@ static void __attribute__((__flatten__)) guest_code(vo= id *arg) =20 memset(buffer, 0xcc, sizeof(buffer)); =20 - set_cr4(get_cr4() | X86_CR4_OSXSAVE); - GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); - - xsetbv(0, xgetbv(0) | supported_xcr0); - /* * Modify state for all supported xfeatures to take them out of * their "init" state, i.e. to make them show up in XSTATE_BV. --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Thu Nov 28 04:49:09 2024 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E73F61D2B06 for ; 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Thu, 03 Oct 2024 16:43:59 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:36 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-11-seanjc@google.com> Subject: [PATCH 10/11] KVM: selftests: Drop manual XCR0 configuration from SEV smoke test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that CR4.OSXSAVE and XCR0 are setup by default, drop the manual enabling from the SEV smoke test that validates FPU state can be transferred into the VMSA. In guest_code_xsave(), explicitly set the Requested-Feature Bitmask (RFBM) to exactly XFEATURE_MASK_X87_AVX instead of relying on the host side of things to enable only X87_AVX features in guest XCR0. I.e. match the RFBM for the host XSAVE. Signed-off-by: Sean Christopherson --- .../testing/selftests/kvm/x86_64/sev_smoke_test.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/sev_smoke_test.c b/tools/te= sting/selftests/kvm/x86_64/sev_smoke_test.c index 2e9197eb1652..965fc362dee3 100644 --- a/tools/testing/selftests/kvm/x86_64/sev_smoke_test.c +++ b/tools/testing/selftests/kvm/x86_64/sev_smoke_test.c @@ -41,8 +41,8 @@ static void guest_sev_code(void) /* Stash state passed via VMSA before any compiled code runs. */ extern void guest_code_xsave(void); asm("guest_code_xsave:\n" - "mov $-1, %eax\n" - "mov $-1, %edx\n" + "mov $" __stringify(XFEATURE_MASK_X87_AVX) ", %eax\n" + "xor %edx, %edx\n" "xsave (%rdi)\n" "jmp guest_sev_es_code"); =20 @@ -70,12 +70,6 @@ static void test_sync_vmsa(uint32_t policy) =20 double x87val =3D M_PI; struct kvm_xsave __attribute__((aligned(64))) xsave =3D { 0 }; - struct kvm_sregs sregs; - struct kvm_xcrs xcrs =3D { - .nr_xcrs =3D 1, - .xcrs[0].xcr =3D 0, - .xcrs[0].value =3D XFEATURE_MASK_X87_AVX, - }; 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Thu, 03 Oct 2024 16:44:00 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 3 Oct 2024 16:43:37 -0700 In-Reply-To: <20241003234337.273364-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241003234337.273364-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241003234337.273364-12-seanjc@google.com> Subject: [PATCH 11/11] KVM: selftests: Ensure KVM supports AVX for SEV-ES VMSA FPU test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Vitaly Kuznetsov Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Verify that KVM's supported XCR0 includes AVX (and earlier features) when running the SEV-ES VMSA XSAVE test. In practice, the issue will likely never pop up, since KVM support for AVX predates KVM support for SEV-ES, but checking for KVM support makes the requirement more obvious. Signed-off-by: Sean Christopherson Reviewed-by: Vitaly Kuznetsov --- tools/testing/selftests/kvm/x86_64/sev_smoke_test.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86_64/sev_smoke_test.c b/tools/te= sting/selftests/kvm/x86_64/sev_smoke_test.c index 965fc362dee3..ae77698e6e97 100644 --- a/tools/testing/selftests/kvm/x86_64/sev_smoke_test.c +++ b/tools/testing/selftests/kvm/x86_64/sev_smoke_test.c @@ -181,6 +181,8 @@ static void test_sev_es_shutdown(void) =20 int main(int argc, char *argv[]) { + const u64 xf_mask =3D XFEATURE_MASK_X87_AVX; + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SEV)); =20 test_sev(guest_sev_code, SEV_POLICY_NO_DBG); @@ -193,7 +195,7 @@ int main(int argc, char *argv[]) test_sev_es_shutdown(); =20 if (kvm_has_cap(KVM_CAP_XCRS) && - (xgetbv(0) & XFEATURE_MASK_X87_AVX) =3D=3D XFEATURE_MASK_X87_AVX) { + (xgetbv(0) & kvm_cpu_supported_xcr0() & xf_mask) =3D=3D xf_mask) { test_sync_vmsa(0); test_sync_vmsa(SEV_POLICY_NO_DBG); } --=20 2.47.0.rc0.187.ge670bccf7e-goog