From nobody Thu Nov 28 04:42:20 2024 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 84F3B1BF7E8; Thu, 3 Oct 2024 22:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727995966; cv=none; b=NMAZjYZL57dp/iU4O5lkRkCw9O/NZKfHN9GfAzFFJTp/x77oQtALQrzmydL/eOPOdJS3eYnfdJz7ztnPBGzkaxTHrQusDyNOERkZojfWM9q3zFrd/5lz5NKYcn7MiQtIPlxsvzxmhiQ048VhfMq+6JGV8XlqbTmC31fCiIqZKCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727995966; c=relaxed/simple; bh=5hEk35OyZYLysm+p+WDkPIClzpEGocFfH9F8Qd/SCO4=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=ML7cSuIRWgrIjOpe4CILdkHf8CHLD+wfyIfeVgw4RsWh0hKSWNUe9/A2YMxwu2iADbuGUCeUPsDXLJ8us9t+j09Jl91Dih40zzb1FvbfcsnodOYtX6z6noaT5SgHE0H2PuKn83H92FJfXaaNarldErC3cn+0jyPVCHczEkyaPWU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=bvkeWOlx; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="bvkeWOlx" Received: from rrs24-12-35.corp.microsoft.com (unknown [131.107.174.176]) by linux.microsoft.com (Postfix) with ESMTPSA id E756A20DB360; Thu, 3 Oct 2024 15:52:44 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com E756A20DB360 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1727995965; bh=FSVoCHOR4Nur1zXWJsVTiFk1urE5TyF4R59CiPEAWLU=; h=From:To:Cc:Subject:Date:From; b=bvkeWOlxZxpdvVT+HuCq7T+tEoF6PaAzwch+Si3EXSCqltSLIXDj5WvJshCY5eai2 /fcxdtqPZEBw3Q87pMVcyLZL+AgojKX2UHw71fOAjL7LnTNjMH3On7yX045kC4fgP/ Jku7y/LNrFPY20WVMtaokBOUTC6KbuzjH6vLt2TQ= From: Easwar Hariharan To: Catalin Marinas , Will Deacon , Jonathan Corbet , Mark Rutland , Oliver Upton , Easwar Hariharan , Rob Herring , D Scott Phillips , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list) Cc: James More , stable@vger.kernel.org Subject: [PATCH] arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386 Date: Thu, 3 Oct 2024 22:52:35 +0000 Message-ID: <20241003225239.321774-1-eahariha@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata: Expand speculative SSBS workaround") CC: Mark Rutland CC: James More CC: Will Deacon CC: stable@vger.kernel.org # 6.6+ Signed-off-by: Easwar Hariharan --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/kernel/cpu_errata.c | 1 + 2 files changed, 3 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 9eb5e70b4888..a7d03f1de72d 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -289,3 +289,5 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_22531= 38 | +----------------+-----------------+-----------------+--------------------= ---------+ +| Microsoft | Azure Cobalt 100| #3324339 | ARM64_ERRATUM_31943= 86 | ++----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index dfefbdf4073a..1a6fd56a13c1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -449,6 +449,7 @@ static const struct midr_range erratum_spec_ssbs_list[]= =3D { MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), --=20 2.43.0