From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1C2891AB6EF; Thu, 3 Oct 2024 18:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981619; cv=none; b=SWJ2RpbSO76p78gkkGJ+BuM/VEKByfzZ4NbqUr9VMqyqFcsHvXuUuvksx/8BPPXmSadkVW9G4GFrUKDol2sAD2lSEtWVwG537+CfegJcTOQiaVqZx3VPwzeRYhPHzVHgA1SKMJHCGYKTODB00qBFC5sm5f1b/oHwajuntnR9Byo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981619; c=relaxed/simple; bh=fPKQP1jFze7BRm9mPDY4X0fnIw4wuUgFrVWd5pUD9i4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YOeTpompeFI05LlibhxWxR9rWUEnBZ8isPRLAico0jYdcaiwOJSjjtUg4xnWqY8DJ8JKOuNGDsRSFaDdEYGzkCY7BxS0YalJmrt1REa/89GG2gaLIwiApEClOycP+Q51u8xKflAUATQfRaGyACxt4mP5ZSvo4ZRh+c6LiRxqMO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F1786497; Thu, 3 Oct 2024 11:54:06 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3D91F3F640; Thu, 3 Oct 2024 11:53:35 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 1/7] perf arm-spe: Rename arm_spe__synth_data_source_generic() Date: Thu, 3 Oct 2024 19:53:16 +0100 Message-Id: <20241003185322.192357-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The arm_spe__synth_data_source_generic() function is invoked when the tool detects that CPUs do not support data source packets and falls back to synthesizing only the memory level. Rename it to arm_spe__synth_memory_level() for better reflecting its purpose. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 13fd2c8afebd..34e147e8a963 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -496,8 +496,8 @@ static void arm_spe__synth_data_source_neoverse(const s= truct arm_spe_record *rec } } =20 -static void arm_spe__synth_data_source_generic(const struct arm_spe_record= *record, - union perf_mem_data_src *data_src) +static void arm_spe__synth_memory_level(const struct arm_spe_record *recor= d, + union perf_mem_data_src *data_src) { if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { data_src->mem_lvl =3D PERF_MEM_LVL_L3; @@ -534,7 +534,7 @@ static u64 arm_spe__synth_data_source(const struct arm_= spe_record *record, u64 m if (is_neoverse) arm_spe__synth_data_source_neoverse(record, &data_src); else - arm_spe__synth_data_source_generic(record, &data_src); + arm_spe__synth_memory_level(record, &data_src); =20 if (record->type & (ARM_SPE_TLB_ACCESS | ARM_SPE_TLB_MISS)) { data_src.mem_dtlb =3D PERF_MEM_TLB_WK; --=20 2.34.1 From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1850A1ABEDC; Thu, 3 Oct 2024 18:53:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981621; cv=none; b=b6qne6WJca8v+326QXx+QGp6B/oFy11euRJ2KW+u12nh0Do98GGrHDGBE+3mpEFDlweDfOjfDyuNF89KNRmQI6N00l+TbNwJIr2FNK7NcZXcFCJuBRX23dv9H202Z5SBoQEE4eMysnFiBHY+g6ZsLInIfYZ4d/9mFtjfzTag1D0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981621; c=relaxed/simple; bh=C7B5n1nOPQE81aD+pGzA8ZYM6Ae8XlpriN2qRcMtntg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Rd53RfmRxkcIH0hQRQxVcZ+R/TxdphW0mewjvx6dOxTNOqt6Z4mge5VckuqYZmgbW3IwBY6GIgVRu714Xr8Hx7fMc2MRlASVEhnfk9MdjpRV9ZhT9BUV5xKdhPxyO/3b+jNehrgClbHrratZ+TcOlJOFmUFKDRvEMS8oR4o433w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C551339; Thu, 3 Oct 2024 11:54:09 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7AA3E3F836; Thu, 3 Oct 2024 11:53:37 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 2/7] perf arm-spe: Rename the common data source encoding Date: Thu, 3 Oct 2024 19:53:17 +0100 Message-Id: <20241003185322.192357-3-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Neoverse CPUs follow the common data source encoding, and other CPU variants can share the same format. Rename the CPU list and data source definitions as common data source names. This change prepares for appending more CPU variants. Signed-off-by: Leo Yan Reviewed-by: James Clark --- .../util/arm-spe-decoder/arm-spe-decoder.h | 18 ++++++------ tools/perf/util/arm-spe.c | 28 +++++++++---------- 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf= /util/arm-spe-decoder/arm-spe-decoder.h index 1443c28545a9..358c611eeddb 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -56,15 +56,15 @@ enum arm_spe_op_type { ARM_SPE_OP_BR_INDIRECT =3D 1 << 17, }; =20 -enum arm_spe_neoverse_data_source { - ARM_SPE_NV_L1D =3D 0x0, - ARM_SPE_NV_L2 =3D 0x8, - ARM_SPE_NV_PEER_CORE =3D 0x9, - ARM_SPE_NV_LOCAL_CLUSTER =3D 0xa, - ARM_SPE_NV_SYS_CACHE =3D 0xb, - ARM_SPE_NV_PEER_CLUSTER =3D 0xc, - ARM_SPE_NV_REMOTE =3D 0xd, - ARM_SPE_NV_DRAM =3D 0xe, +enum arm_spe_common_data_source { + ARM_SPE_COMMON_DS_L1D =3D 0x0, + ARM_SPE_COMMON_DS_L2 =3D 0x8, + ARM_SPE_COMMON_DS_PEER_CORE =3D 0x9, + ARM_SPE_COMMON_DS_LOCAL_CLUSTER =3D 0xa, + ARM_SPE_COMMON_DS_SYS_CACHE =3D 0xb, + ARM_SPE_COMMON_DS_PEER_CLUSTER =3D 0xc, + ARM_SPE_COMMON_DS_REMOTE =3D 0xd, + ARM_SPE_COMMON_DS_DRAM =3D 0xe, }; =20 struct arm_spe_record { diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 34e147e8a963..b0e9eb6057c3 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -413,15 +413,15 @@ static int arm_spe__synth_instruction_sample(struct a= rm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } =20 -static const struct midr_range neoverse_spe[] =3D { +static const struct midr_range common_ds_encoding_cpus[] =3D { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), {}, }; =20 -static void arm_spe__synth_data_source_neoverse(const struct arm_spe_recor= d *record, - union perf_mem_data_src *data_src) +static void arm_spe__synth_data_source_common(const struct arm_spe_record = *record, + union perf_mem_data_src *data_src) { /* * Even though four levels of cache hierarchy are possible, no known @@ -443,17 +443,17 @@ static void arm_spe__synth_data_source_neoverse(const= struct arm_spe_record *rec } =20 switch (record->source) { - case ARM_SPE_NV_L1D: + case ARM_SPE_COMMON_DS_L1D: data_src->mem_lvl =3D PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L1; data_src->mem_snoop =3D PERF_MEM_SNOOP_NONE; break; - case ARM_SPE_NV_L2: + case ARM_SPE_COMMON_DS_L2: data_src->mem_lvl =3D PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L2; data_src->mem_snoop =3D PERF_MEM_SNOOP_NONE; break; - case ARM_SPE_NV_PEER_CORE: + case ARM_SPE_COMMON_DS_PEER_CORE: data_src->mem_lvl =3D PERF_MEM_LVL_L2 | PERF_MEM_LVL_HIT; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L2; data_src->mem_snoopx =3D PERF_MEM_SNOOPX_PEER; @@ -462,8 +462,8 @@ static void arm_spe__synth_data_source_neoverse(const s= truct arm_spe_record *rec * We don't know if this is L1, L2 but we do know it was a cache-2-cache * transfer, so set SNOOPX_PEER */ - case ARM_SPE_NV_LOCAL_CLUSTER: - case ARM_SPE_NV_PEER_CLUSTER: + case ARM_SPE_COMMON_DS_LOCAL_CLUSTER: + case ARM_SPE_COMMON_DS_PEER_CLUSTER: data_src->mem_lvl =3D PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L3; data_src->mem_snoopx =3D PERF_MEM_SNOOPX_PEER; @@ -471,7 +471,7 @@ static void arm_spe__synth_data_source_neoverse(const s= truct arm_spe_record *rec /* * System cache is assumed to be L3 */ - case ARM_SPE_NV_SYS_CACHE: + case ARM_SPE_COMMON_DS_SYS_CACHE: data_src->mem_lvl =3D PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_L3; data_src->mem_snoop =3D PERF_MEM_SNOOP_HIT; @@ -480,13 +480,13 @@ static void arm_spe__synth_data_source_neoverse(const= struct arm_spe_record *rec * We don't know what level it hit in, except it came from the other * socket */ - case ARM_SPE_NV_REMOTE: + case ARM_SPE_COMMON_DS_REMOTE: data_src->mem_lvl =3D PERF_MEM_LVL_REM_CCE1; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_ANY_CACHE; data_src->mem_remote =3D PERF_MEM_REMOTE_REMOTE; data_src->mem_snoopx =3D PERF_MEM_SNOOPX_PEER; break; - case ARM_SPE_NV_DRAM: + case ARM_SPE_COMMON_DS_DRAM: data_src->mem_lvl =3D PERF_MEM_LVL_LOC_RAM | PERF_MEM_LVL_HIT; data_src->mem_lvl_num =3D PERF_MEM_LVLNUM_RAM; data_src->mem_snoop =3D PERF_MEM_SNOOP_NONE; @@ -522,7 +522,7 @@ static void arm_spe__synth_memory_level(const struct ar= m_spe_record *record, static u64 arm_spe__synth_data_source(const struct arm_spe_record *record,= u64 midr) { union perf_mem_data_src data_src =3D { .mem_op =3D PERF_MEM_OP_NA }; - bool is_neoverse =3D is_midr_in_range_list(midr, neoverse_spe); + bool is_common =3D is_midr_in_range_list(midr, common_ds_encoding_cpus); =20 if (record->op & ARM_SPE_OP_LD) data_src.mem_op =3D PERF_MEM_OP_LOAD; @@ -531,8 +531,8 @@ static u64 arm_spe__synth_data_source(const struct arm_= spe_record *record, u64 m else return 0; =20 - if (is_neoverse) - arm_spe__synth_data_source_neoverse(record, &data_src); + if (is_common) + arm_spe__synth_data_source_common(record, &data_src); else arm_spe__synth_memory_level(record, &data_src); =20 --=20 2.34.1 From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 37B751AC458; Thu, 3 Oct 2024 18:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 48AFD14BF; Thu, 3 Oct 2024 11:54:11 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B75103F640; Thu, 3 Oct 2024 11:53:39 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 3/7] perf arm-spe: Introduce arm_spe__is_homogeneous() Date: Thu, 3 Oct 2024 19:53:18 +0100 Message-Id: <20241003185322.192357-4-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the arm_spe__is_homogeneous() function, it uses to check if Arm SPE is homogeneous cross all CPUs. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index b0e9eb6057c3..587943b6bdb8 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -82,6 +82,7 @@ struct arm_spe { u64 **metadata; u64 metadata_ver; u64 metadata_nr_cpu; + bool is_homogeneous; }; =20 struct arm_spe_queue { @@ -1374,6 +1375,30 @@ arm_spe_synth_events(struct arm_spe *spe, struct per= f_session *session) return 0; } =20 +static bool arm_spe__is_homogeneous(u64 **metadata, int nr_cpu) +{ + u64 midr; + int i; + + if (!nr_cpu) + return false; + + for (i =3D 0; i < nr_cpu; i++) { + if (!metadata[i]) + return false; + + if (i =3D=3D 0) { + midr =3D metadata[i][ARM_SPE_CPU_MIDR]; + continue; + } + + if (midr !=3D metadata[i][ARM_SPE_CPU_MIDR]) + return false; + } + + return true; +} + int arm_spe_process_auxtrace_info(union perf_event *event, struct perf_session *session) { @@ -1419,6 +1444,7 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, spe->metadata =3D metadata; spe->metadata_ver =3D metadata_ver; spe->metadata_nr_cpu =3D nr_cpu; + spe->is_homogeneous =3D arm_spe__is_homogeneous(metadata, nr_cpu); =20 spe->timeless_decoding =3D arm_spe__is_timeless_decoding(spe); =20 --=20 2.34.1 From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5DE651AD9F8; Thu, 3 Oct 2024 18:53:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981625; cv=none; b=Fp1WquBldQYxsXYZbXQ/QdN6hW+6XmB9ptNdGgMh//kSbBwSVHfLfN5S4sOAoMOE1qcIoYfgS2SwHjbIvV89RYd9zesPZ7k6Qnpi/0S7CbISECnhw57wcHZ8EHWTREpryBKfx+JPGlnKs33owqHG+8UDoZo+LzoTInuhucz/gdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981625; c=relaxed/simple; bh=ogF78HKBDHqnrPfvhawMtYytPGdQOMbfO6Mm2m/Ln3M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g/2xHzao9BEiojYwXcLVKD38NaZRUyKtPlv8vHyUq9NvwrYmj5pqfG5OK3Q0TzouAiDmr5+iR6Og6aP4oQZgaHh78v85vXyQj8UtVyGYwFhLTtQZcADEwy/UDH1Mmu3Op2DXMKpfxY6TeelyEXq/4QvJ7pNDKwXo0kgBSIUPgrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85AE3339; Thu, 3 Oct 2024 11:54:13 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F3F5F3F640; Thu, 3 Oct 2024 11:53:41 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 4/7] perf arm-spe: Use metadata to decide the data source feature Date: Thu, 3 Oct 2024 19:53:19 +0100 Message-Id: <20241003185322.192357-5-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the info in the metadata to decide if the data source feature is supported. The CPU MIDR must be in the CPU list for the common data source encoding. For the metadata version 1, it doesn't include info for MIDR. In this case, due to absent info for making decision, print out warning to remind users to upgrade tool and returns false. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 67 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 587943b6bdb8..9221b2f66bbe 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -278,6 +278,20 @@ static int arm_spe_set_tid(struct arm_spe_queue *speq,= pid_t tid) return 0; } =20 +static u64 *arm_spe__get_metadata_by_cpu(struct arm_spe *spe, u64 cpu) +{ + u64 i; + + if (!spe->metadata) + return NULL; + + for (i =3D 0; i < spe->metadata_nr_cpu; i++) + if (spe->metadata[i][ARM_SPE_CPU] =3D=3D cpu) + return spe->metadata[i]; + + return NULL; +} + static struct simd_flags arm_spe__synth_simd_flags(const struct arm_spe_re= cord *record) { struct simd_flags simd_flags =3D {}; @@ -520,10 +534,57 @@ static void arm_spe__synth_memory_level(const struct = arm_spe_record *record, data_src->mem_lvl |=3D PERF_MEM_LVL_REM_CCE1; } =20 -static u64 arm_spe__synth_data_source(const struct arm_spe_record *record,= u64 midr) +static bool arm_spe__is_common_ds_encoding(struct arm_spe_queue *speq) +{ + struct arm_spe *spe =3D speq->spe; + bool is_in_cpu_list; + u64 *metadata =3D NULL; + u64 midr =3D 0; + + /* + * Metadata version 1 doesn't contain any info for MIDR. + * Simply return false in this case. + */ + if (spe->metadata_ver =3D=3D 1) { + pr_warning_once("The data file contains metadata version 1, " + "which is absent the info for data source. " + "Please upgrade the tool to record data.\n"); + return false; + } + + /* CPU ID is -1 for per-thread mode */ + if (speq->cpu < 0) { + /* + * On the heterogeneous system, due to CPU ID is -1, + * cannot confirm the data source packet is supported. + */ + if (!spe->is_homogeneous) + return false; + + /* In homogeneous system, simply use CPU0's metadata */ + if (spe->metadata) + metadata =3D spe->metadata[0]; + } else { + metadata =3D arm_spe__get_metadata_by_cpu(spe, speq->cpu); + } + + if (!metadata) + return false; + + midr =3D metadata[ARM_SPE_CPU_MIDR]; + + is_in_cpu_list =3D is_midr_in_range_list(midr, common_ds_encoding_cpus); + if (is_in_cpu_list) + return true; + else + return false; +} + +static u64 arm_spe__synth_data_source(struct arm_spe_queue *speq, + const struct arm_spe_record *record) { union perf_mem_data_src data_src =3D { .mem_op =3D PERF_MEM_OP_NA }; - bool is_common =3D is_midr_in_range_list(midr, common_ds_encoding_cpus); + bool is_common =3D arm_spe__is_common_ds_encoding(speq); =20 if (record->op & ARM_SPE_OP_LD) data_src.mem_op =3D PERF_MEM_OP_LOAD; @@ -556,7 +617,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) u64 data_src; int err; =20 - data_src =3D arm_spe__synth_data_source(record, spe->midr); + data_src =3D arm_spe__synth_data_source(speq, record); =20 if (spe->sample_flc) { if (record->type & ARM_SPE_L1D_MISS) { --=20 2.34.1 From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C268E1B85D0; Thu, 3 Oct 2024 18:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981628; cv=none; b=UF1lD4wbsv0Fn5UqKAnLf8xOE/ccN0O/H6P956M2Ti/ixUFwN9dwadg71y1tduAf3Ox+5beiFhDkbqAwRthUvF4teX7XxNrt3ZJNaeuwqSAFnj6N8LiVIAg5rRGI22Xjruzz5doNQ/wm8pGYyt9GJeF3ivUqpmeK3uQaflW54pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981628; c=relaxed/simple; bh=uKnz5kd7YKacNv+wpKZkgJqTFb4cESY+HRNpg921fPw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WYsUQeYiWYaztS5at9El4aW6sbPm56622Lu4VR5EVAXZYopk/LOlUq3I0nNGSlt4wEPL9gy97HbSwKNd1tqj5FZHHYzf9+acOIyPAlrwznV0khUIokM95Hz9dIRk2l12mvaxKd3BbzjcMVhbELpkSghMXewtPTFK9FrJrjxiPrA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C581B339; Thu, 3 Oct 2024 11:54:15 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3DC273F640; Thu, 3 Oct 2024 11:53:44 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 5/7] perf arm-spe: Remove the unused 'midr' field Date: Thu, 3 Oct 2024 19:53:20 +0100 Message-Id: <20241003185322.192357-6-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 'midr' field is replaced by the MIDR values stored in metadata (per CPU wise). Remove the 'midr' field as it is no longer used. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 9221b2f66bbe..485f60c32309 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -46,7 +46,6 @@ struct arm_spe { struct perf_session *session; struct machine *machine; u32 pmu_type; - u64 midr; =20 struct perf_tsc_conversion tc; =20 @@ -1466,8 +1465,6 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, struct perf_record_auxtrace_info *auxtrace_info =3D &event->auxtrace_info; size_t min_sz =3D ARM_SPE_AUXTRACE_V1_PRIV_SIZE; struct perf_record_time_conv *tc =3D &session->time_conv; - const char *cpuid =3D perf_env__cpuid(session->evlist->env); - u64 midr =3D strtol(cpuid, NULL, 16); struct arm_spe *spe; u64 **metadata =3D NULL; u64 metadata_ver; @@ -1501,7 +1498,6 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, spe->pmu_type =3D auxtrace_info->priv[ARM_SPE_PMU_TYPE]; else spe->pmu_type =3D auxtrace_info->priv[ARM_SPE_PMU_TYPE_V2]; - spe->midr =3D midr; spe->metadata =3D metadata; spe->metadata_ver =3D metadata_ver; spe->metadata_nr_cpu =3D nr_cpu; --=20 2.34.1 From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1A07C1AB6DE; Thu, 3 Oct 2024 18:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981630; cv=none; b=JAjUv8WclFzbma6n1GIW5hzvArUffWx89cDe3P4ZqkF2zLV1PhG2Q24q+u71m0q6k3Nywouz9rUWaOAP4C6cWBAVa70NUNeU5YufqUQxMzXu9dTR+JMerE4ckdUujs4MpAFU23hblI08ghBaUxhXamKioZtOipoWbYkr5JV5Sbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981630; c=relaxed/simple; bh=7kEFo8Kklmc9Fw0lsHNelbnmeo3pWe6BVgToP4WKWDg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Jl3gY3lsUVy3rTdEUCPU3c6GDpx3F0gStS9Y/ZpNP/i1mlYpfYjQj5GUY+UrlsMWRJxcCEpiFLgK6nGQfmj1/leR5irj3tMxmeDTyCDVndgDovP6DxVaa5FDkEm6Vl3SOkXyB+Zyppo9NXDKtxe3AGzOnz919HJ8kmtnzyk95bQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16E4D497; Thu, 3 Oct 2024 11:54:18 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7B63B3F640; Thu, 3 Oct 2024 11:53:46 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 6/7] perf arm-spe: Add Neoverse-V2 to common data source encoding list Date: Thu, 3 Oct 2024 19:53:21 +0100 Message-Id: <20241003185322.192357-7-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Besar Wicaksono Add Neoverse-V2 MIDR to the common data source encoding range list. Signed-off-by: Besar Wicaksono Reviewed-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 485f60c32309..5c34a9ae3862 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -431,6 +431,7 @@ static const struct midr_range common_ds_encoding_cpus[= ] =3D { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), {}, }; =20 --=20 2.34.1 From nobody Thu Nov 28 05:54:36 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C6C31C0DD6; Thu, 3 Oct 2024 18:53:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981632; cv=none; b=mFzBuLhRKlssItspTzyzAU+GsI0VNg6hXQQ03baBq0MwtLKWYRu5HTHkwbpOcTdqzpdwEiZURmBdxvJpwQ/qZpIq+rNDNXLRU3zJyM+CrYMx+Ize3olYYK7AsdHTkPwR0ygp6shasf+AQ419euE0N5AL8LtrjaCjmgTIsdpuuV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981632; c=relaxed/simple; bh=hKO/B15J995VtpURcUXXxTlAjV8SBjlKHuMwCb1tRsw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TWC2u7xYoCADMlzV969zThKoJoiq0E0w3g9weIMfc2u8Zjnv7QELzh6NvJaxWNn9r9pJ4s5FEKVHFPGgvy7iiGajW8bC9n+WdBFU/7oe40Np5dc2SZpGSzaicD2eI9N6dla5Z9MaKbeC1ilZX9ZT2EhdGW5KhAeNohgWEv7XdPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5DE7B339; Thu, 3 Oct 2024 11:54:20 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C23143F640; Thu, 3 Oct 2024 11:53:48 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Besar Wicaksono , James Clark , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , John Garry , Will Deacon , Mike Leach , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v3 7/7] perf arm-spe: Add Cortex CPUs to common data source encoding list Date: Thu, 3 Oct 2024 19:53:22 +0100 Message-Id: <20241003185322.192357-8-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003185322.192357-1-leo.yan@arm.com> References: <20241003185322.192357-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Cortex-A720, Cortex-A725, Cortex-X1C, Cortex-X3 and Cortex-X925 into the common data source encoding list. For everyone of these CPUs, it technical reference manual defines the data source packet as the common encoding format. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 5c34a9ae3862..c424e5b9a11d 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -428,6 +428,11 @@ static int arm_spe__synth_instruction_sample(struct ar= m_spe_queue *speq, } =20 static const struct midr_range common_ds_encoding_cpus[] =3D { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), --=20 2.34.1