From nobody Thu Nov 28 05:38:56 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1854419F134; Thu, 3 Oct 2024 18:43:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981001; cv=none; b=oUqHXVlnYcYZsHuMa0n5O+IbY/JcDHhb08Ih5i76fDEyrn+pL4XWQmp2/RYVZyzcELdEP5HdCxtXiaya0PfreJfCAoFf19bkdSSC3xQVda4AxwKQD463NA6OuLgQK6evCjreOfE5Jw2aTwUse1HUUrU1VTUv/v0NM8cVdwl1Fls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981001; c=relaxed/simple; bh=V2OGvRa2Ftp5vEJMZlDF63cwahPII5E7H3BqHG/1sTo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CEITY0DjE3L7EvTXeVEG+BrI5t93mYAt9sH6E3X1anzD2+yAKVejoMrBBHAknR2bjdigD6uThWlos2WbjNkV4Sl6b+g8bW+9ynDX30vNMkjnnef2gY0onUe2/nvOAqBaPwutI7neMnDp/1dvs5JqSMuJLo5u7NnjxgUgeszGZ88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C58E8497; Thu, 3 Oct 2024 11:43:47 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2A4E33F58B; Thu, 3 Oct 2024 11:43:16 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Besar Wicaksono , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , John Garry , James Clark , Mike Leach Cc: Leo Yan Subject: [PATCH v4 1/5] perf arm-spe: Define metadata header version 2 Date: Thu, 3 Oct 2024 19:42:58 +0100 Message-Id: <20241003184302.190806-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003184302.190806-1-leo.yan@arm.com> References: <20241003184302.190806-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The first version's metadata header structure doesn't include a field to indicate a header version, which is not friendly for extension. Define the metadata version 2 format with a new header structure and extend per CPU's metadata. In the meantime, the old metadata header will still be supported for backward compatibility. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 4 +-- tools/perf/util/arm-spe.c | 2 +- tools/perf/util/arm-spe.h | 38 +++++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/u= til/arm-spe.c index 2be99fdf997d..c2d5c8ca4900 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -41,7 +41,7 @@ static size_t arm_spe_info_priv_size(struct auxtrace_record *itr __maybe_unused, struct evlist *evlist __maybe_unused) { - return ARM_SPE_AUXTRACE_PRIV_SIZE; + return ARM_SPE_AUXTRACE_V1_PRIV_SIZE; } =20 static int arm_spe_info_fill(struct auxtrace_record *itr, @@ -53,7 +53,7 @@ static int arm_spe_info_fill(struct auxtrace_record *itr, container_of(itr, struct arm_spe_recording, itr); struct perf_pmu *arm_spe_pmu =3D sper->arm_spe_pmu; =20 - if (priv_size !=3D ARM_SPE_AUXTRACE_PRIV_SIZE) + if (priv_size !=3D ARM_SPE_AUXTRACE_V1_PRIV_SIZE) return -EINVAL; =20 if (!session->evlist->core.nr_mmaps) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 138ffc71b32d..70989b1bae47 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -1262,7 +1262,7 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, struct perf_session *session) { struct perf_record_auxtrace_info *auxtrace_info =3D &event->auxtrace_info; - size_t min_sz =3D sizeof(u64) * ARM_SPE_AUXTRACE_PRIV_MAX; + size_t min_sz =3D ARM_SPE_AUXTRACE_V1_PRIV_SIZE; struct perf_record_time_conv *tc =3D &session->time_conv; const char *cpuid =3D perf_env__cpuid(session->evlist->env); u64 midr =3D strtol(cpuid, NULL, 16); diff --git a/tools/perf/util/arm-spe.h b/tools/perf/util/arm-spe.h index 4f4900c18f3e..390679a4af2f 100644 --- a/tools/perf/util/arm-spe.h +++ b/tools/perf/util/arm-spe.h @@ -12,10 +12,46 @@ enum { ARM_SPE_PMU_TYPE, ARM_SPE_PER_CPU_MMAPS, + ARM_SPE_AUXTRACE_V1_PRIV_MAX, +}; + +#define ARM_SPE_AUXTRACE_V1_PRIV_SIZE \ + (ARM_SPE_AUXTRACE_V1_PRIV_MAX * sizeof(u64)) + +enum { + /* + * The old metadata format (defined above) does not include a + * field for version number. Version 1 is reserved and starts + * from version 2. + */ + ARM_SPE_HEADER_VERSION, + /* Number of sizeof(u64) */ + ARM_SPE_HEADER_SIZE, + /* PMU type shared by CPUs */ + ARM_SPE_PMU_TYPE_V2, + /* Number of CPUs */ + ARM_SPE_CPUS_NUM, ARM_SPE_AUXTRACE_PRIV_MAX, }; =20 -#define ARM_SPE_AUXTRACE_PRIV_SIZE (ARM_SPE_AUXTRACE_PRIV_MAX * sizeof(u64= )) +enum { + /* Magic number */ + ARM_SPE_MAGIC, + /* CPU logical number in system */ + ARM_SPE_CPU, + /* Number of parameters */ + ARM_SPE_CPU_NR_PARAMS, + /* CPU MIDR */ + ARM_SPE_CPU_MIDR, + /* Associated PMU type */ + ARM_SPE_CPU_PMU_TYPE, + /* Minimal interval */ + ARM_SPE_CAP_MIN_IVAL, + ARM_SPE_CPU_PRIV_MAX, +}; + +#define ARM_SPE_HEADER_CURRENT_VERSION 2 + =20 union perf_event; struct perf_session; --=20 2.34.1 From nobody Thu Nov 28 05:38:56 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 419181ABEBA; Thu, 3 Oct 2024 18:43:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981002; cv=none; b=Y1UdRFme6xR28Ka0FiUyfFySGdKOJ/wKsKeWHNSnLqXcg2akYk2p8FYSwli63hGBPJI5c2faNT7r2Ff65tJcbkpnlrcRXjPPJa/NelwF8olxUqMOfMteiv6OwMgMyu4RCld6UU2SAsN67Z8rCQj61wWFSanwkJ2PrX8PBydrdwM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981002; c=relaxed/simple; bh=1nOjb5P8Kz4jN1Nt9f0iqKsglQ9eFkzmO3XqsM7gx1o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tTWjaVmGZvht8l1RSD9mbs8MVlW6LUfYeo/kS7Dbh/ubR2mExEgLZEeMOAwT0pI6+dz0Lmr3H2w7dXpFJmBK19JC8nut5966NN9hbYnmdVYZTixORDh3pWnJRwOBaeoUosfCbOJx7dbxvcCBawT7kWBroGj/NSceMBaJfNtoclY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE1E314BF; Thu, 3 Oct 2024 11:43:49 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 681E53F58B; Thu, 3 Oct 2024 11:43:18 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Besar Wicaksono , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , John Garry , James Clark , Mike Leach Cc: Leo Yan Subject: [PATCH v4 2/5] perf arm-spe: Calculate meta data size Date: Thu, 3 Oct 2024 19:42:59 +0100 Message-Id: <20241003184302.190806-3-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003184302.190806-1-leo.yan@arm.com> References: <20241003184302.190806-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The metadata is designed to contain a header and per CPU information. The arm_spe_find_cpus() function is introduced to identify how many CPUs support ARM SPE. Based on the CPU number, calculates the metadata size. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 39 +++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/u= til/arm-spe.c index c2d5c8ca4900..81d5c07380a4 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -37,11 +37,44 @@ struct arm_spe_recording { bool *wrapped; }; =20 +/* + * arm_spe_find_cpus() returns a new cpu map, and the caller should invoke + * perf_cpu_map__put() to release the map after use. + */ +static struct perf_cpu_map *arm_spe_find_cpus(struct evlist *evlist) +{ + struct perf_cpu_map *event_cpus =3D evlist->core.user_requested_cpus; + struct perf_cpu_map *online_cpus =3D perf_cpu_map__new_online_cpus(); + struct perf_cpu_map *intersect_cpus; + + /* cpu map is not "any" CPU , we have specific CPUs to work with */ + if (!perf_cpu_map__has_any_cpu(event_cpus)) { + intersect_cpus =3D perf_cpu_map__intersect(event_cpus, online_cpus); + perf_cpu_map__put(online_cpus); + /* Event can be "any" CPU so count all CPUs. */ + } else { + intersect_cpus =3D online_cpus; + } + + return intersect_cpus; +} + static size_t arm_spe_info_priv_size(struct auxtrace_record *itr __maybe_unused, - struct evlist *evlist __maybe_unused) + struct evlist *evlist) { - return ARM_SPE_AUXTRACE_V1_PRIV_SIZE; + struct perf_cpu_map *cpu_map =3D arm_spe_find_cpus(evlist); + size_t size; + + if (!cpu_map) + return 0; + + size =3D ARM_SPE_AUXTRACE_PRIV_MAX + + ARM_SPE_CPU_PRIV_MAX * perf_cpu_map__nr(cpu_map); + size *=3D sizeof(u64); + + perf_cpu_map__put(cpu_map); + return size; } =20 static int arm_spe_info_fill(struct auxtrace_record *itr, @@ -53,7 +86,7 @@ static int arm_spe_info_fill(struct auxtrace_record *itr, container_of(itr, struct arm_spe_recording, itr); struct perf_pmu *arm_spe_pmu =3D sper->arm_spe_pmu; =20 - if (priv_size !=3D ARM_SPE_AUXTRACE_V1_PRIV_SIZE) + if (priv_size !=3D arm_spe_info_priv_size(itr, session->evlist)) return -EINVAL; =20 if (!session->evlist->core.nr_mmaps) --=20 2.34.1 From nobody Thu Nov 28 05:38:56 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 452E41AC891; Thu, 3 Oct 2024 18:43:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981004; cv=none; b=GSeGZvIKIP2eATITQNZk554f9U4QnCvQy+voKTsn2fSMRz7jw80syqtCoV80lyYJQungebquLmrl1dt9FxI5LijRYECfXw3o5J6Y27z4weoFNJrxvjoxID066ithQa/5mPRHSCOfN10oM6HXgwv1u7aG7y/9xqeo4ZFVrqEsd8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981004; c=relaxed/simple; bh=lyphz1EPh8Qt2lMXrF1Pu2CTR2pWFAvY8Rn8Vq96Jw4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rtNCwHQ6J99sKigVKkNTKKZ7nC2S0ZNX5X2CdMShj0SBBrRFWRYA+CRyExGxtBiejsBRp66jRk46zkuI3xdBOcO94prFdFJAwiQScaZmUx4QjT/jhwg71a00jX5A2hGKcXKK4zY677ViLL3p1IRzxJ4L2+TLRY0iMitPI/ayM0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 394D4339; Thu, 3 Oct 2024 11:43:52 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A583B3F58B; Thu, 3 Oct 2024 11:43:20 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Besar Wicaksono , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , John Garry , James Clark , Mike Leach Cc: Leo Yan Subject: [PATCH v4 3/5] perf arm-spe: Save per CPU information in metadata Date: Thu, 3 Oct 2024 19:43:00 +0100 Message-Id: <20241003184302.190806-4-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003184302.190806-1-leo.yan@arm.com> References: <20241003184302.190806-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Save the Arm SPE information on a per-CPU basis. This approach is easier in the decoding phase for retrieving metadata based on the CPU number of every Arm SPE record. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/arch/arm64/util/arm-spe.c | 83 +++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/u= til/arm-spe.c index 81d5c07380a4..28b35463d274 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -26,6 +26,8 @@ #include "../../../util/arm-spe.h" #include // reallocarray =20 +#define ARM_SPE_CPU_MAGIC 0x1010101010101010ULL + #define KiB(x) ((x) * 1024) #define MiB(x) ((x) * 1024 * 1024) =20 @@ -77,14 +79,70 @@ arm_spe_info_priv_size(struct auxtrace_record *itr __ma= ybe_unused, return size; } =20 +static int arm_spe_save_cpu_header(struct auxtrace_record *itr, + struct perf_cpu cpu, __u64 data[]) +{ + struct arm_spe_recording *sper =3D + container_of(itr, struct arm_spe_recording, itr); + struct perf_pmu *pmu =3D NULL; + struct perf_pmu tmp_pmu; + char cpu_id_str[16]; + char *cpuid =3D NULL; + u64 val; + + snprintf(cpu_id_str, sizeof(cpu_id_str), "%d", cpu.cpu); + tmp_pmu.cpus =3D perf_cpu_map__new(cpu_id_str); + if (!tmp_pmu.cpus) + return -ENOMEM; + + /* Read CPU MIDR */ + cpuid =3D perf_pmu__getcpuid(&tmp_pmu); + + /* The CPU map will not be used anymore, release it */ + perf_cpu_map__put(tmp_pmu.cpus); + + if (!cpuid) + return -ENOMEM; + val =3D strtol(cpuid, NULL, 16); + + data[ARM_SPE_MAGIC] =3D ARM_SPE_CPU_MAGIC; + data[ARM_SPE_CPU] =3D cpu.cpu; + data[ARM_SPE_CPU_NR_PARAMS] =3D ARM_SPE_CPU_PRIV_MAX - ARM_SPE_CPU_MIDR; + data[ARM_SPE_CPU_MIDR] =3D val; + + /* Find the associate Arm SPE PMU for the CPU */ + if (perf_cpu_map__has(sper->arm_spe_pmu->cpus, cpu)) + pmu =3D sper->arm_spe_pmu; + + if (!pmu) { + /* No Arm SPE PMU is found */ + data[ARM_SPE_CPU_PMU_TYPE] =3D ULLONG_MAX; + data[ARM_SPE_CAP_MIN_IVAL] =3D 0; + } else { + data[ARM_SPE_CPU_PMU_TYPE] =3D pmu->type; + + if (perf_pmu__scan_file(pmu, "caps/min_interval", "%lu", &val) !=3D 1) + val =3D 0; + data[ARM_SPE_CAP_MIN_IVAL] =3D val; + } + + free(cpuid); + return ARM_SPE_CPU_PRIV_MAX; +} + static int arm_spe_info_fill(struct auxtrace_record *itr, struct perf_session *session, struct perf_record_auxtrace_info *auxtrace_info, size_t priv_size) { + int i, ret; + size_t offset; struct arm_spe_recording *sper =3D container_of(itr, struct arm_spe_recording, itr); struct perf_pmu *arm_spe_pmu =3D sper->arm_spe_pmu; + struct perf_cpu_map *cpu_map; + struct perf_cpu cpu; + __u64 *data; =20 if (priv_size !=3D arm_spe_info_priv_size(itr, session->evlist)) return -EINVAL; @@ -92,10 +150,31 @@ static int arm_spe_info_fill(struct auxtrace_record *i= tr, if (!session->evlist->core.nr_mmaps) return -EINVAL; =20 + cpu_map =3D arm_spe_find_cpus(session->evlist); + if (!cpu_map) + return -EINVAL; + auxtrace_info->type =3D PERF_AUXTRACE_ARM_SPE; - auxtrace_info->priv[ARM_SPE_PMU_TYPE] =3D arm_spe_pmu->type; + auxtrace_info->priv[ARM_SPE_HEADER_VERSION] =3D ARM_SPE_HEADER_CURRENT_VE= RSION; + auxtrace_info->priv[ARM_SPE_HEADER_SIZE] =3D + ARM_SPE_AUXTRACE_PRIV_MAX - ARM_SPE_HEADER_VERSION; + auxtrace_info->priv[ARM_SPE_PMU_TYPE_V2] =3D arm_spe_pmu->type; + auxtrace_info->priv[ARM_SPE_CPUS_NUM] =3D perf_cpu_map__nr(cpu_map); + + offset =3D ARM_SPE_AUXTRACE_PRIV_MAX; + perf_cpu_map__for_each_cpu(cpu, i, cpu_map) { + assert(offset < priv_size); + data =3D &auxtrace_info->priv[offset]; + ret =3D arm_spe_save_cpu_header(itr, cpu, data); + if (ret < 0) + goto out; + offset +=3D ret; + } =20 - return 0; + ret =3D 0; +out: + perf_cpu_map__put(cpu_map); + return ret; } =20 static void --=20 2.34.1 From nobody Thu Nov 28 05:38:56 2024 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 220D81AD9C3; Thu, 3 Oct 2024 18:43:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727981006; cv=none; b=tnex0vn27XVN3O+ouNTKnXyrslY6Ej1HsJXU91Y9yWDaPRUqrW8Sj068tJO6Lfkq6lyOmRmkMjKeA4NMNQeJr/HCobLRD5CjFFUymeDFVRWBY5FW793Ik2erwZA9u5g8PF8DRzDcFfVSFpNdy6h1U6i50qgoBgUVxOD0U+0mefQ= ARC-Message-Signature: i=1; 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Thu, 3 Oct 2024 11:43:22 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Besar Wicaksono , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , John Garry , James Clark , Mike Leach Cc: Leo Yan Subject: [PATCH v4 4/5] perf arm-spe: Support metadata version 2 Date: Thu, 3 Oct 2024 19:43:01 +0100 Message-Id: <20241003184302.190806-5-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003184302.190806-1-leo.yan@arm.com> References: <20241003184302.190806-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit is to support metadata version 2 and at the meantime it is backward compatible for version 1's format. The metadata version 1 doesn't include the ARM_SPE_HEADER_VERSION field. As version 1 is fixed with two u64 fields, by checking the metadata size, it distinguishes the metadata is version 1 or version 2 (and any new versions if later will have). For version 2, it reads out CPU number and retrieves the metadata info for every CPU. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 99 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 70989b1bae47..8b2af1c7dc9b 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -78,6 +78,10 @@ struct arm_spe { =20 unsigned long num_events; u8 use_ctx_pkt_for_pid; + + u64 **metadata; + u64 metadata_ver; + u64 metadata_nr_cpu; }; =20 struct arm_spe_queue { @@ -1016,6 +1020,73 @@ static int arm_spe_flush(struct perf_session *sessio= n __maybe_unused, return 0; } =20 +static u64 *arm_spe__alloc_per_cpu_metadata(u64 *buf, int per_cpu_size) +{ + u64 *metadata; + + metadata =3D zalloc(per_cpu_size); + if (!metadata) + return NULL; + + memcpy(metadata, buf, per_cpu_size); + return metadata; +} + +static void arm_spe__free_metadata(u64 **metadata, int nr_cpu) +{ + int i; + + for (i =3D 0; i < nr_cpu; i++) + zfree(&metadata[i]); + free(metadata); +} + +static u64 **arm_spe__alloc_metadata(struct perf_record_auxtrace_info *inf= o, + u64 *ver, int *nr_cpu) +{ + u64 *ptr =3D (u64 *)info->priv; + u64 metadata_size; + u64 **metadata =3D NULL; + int hdr_sz, per_cpu_sz, i; + + metadata_size =3D info->header.size - + sizeof(struct perf_record_auxtrace_info); + + /* Metadata version 1 */ + if (metadata_size =3D=3D ARM_SPE_AUXTRACE_V1_PRIV_SIZE) { + *ver =3D 1; + *nr_cpu =3D 0; + /* No per CPU metadata */ + return NULL; + } + + *ver =3D ptr[ARM_SPE_HEADER_VERSION]; + hdr_sz =3D ptr[ARM_SPE_HEADER_SIZE]; + *nr_cpu =3D ptr[ARM_SPE_CPUS_NUM]; + + metadata =3D calloc(*nr_cpu, sizeof(*metadata)); + if (!metadata) + return NULL; + + /* Locate the start address of per CPU metadata */ + ptr +=3D hdr_sz; + per_cpu_sz =3D (metadata_size - (hdr_sz * sizeof(u64))) / (*nr_cpu); + + for (i =3D 0; i < *nr_cpu; i++) { + metadata[i] =3D arm_spe__alloc_per_cpu_metadata(ptr, per_cpu_sz); + if (!metadata[i]) + goto err_per_cpu_metadata; + + ptr +=3D per_cpu_sz / sizeof(u64); + } + + return metadata; + +err_per_cpu_metadata: + arm_spe__free_metadata(metadata, *nr_cpu); + return NULL; +} + static void arm_spe_free_queue(void *priv) { struct arm_spe_queue *speq =3D priv; @@ -1050,6 +1121,7 @@ static void arm_spe_free(struct perf_session *session) auxtrace_heap__free(&spe->heap); arm_spe_free_events(session); session->auxtrace =3D NULL; + arm_spe__free_metadata(spe->metadata, spe->metadata_nr_cpu); free(spe); } =20 @@ -1267,15 +1339,26 @@ int arm_spe_process_auxtrace_info(union perf_event = *event, const char *cpuid =3D perf_env__cpuid(session->evlist->env); u64 midr =3D strtol(cpuid, NULL, 16); struct arm_spe *spe; - int err; + u64 **metadata =3D NULL; + u64 metadata_ver; + int nr_cpu, err; =20 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info)= + min_sz) return -EINVAL; =20 + metadata =3D arm_spe__alloc_metadata(auxtrace_info, &metadata_ver, + &nr_cpu); + if (!metadata && metadata_ver !=3D 1) { + pr_err("Failed to parse Arm SPE metadata.\n"); + return -EINVAL; + } + spe =3D zalloc(sizeof(struct arm_spe)); - if (!spe) - return -ENOMEM; + if (!spe) { + err =3D -ENOMEM; + goto err_free_metadata; + } =20 err =3D auxtrace_queues__init(&spe->queues); if (err) @@ -1284,8 +1367,14 @@ int arm_spe_process_auxtrace_info(union perf_event *= event, spe->session =3D session; spe->machine =3D &session->machines.host; /* No kvm support */ spe->auxtrace_type =3D auxtrace_info->type; - spe->pmu_type =3D auxtrace_info->priv[ARM_SPE_PMU_TYPE]; + if (metadata_ver =3D=3D 1) + spe->pmu_type =3D auxtrace_info->priv[ARM_SPE_PMU_TYPE]; + else + spe->pmu_type =3D auxtrace_info->priv[ARM_SPE_PMU_TYPE_V2]; spe->midr =3D midr; + spe->metadata =3D metadata; + spe->metadata_ver =3D metadata_ver; + spe->metadata_nr_cpu =3D nr_cpu; =20 spe->timeless_decoding =3D arm_spe__is_timeless_decoding(spe); =20 @@ -1346,5 +1435,7 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, session->auxtrace =3D NULL; err_free: free(spe); +err_free_metadata: + arm_spe__free_metadata(metadata, nr_cpu); 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B7BC0339; Thu, 3 Oct 2024 11:43:56 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2CD923F58B; Thu, 3 Oct 2024 11:43:25 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Besar Wicaksono , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Will Deacon , John Garry , James Clark , Mike Leach Cc: Leo Yan Subject: [PATCH v4 5/5] perf arm-spe: Dump metadata with version 2 Date: Thu, 3 Oct 2024 19:43:02 +0100 Message-Id: <20241003184302.190806-6-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241003184302.190806-1-leo.yan@arm.com> References: <20241003184302.190806-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit dumps metadata with version 2. It dumps metadata for header and per CPU data respectively in the arm_spe_print_info() function to support metadata version 2 format. After: 0 0 0x3c0 [0x1b0]: PERF_RECORD_AUXTRACE_INFO type: 4 Header version :2 Header size :4 PMU type v2 :13 CPU number :8 Magic :0x1010101010101010 CPU # :0 Num of params :3 MIDR :0x410fd801 PMU Type :-1 Min Interval :0 Magic :0x1010101010101010 CPU # :1 Num of params :3 MIDR :0x410fd801 PMU Type :-1 Min Interval :0 Magic :0x1010101010101010 CPU # :2 Num of params :3 MIDR :0x410fd870 PMU Type :13 Min Interval :1024 Magic :0x1010101010101010 CPU # :3 Num of params :3 MIDR :0x410fd870 PMU Type :13 Min Interval :1024 Magic :0x1010101010101010 CPU # :4 Num of params :3 MIDR :0x410fd870 PMU Type :13 Min Interval :1024 Magic :0x1010101010101010 CPU # :5 Num of params :3 MIDR :0x410fd870 PMU Type :13 Min Interval :1024 Magic :0x1010101010101010 CPU # :6 Num of params :3 MIDR :0x410fd850 PMU Type :-1 Min Interval :0 Magic :0x1010101010101010 CPU # :7 Num of params :3 MIDR :0x410fd850 PMU Type :-1 Min Interval :0 Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 54 +++++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 5 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 8b2af1c7dc9b..13fd2c8afebd 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -1133,16 +1133,60 @@ static bool arm_spe_evsel_is_auxtrace(struct perf_s= ession *session, return evsel->core.attr.type =3D=3D spe->pmu_type; } =20 -static const char * const arm_spe_info_fmts[] =3D { - [ARM_SPE_PMU_TYPE] =3D " PMU Type %"PRId64"\n", +static const char * const metadata_hdr_v1_fmts[] =3D { + [ARM_SPE_PMU_TYPE] =3D " PMU Type :%"PRId64"\n", + [ARM_SPE_PER_CPU_MMAPS] =3D " Per CPU mmaps :%"PRId64"\n", }; =20 -static void arm_spe_print_info(__u64 *arr) +static const char * const metadata_hdr_fmts[] =3D { + [ARM_SPE_HEADER_VERSION] =3D " Header version :%"PRId64"\n", + [ARM_SPE_HEADER_SIZE] =3D " Header size :%"PRId64"\n", + [ARM_SPE_PMU_TYPE_V2] =3D " PMU type v2 :%"PRId64"\n", + [ARM_SPE_CPUS_NUM] =3D " CPU number :%"PRId64"\n", +}; + +static const char * const metadata_per_cpu_fmts[] =3D { + [ARM_SPE_MAGIC] =3D " Magic :0x%"PRIx64"\n", + [ARM_SPE_CPU] =3D " CPU # :%"PRId64"\n", + [ARM_SPE_CPU_NR_PARAMS] =3D " Num of params :%"PRId64"\n", + [ARM_SPE_CPU_MIDR] =3D " MIDR :0x%"PRIx64"\n", + [ARM_SPE_CPU_PMU_TYPE] =3D " PMU Type :%"PRId64"\n", + [ARM_SPE_CAP_MIN_IVAL] =3D " Min Interval :%"PRId64"\n", +}; + +static void arm_spe_print_info(struct arm_spe *spe, __u64 *arr) { + unsigned int i, cpu, hdr_size, cpu_num, cpu_size; + const char * const *hdr_fmts; + if (!dump_trace) return; =20 - fprintf(stdout, arm_spe_info_fmts[ARM_SPE_PMU_TYPE], arr[ARM_SPE_PMU_TYPE= ]); + if (spe->metadata_ver =3D=3D 1) { + cpu_num =3D 0; + hdr_size =3D ARM_SPE_AUXTRACE_V1_PRIV_MAX; + hdr_fmts =3D metadata_hdr_v1_fmts; + } else { + cpu_num =3D arr[ARM_SPE_CPUS_NUM]; + hdr_size =3D arr[ARM_SPE_HEADER_SIZE]; + hdr_fmts =3D metadata_hdr_fmts; + } + + for (i =3D 0; i < hdr_size; i++) + fprintf(stdout, hdr_fmts[i], arr[i]); + + arr +=3D hdr_size; + for (cpu =3D 0; cpu < cpu_num; cpu++) { + /* + * The parameters from ARM_SPE_MAGIC to ARM_SPE_CPU_NR_PARAMS + * are fixed. The sequential parameter size is decided by the + * field 'ARM_SPE_CPU_NR_PARAMS'. + */ + cpu_size =3D (ARM_SPE_CPU_NR_PARAMS + 1) + arr[ARM_SPE_CPU_NR_PARAMS]; + for (i =3D 0; i < cpu_size; i++) + fprintf(stdout, metadata_per_cpu_fmts[i], arr[i]); + arr +=3D cpu_size; + } } =20 static void arm_spe_set_event_name(struct evlist *evlist, u64 id, @@ -1407,7 +1451,7 @@ int arm_spe_process_auxtrace_info(union perf_event *e= vent, spe->auxtrace.evsel_is_auxtrace =3D arm_spe_evsel_is_auxtrace; session->auxtrace =3D &spe->auxtrace; =20 - arm_spe_print_info(&auxtrace_info->priv[0]); + arm_spe_print_info(spe, &auxtrace_info->priv[0]); =20 if (dump_trace) return 0; --=20 2.34.1