From nobody Thu Nov 28 05:46:27 2024 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4A9E1AB506; Thu, 3 Oct 2024 17:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974896; cv=none; b=o+qoFOdcugS6Ma1UzzrZ6uI0IkP66/XnsPtLH7kNz8/vV5RxNLLN4MqtP7xknbU4c+rcZV7Tj6SPM1Qlk9mqG5xXsYSWNrOojk1N3DWkwQ1U2M/EKV81uhM9gVy6Xt4geCElimdmzBHtcLLR1PKUlU7l9czZuc4Cf1okHaeMbnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974896; c=relaxed/simple; bh=oiOYHR3d4RoyWI3MaPFRg53fp+uprCbyUtfxMTPBMRU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=H8Xaknc1EzCa0IKXq+DOc2eJzEIT9EoQfqXOlTkC0aQhy2se6qg/x7bgfVQk5aUephp6NDrwJR0WF1IKaoiTP2c1ileksrAzohJ64HGv2Kd8pxpmWCZte4vUPmW3myrb6RTrzPwWb4TjsUWe1LH7RkOFFXW7GGxmt5BlrWuVp8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=LzZn+gWS; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="LzZn+gWS" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 493H1J8e008885; Thu, 3 Oct 2024 12:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727974879; bh=tj+udxRt59HTIlu943j0s/KqJp2ZLN/fW2bY75qirRs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LzZn+gWSBYS6RApR12u008YD0ECt/oLMUBk0wLh+SnAW8KsuqB3/kabxeInVE6fd6 XI1kV88aFQn3LfUDSbKuRwqAARRwrmDZVFgiolwLJn3cBgjUP7/i8qzzrFe2Y0MfcM d0hWO1hF9xaQkNVM+OJ++6lFLMmZYDuhk1hXaUeo= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1JbV083232; Thu, 3 Oct 2024 12:01:19 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 3 Oct 2024 12:01:18 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 3 Oct 2024 12:01:18 -0500 Received: from ula0226330.dhcp.ti.com (ula0226330.dhcp.ti.com [128.247.81.173] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1IJa034882; Thu, 3 Oct 2024 12:01:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH v12 1/5] arm64: dts: ti: k3-am62: Add M4F remoteproc node Date: Thu, 3 Oct 2024 12:01:14 -0500 Message-ID: <20241003170118.24932-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241003170118.24932-1-afd@ti.com> References: <20241003170118.24932-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. Disable by default as this node is not complete until mailbox data is provided in the board level DT. Signed-off-by: Hari Nagalla Signed-off-by: Andrew Davis Tested-by: Wadim Egorov --- arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am62-mcu.dtsi index bb43a411f59b2..68e906796aefe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -174,4 +174,17 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_m4fss: m4fss@5000000 { + compatible =3D "ti,am64-m4fss"; + reg =3D <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names =3D "iram", "dram"; + resets =3D <&k3_reset 9 1>; + firmware-name =3D "am62-mcu-m4f0_0-fw"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <9>; + ti,sci-proc-ids =3D <0x18 0xff>; + status =3D "disabled"; + }; }; --=20 2.39.2 From nobody Thu Nov 28 05:46:27 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C5761EB31; Thu, 3 Oct 2024 17:01:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974889; cv=none; b=PRIOL3hiZVapVqQlXHhW2+fZweCKr8AvNEw+VNsjfLhxIjGP3SjkY1QHgJHI7G8OULStAiKacw5+fct7ggATpxVS7LAv681RGTLQ98cCINTMPdgeErb5jJVw74CZicm4EoLJ72i1ZZVTTjtrBBg2vvX7HkPyqj1XLurDPH2i3Q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974889; c=relaxed/simple; bh=IP+QVtSF3jwPNMeOJ0TxzVmLpPC/ev7AEsN/Z6felv8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ckRxbhVKx7y2U35GRYSUA/YJp15hoLHigNwXJKzkE+eamKFXpOaLSY0GsgxJD9yVQn/7BJ4R/BxVLqpzTwba5hszu9o48zK81DSJzspPMh+X+x18+IMQmHQA/MIuhL2k0ATdEyaYclvkyZ7q2MqVfc3+xvr/CT8vUqthD++zNMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fbZ6t3UH; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fbZ6t3UH" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 493H1Jpj022823; Thu, 3 Oct 2024 12:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727974879; bh=keA83r8ebhZaOZjYQh4+oaPatkLOV6zBeVEOuCilGSg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fbZ6t3UHQhfCHMOevOKqyZdVU3JJPorhg0nzVvvZoYABjS/u6AMnufUizKNMmhhU0 EfqydLYniQzjMmF2Td2VOUe1IUNGgWGORkQ+DNwk9j+muV0HxqrOqHbiKxO8mRt8EL O+TuY63fKF70qUapqOPzeSP5mWItKxeJSU3LsrH0= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 493H1JJt047726 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Oct 2024 12:01:19 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 3 Oct 2024 12:01:18 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 3 Oct 2024 12:01:18 -0500 Received: from ula0226330.dhcp.ti.com (ula0226330.dhcp.ti.com [128.247.81.173] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1IJb034882; Thu, 3 Oct 2024 12:01:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH v12 2/5] arm64: dts: ti: k3-am625-sk: Add M4F remoteproc node Date: Thu, 3 Oct 2024 12:01:15 -0500 Message-ID: <20241003170118.24932-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241003170118.24932-1-afd@ti.com> References: <20241003170118.24932-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor does not have an MMU, and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla Signed-off-by: Andrew Davis --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 44ff67b6bf1e4..6957b3e44c82f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -56,6 +56,18 @@ linux,cma { linux,cma-default; }; =20 + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -464,6 +476,13 @@ mbox_m4_0: mbox-m4-0 { }; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + &usbss0 { bootph-all; status =3D "okay"; --=20 2.39.2 From nobody Thu Nov 28 05:46:27 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A46A1A7043; Thu, 3 Oct 2024 17:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974890; cv=none; b=M6ZR6qjHwsXw8D+NiEmZFs45gL+xBD6EaB2Dm+7hUxleXKUSv2F1TW2QHeHMb7IDJdG9OyqNBhrDWDnMso5P0WaNkTG3jLrVDOi/VL2p6AK4rP1Iffx6QPvXwld6fAbwPKbzTGuwx609vEm2jJ5grWUHvvYgNS3j4QpRDxBq6cg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974890; c=relaxed/simple; bh=8jASYYoaxkhcRfzV8vhnqOX48NGySocFuCNn9+TL1aQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=i9HDSXUbvKgxlPdYLCo0cIxmF2r8NcsAKlub3X3weWN9gA1IR+iL++WZnK10Pbp2R8fGXAYJ8n3MKMWYyBeNN2dlvgb5LSGl4+Jy4Ww2fmBgp3vQFxcwti4EkyPC4EYpn2zK1uhTqzNcR1ch3nM/KLl0m9lZM+vA1g5A6IsQzEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VKD2e4rz; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VKD2e4rz" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 493H1Jwb050024; Thu, 3 Oct 2024 12:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727974879; bh=5OXZ7TNWoedd0uvQusRZDSQMlO93fpQ7zDO/4wd4lFU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VKD2e4rz8TRNZD1Z4vJhzp9Fa1ADeRbaYZMfTUa9ECYD5MPApwwaYBK1ZVsySaT+R 2XmBvfmfkSq4xLlJzgezMhtCjzbNYWjsrPfQBOQeP7UWZxao7X0BpjeO5iUEi216TG nuw4IWdtsexauPrALjTdsMHCdQUfR//CfboycM0k= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1Jbn083229; Thu, 3 Oct 2024 12:01:19 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 3 Oct 2024 12:01:18 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 3 Oct 2024 12:01:18 -0500 Received: from ula0226330.dhcp.ti.com (ula0226330.dhcp.ti.com [128.247.81.173] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1IJc034882; Thu, 3 Oct 2024 12:01:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH v12 3/5] arm64: dts: ti: k3-am64: Add M4F remoteproc node Date: Thu, 3 Oct 2024 12:01:16 -0500 Message-ID: <20241003170118.24932-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241003170118.24932-1-afd@ti.com> References: <20241003170118.24932-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. Disable by default as this node is not complete until mailbox data is provided in the board level DT. Signed-off-by: Hari Nagalla Signed-off-by: Andrew Davis Tested-by: Wadim Egorov --- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am64-mcu.dtsi index ad4bed5d3f9eb..a243c981e8535 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -161,4 +161,17 @@ mcu_esm: esm@4100000 { /* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */ ti,esm-pins =3D <0>, <1>, <2>, <85>; }; + + mcu_m4fss: m4fss@5000000 { + compatible =3D "ti,am64-m4fss"; + reg =3D <0x00 0x5000000 0x00 0x30000>, + <0x00 0x5040000 0x00 0x10000>; + reg-names =3D "iram", "dram"; + resets =3D <&k3_reset 9 1>; + firmware-name =3D "am64-mcu-m4f0_0-fw"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <9>; + ti,sci-proc-ids =3D <0x18 0xff>; + status =3D "disabled"; + }; }; --=20 2.39.2 From nobody Thu Nov 28 05:46:27 2024 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF5641A7266; Thu, 3 Oct 2024 17:01:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974891; cv=none; b=TlQKqx3Zg8ENRy4FJXeK5GoBVxBJgKzM5KFfeJ65cWVASlbF+aSC3f7bi8CLzxwe5LBz0Af6SKlFT5Zgrjbjv2RiXEu9ILKvFHMb4Q3DePOEmOxP2xfBB48ie6dtHkJ0AO3kuU6IZIj3B8tgXjlukGEuu26NF9+8TDqbtb7iG4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974891; c=relaxed/simple; bh=rsjyAwUdZPUtpq7X0EOtW5mmNPwrNeArEGoNK40w5+Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ViG4vB1u+0huiG7xL7PIDOOE4f1GSGKPWlji7qrnJbZxjwDwzxQGBj5/ePy7L5sSh3FIxSC9VwjicvhpTkleYj2vLixBzR1Ugx82lhD1+ALtPLzsrZe8k9BssT8tVjzVo/O75/f8Prh+eTROkgmUooL3KV0m5zOQGCa4GTPfTEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=yuUBQRzy; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="yuUBQRzy" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 493H1JWf050026; Thu, 3 Oct 2024 12:01:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727974879; bh=6er3fLH1h7Mp2w3l0QFcwApkR0btaLUtHcIDiCixkb8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yuUBQRzyrQc5Lv09xR4Xrcmz7Ilvkd+r2UhsFygV3dDkZW3UzDBn+5w1RIEW+qj1M pEO124soQK0WAnyP90RrXLjpyOfj/qJskYrk16wEb2SExNetZ2SjgW1zfo0kWMMNXn ziG/JWK5GUaxRsdv4xE07GvEJmy1UFAeuSel2gfo= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 493H1Jne047732 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 3 Oct 2024 12:01:19 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 3 Oct 2024 12:01:18 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 3 Oct 2024 12:01:18 -0500 Received: from ula0226330.dhcp.ti.com (ula0226330.dhcp.ti.com [128.247.81.173] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1IJd034882; Thu, 3 Oct 2024 12:01:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH v12 4/5] arm64: dts: ti: k3-am642-sk: Add M4F remoteproc node Date: Thu, 3 Oct 2024 12:01:17 -0500 Message-ID: <20241003170118.24932-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241003170118.24932-1-afd@ti.com> References: <20241003170118.24932-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor does not have an MMU, and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 86369525259c3..26d4ad5e96f1c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -99,6 +99,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { no-map; }; =20 + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; @@ -681,6 +693,13 @@ &main_r5fss1_core1 { <&main_r5fss1_core1_memory_region>; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + &ecap0 { status =3D "okay"; /* PWM is available on Pin 1 of header J3 */ --=20 2.39.2 From nobody Thu Nov 28 05:46:27 2024 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A98A41AB505; Thu, 3 Oct 2024 17:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974897; cv=none; b=eOmYcAMCxYxcpWwekbnIiwVEgzR/e2tvu8xEotjltK8HBF067MkEN4AlacnNugpZAFKs5J8cJ6ZPZqgcPz5TMG+Kislq6EMV5STUaOmzJYe2Z1ivrotor7pDJzJ3WqzAPZ4eXh/KPMcplP2ApNNCyHr6MPP/w7xiHoUFp+DGK2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727974897; c=relaxed/simple; bh=xHdJpYqa3TXOA+dz+X8uvcICfSTHlkkpOc84aJoiLGM=; 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Thu, 3 Oct 2024 12:01:18 -0500 Received: from ula0226330.dhcp.ti.com (ula0226330.dhcp.ti.com [128.247.81.173] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 493H1IJe034882; Thu, 3 Oct 2024 12:01:18 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH v12 5/5] arm64: dts: ti: k3-am642-evm: Add M4F remoteproc node Date: Thu, 3 Oct 2024 12:01:18 -0500 Message-ID: <20241003170118.24932-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241003170118.24932-1-afd@ti.com> References: <20241003170118.24932-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU domain. This core can be used by non safety applications as a remote processor. When used as a remote processor with virtio/rpmessage IPC, two carveout reserved memory nodes are needed. The first region is used as a DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each rproc device. The M4F processor does not have an MMU, and as such requires the exact memory used by the firmware to be set-aside. Signed-off-by: Hari Nagalla Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index 97ca16f00cd26..19d7ed8a9ea0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -101,6 +101,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { no-map; }; =20 + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: ipc-memories@a5000000 { reg =3D <0x00 0xa5000000 0x00 0x00800000>; alignment =3D <0x1000>; @@ -776,6 +788,13 @@ &main_r5fss1_core1 { <&main_r5fss1_core1_memory_region>; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + &serdes_ln_ctrl { idle-states =3D ; }; --=20 2.39.2