From nobody Thu Nov 28 08:46:39 2024 Received: from mail-oi1-f174.google.com (mail-oi1-f174.google.com [209.85.167.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0427312F588 for ; Thu, 3 Oct 2024 07:01:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938919; cv=none; b=bC0lmEke6qgivnBFRvEwSYAM+ePBsYGugk9E2XIyF9r+dg7nsJ3oZGYDuG6IMAsHJGot4+Jrum7psoNJ50ddRxvvJIkYB2lZ+FH9vItJE2bxe3ti4NzFAUwRbOJ9Y33Bu8Wfhp/61fUCj7ibzpKv/FedNaNwL9JEPxcD7REWezA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938919; c=relaxed/simple; bh=rK33i3jEG4kX5NudfttSmDhiUicK7UXMvpbOl5/ElaA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DNLM7xeYxex29GyEPXW7J87hB51XdILIDQsdy7GT8QXi+eB8vmUbziV19z7sBPNstpesxrjFRGMCQLpuXzRX9glAt5klHxqmuLlvDpq3GMmyYg8SVlOsUVnUveYGrcwRX0h/AxSEKE3CuBm3FtdfeoHd1vgUOPfRRERWz5cd30g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=iDuz8Yh8; arc=none smtp.client-ip=209.85.167.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="iDuz8Yh8" Received: by mail-oi1-f174.google.com with SMTP id 5614622812f47-3e03e9d1f8dso376448b6e.2 for ; Thu, 03 Oct 2024 00:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938917; x=1728543717; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x3JpBIk+dizy5e9goqMv92qE1UL5hLhhWiLghC/pf7k=; b=iDuz8Yh8DHYmxcjuzMTAXxsUxngMvH36HI84w1hjy0HQC8+ldnJiZ6nE2a3xMZqyD+ ImeNjZErtLhXfkxi9HUwVurpLqc2fDg47HVDydU4k44R6KmgLw/uFc1BgTmz0kKhcFVz LWadNmH+8RhC0l6+OkQEKmZaTsUKFjZEXtLjk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938917; x=1728543717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x3JpBIk+dizy5e9goqMv92qE1UL5hLhhWiLghC/pf7k=; b=MsiACwfUS6ohWvwh2DI1azURpVNMIlZ2o1qe0UhTXcc2P1ZvuqK0s+ej/g0vSMpdB9 f+67i9eS/WoKOlMUnzUFPPPxKRBdp4pIUxSIuNfwRD3U68mmktcTO7QXtCYXYDiga7at qPYdmYZCHR/eVyO86Giy1FJ233Rr88qsYgYWOZbpxBewBvk8uZ6LT3mV2Nj/OK5d16JP MW9eZU8m9PBssTB0g/qKrVTbI0rjV7ODcQM01uH3p2Zjv2xPeHFDMJKTqaShbEFT9A6v YzO0KCB3TXvBBJpI66gZ6levRBKA6e++hesvxwDBAaf5LLKNk6Hh0RTnBYND7BE6QYZn 025A== X-Forwarded-Encrypted: i=1; AJvYcCVmxE5u/o+moOSW5UvyVfNP06ypuIYv7PK9plH2Mp4Tmct8u2dVEP3HUyOdULn+E0yBfYisV5p3dSdnS/4=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1hqNS1fc0Vvx3lq3yuYrJAhJEvVJnsyaT5dJU63l7gXKl4g45 6qgxifwzyQxnv0zbc/l5QPF/JOk3/HKN/4579Gln47qEyjfbn5+ta/zjbKoeKA== X-Google-Smtp-Source: AGHT+IFha9Fj/OXST1rmXZUQpjR/6jvkkRdPdpqAlTCawnloKZPpCJkNTYsOHYUG1EKOL7N+SHqhUg== X-Received: by 2002:a05:6808:13c3:b0:3e3:9f31:c8cc with SMTP id 5614622812f47-3e3b4181612mr4830531b6e.47.1727938917115; Thu, 03 Oct 2024 00:01:57 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:01:56 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 4/9] arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes Date: Thu, 3 Oct 2024 14:59:58 +0800 Message-ID: <20241003070139.1461472-5-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 719d2409a7db..49d4180595a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2183,6 +2183,64 @@ ccusys: clock-controller@17200000 { #clock-cells =3D <1>; }; =20 + video_decoder: video-decoder@18000000 { + compatible =3D "mediatek,mt8188-vcodec-dec"; + reg =3D <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges =3D <0 0 0 0x18000000 0 0x26000>; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + mediatek,scp =3D <&scp>; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x10000 0 0x800>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + larb23: smi@1800d000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1800d000 0 0x1000>; @@ -2234,6 +2292,31 @@ larb19: smi@1a010000 { mediatek,smi =3D <&vdo_smi_common>; }; =20 + video_encoder: video-encoder@1a020000 { + compatible =3D "mediatek,mt8188-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks =3D <&vencsys CLK_VENC1_VENC>; + clock-names =3D "venc_sel"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,scp =3D <&scp>; + }; + disp_dsi: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; --=20 2.46.1.824.gd892dcdcdd-goog