From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF2EE83A14 for ; Thu, 3 Oct 2024 07:01:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938911; cv=none; b=KJYl1PfDWTW7RsUAo28SDtyEEGjZm2oWJysCJRcD4MNOYLGlStrFNOxAJUoBh/fNpjvBzxljJsyV/lYShEk+VPNOtNza3ArzdbQyrf6FyFs+3hSxC7D6fX6RdRFKKHdX+6RaTAH7r0azRjoYlh/NA7230jZh8PzabHXyuumGAeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938911; c=relaxed/simple; bh=8UypYrlWqk4JErxk8uVv4PjIsoX+682r515rUWNlgKs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Uf/sSqTz4anzw+QJ9W9tWso2oIQa3u9riFwE7xobzG9EYn6z6uZHBJmCtszLxXUez6EyNkWXp1Nk05DbliJTEu5dfCA2pdqsNEeojSaivMRFmRVqlPajWJ1+ZYIfXwnshk57prZW8o+g+ka3bGDmwHJZeHCegpon+RTaXMk00NY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=T+vBdrG5; arc=none smtp.client-ip=209.85.215.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="T+vBdrG5" Received: by mail-pg1-f182.google.com with SMTP id 41be03b00d2f7-7e6afa8baeaso479165a12.3 for ; Thu, 03 Oct 2024 00:01:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938909; x=1728543709; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oe/n9hHH0mKojPtYx3rZSCjoPpBX5CErclQAFbwUbmw=; b=T+vBdrG5qNb/JbdR9bU6I/Z+OceRF3Wn8FdB2lb5Ic5BHaDASu3WnqRfh9++bjaw0u p3b/l6zZkmSMfqWQ+bzLY93b+Wm5driu0OIrdvy0yG+vuc61b6I7kZbYwqSlbZnMamHs jsLExpK3xSI5WkEhkNkZXQPZdfEhfdFaALVIM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938909; x=1728543709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oe/n9hHH0mKojPtYx3rZSCjoPpBX5CErclQAFbwUbmw=; b=oalhmTQ7QHa97haoe7UYuTj0OSFziJt2F2d9iRLvEBWaZnwlKyPUn+EhiavMFHWJKz L76iUaS9/Z9suRIdwpHfbPmLDbr71aFcc12fws/RgrpZ+rsdMCKMwtH7ryG3txF1wpsG b3HOlFto+EXPguTRXbyLD5fjgvmTSvvW4WVHXlNmeXtRaA0NurFGCvoBU/kKMmVVOCbj jjBCd47fpQg+7J6b7pvEL6iKBV7IpDo3N9WwsfZazH0SqZv+Td1qcYCwJi4EWRfd9Ti/ Q70bzDAYaN4qg+dk9cj0+RHAocEdYNS/zY2DJbeNxwfDY4eytq48tHINrNzkcOq0cvBX beww== X-Forwarded-Encrypted: i=1; AJvYcCX1CRvqsviNGDe0/GvKO5HxFKxkwZ4CsQNnF38qXV501XgbV/OLecFu8JgrFxPCBsMxunPBEBpqVGPQbKQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yy6pWlVd0k5zQQBshKlugIBZ0gZNYy7ixbayVAckYYsz4rtuK+N gpDtFl0s5vCEtk6i2VpYTLCb6J11dUqCqZAxD6s0wXPU0YeBCgtdRyz500E/gw== X-Google-Smtp-Source: AGHT+IHnCV7kmSOR4DccXhZDS0a+MPrHfdhqHJncrbL+gRJDUqEcGORVVOObqAVae6mIpY+s/kJRIQ== X-Received: by 2002:a05:6a20:c797:b0:1d5:388f:275c with SMTP id adf61e73a8af0-1d5db14c8d3mr8114513637.20.1727938909295; Thu, 03 Oct 2024 00:01:49 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:01:48 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 1/9] arm64: dts: mediatek: mt8188: Assign GCE aliases Date: Thu, 3 Oct 2024 14:59:55 +0800 Message-ID: <20241003070139.1461472-2-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create and assign aliases for the MediaTek GCE mailboxes. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index bf15ac9901da..10195a4e4e9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -23,6 +23,11 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + gce0 =3D &gce0; + gce1 =3D &gce1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A756C126C04 for ; Thu, 3 Oct 2024 07:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938914; cv=none; b=ssqbfcB9CftMKvo2rjEjQajbFhX+aH0wve21zkoTgk9HHX1726/CihEoqk7i39DYRe7EB5jTwOlnLT/bb+RuGFDp0Fh0hH18X1UPk5VkLnVcZztkwa5JhAzl4JvEg4bvcoxvOM9bgpUIPTMgkALWTVpXOewl4AYOh8Nrfjtx30w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938914; c=relaxed/simple; bh=0mpLEj9yVGBPVockx2HmuEIpJAkRSQyoa+ZWdgYrad8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G3XlSDaH2WIVE7Q1/wt1ThhxORk7I4jRZkHW3YWOLUz6w6psCdYGqP/54qY+rK0rR8koP4AXUw5fLyISIwuTuRjD8iNsAEbml+bmPkOmpfmQJYcdX2EHWNhAp9kX2ZGodU2HQ7dj3XvVas15Gk/SEN12uE2pB8R8cHbmBD79hb0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=Cq4uctbo; arc=none smtp.client-ip=209.85.215.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Cq4uctbo" Received: by mail-pg1-f182.google.com with SMTP id 41be03b00d2f7-7db90a28cf6so1148676a12.0 for ; Thu, 03 Oct 2024 00:01:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938912; x=1728543712; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aWjhvVZMIKZFWQGVvBTmWBQtbFvDraf8qJPfgaxmV8E=; b=Cq4uctbo6qGuDjh2SiJMCTOdRZKgcche+M3fMRNOPAYWf2oobPW0FXlOK2/0qAxKl+ FrR3vzWGg7SR3HocOPrgd6ofnMUKTNsroDD7X4+/iXsp04+JTE1C0BOkb5HwYbty0JMJ beMA5OcQkp8aBqYAp8RUYEFT6WPzHpnuvZb8I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938912; x=1728543712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aWjhvVZMIKZFWQGVvBTmWBQtbFvDraf8qJPfgaxmV8E=; b=Jb8dHlJqtu/p+NmcquMkLN2Za46r/5qCZmSAwSLgjl4t7nNm+YT7tRFaAm6glmUB+W 5PgHCE3IBWBRUIxdxuqaQRvtKMi0DmdQqPFPWAtvYmdENdRqxW0Psltiosyo3EWYSNDO AqWk/A/bvbTfMtk2nI+3DHAsZKHw1fkHhBoBVxtVw0C+z9iaoYeZHvSTMxQRP8G8jJvd m4Th1WJWMtUo+/pkMZaPKekG4dPPB0jRUi1Ypa4YfhXRE1WfzFrJSfm0+AThJbftRs7z sqHWiBmyg1FY2zsu8927sRIsF2PKIrT5g6JoextAPs1bFNF0vpHaF/yRAJtFvhmNQ4by txdw== X-Forwarded-Encrypted: i=1; AJvYcCWpbk+eQuG48fKbO/reP79WUaCX8SRB0xluJ/JBkRJ7hg+1eY6I7Oqm4TpnHFqpKTqmLaALrh056/bxf/k=@vger.kernel.org X-Gm-Message-State: AOJu0Yz84XRzSNQdtNCdVLCH4gUm899kntryb6UZQkbdA3072SN1chVi hjiYcNPd0DBQNgDwslwdK+eT/ZriJ8dtQKsTThaaJmydz/V4xc7rqDHD3JKqizCS7T2i3aHmqTa CFg== X-Google-Smtp-Source: AGHT+IGhrhDbzrLuVxP6LwbUL6ZECwPUpOpG8SVbkabencZcbtS6o7ftPals6nEeuoFPkwElfXd0PA== X-Received: by 2002:a05:6a20:c89b:b0:1d5:10c1:4713 with SMTP id adf61e73a8af0-1d6d3a8b86emr3319481637.14.1727938911986; Thu, 03 Oct 2024 00:01:51 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:01:51 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 2/9] arm64: dts: mediatek: mt8188: Add PCIe nodes Date: Thu, 3 Oct 2024 14:59:56 +0800 Message-ID: <20241003070139.1461472-3-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe node and the associated PHY node. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao Reviewed-by: Macpaul Lin --- Changes in v2: - add linux,pci-domain to PCIe node - add power domain to PCIe PHY node. The binding patch: https://lore.kernel.org/all/20240926101804.22471-1-macpaul.lin@mediatek.c= om/ arch/arm64/boot/dts/mediatek/mt8188.dtsi | 64 ++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 10195a4e4e9d..23101d316c4e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1763,6 +1763,54 @@ xhci0: usb@112b0000 { status =3D "disabled"; }; =20 + pcie: pcie@112f0000 { + compatible =3D "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; + reg =3D <0 0x112f0000 0 0x2000>; + reg-names =3D "pcie-mac"; + ranges =3D <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; + bus-range =3D <0 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", "tl_32k", + "peri_26m", "peri_mem"; + + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + + iommu-map =3D <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; + iommu-map-mask =3D <0>; + + phys =3D <&pcieport PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + + power-domains =3D <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; + + resets =3D <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; + reset-names =3D "mac"; + + status =3D "disabled"; + + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + nor_flash: spi@1132c000 { compatible =3D "mediatek,mt8188-nor", "mediatek,mt8186-nor"; reg =3D <0 0x1132c000 0 0x1000>; @@ -1775,6 +1823,22 @@ nor_flash: spi@1132c000 { status =3D "disabled"; }; =20 + pciephy: t-phy@11c20700 { + compatible =3D "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; + ranges =3D <0 0 0x11c20700 0x700>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; + status =3D "disabled"; + + pcieport: pcie-phy@0 { + reg =3D <0 0x700>; + clocks =3D <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + i2c1: i2c@11e00000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11e00000 0 0x1000>, --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F4B3126C15 for ; Thu, 3 Oct 2024 07:01:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938916; cv=none; b=pI6a6TTc6dsRvaT1Duhauep5x/JEZdetAM09ONR3n+LeZ3sBPKtiuw5vkP6S2JwxJbpQX7EdkFEwbhQwD7JNMJnxG5597XLoDjvaPevosn1VC2Cg/sSV0ocAA014drUTa8HwwJnB+PE2uk9nKirm01Ir2OvVO03U9fbo6PY+JLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938916; c=relaxed/simple; bh=VESsjXVlk43UNjCparYvaPuSRFaK5WDMd0meG9wkXUE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CqQjY2h120FzoBdLow3qJKH+vyq2/Bz1Ezn0dFPVC6xqv10tf5VUgHolzaqd/5+LWycPdH5NLWaTZX0/yhGADTOf5vPrtKLu6iTGNQ1mJwwLj9sNJn/ld/S4xc6YiH0ZQBD5kF+fS3RxfKoPb3YoSgbkIF9oRLrGCGcDFxyXgPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=Zn8mNYI+; arc=none smtp.client-ip=209.85.210.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Zn8mNYI+" Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-71dd92e3718so300992b3a.3 for ; Thu, 03 Oct 2024 00:01:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938914; x=1728543714; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HEQbIZ1kOEPpCwOKFUVGo0GWUflsfubNyX6zy8z13EU=; b=Zn8mNYI+lCo260BjaP9z77icojAmY7ZVdNMR7zeJMaWK8SOgIFy9CLXca7ya+C0zvY Zz9kxTKZKQ4pz9rmoMn7E1MJJ4B1Z9gg2TrddnbliwpC3EOLQFfQd5p29hlcaPCSVo/c l8txAFot3DUF7ioPk03W+Itrhe7wtzbCGG3kM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938914; x=1728543714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HEQbIZ1kOEPpCwOKFUVGo0GWUflsfubNyX6zy8z13EU=; b=XIA1gYOAwyI2kL0RUBtiDSwjUhAO3rWfE/0BTuYd5Y5LvPfl+BDQFEKIjSzWENB8Ne URmRIbIJ9/Lrm3PAD+TnpWc1o+7lKBZKqJLrJm0J+VlxD+LOU5S6oNXJ5sTp/uOY5oLe Vu0TJR/DUSYBgCg5f7uTOcnE08ozD2biqNvczqTJMFBP1AmIUxV41A/JTmDlxVkJA+Y3 na3btw0bgM3prD/0er0nsBeYFA9AIgvoI45LIgP0nXpwmRs3XAHOsp9X9td2imJe7wM5 7G539MvbP29r8ApSWP8RrDrcd5Q6z/+EDi6ALOIjHh9dVXwWUphyVnUTaBuaAIIfqAhw Sa3A== X-Forwarded-Encrypted: i=1; AJvYcCX9xGl3Zpz8Ku6DRRDWkqXgzHDexty7utvEBdsTKuzhsjBZ8GbTR3oiapibgg57/abBiu5QsIJ45Uh+wpE=@vger.kernel.org X-Gm-Message-State: AOJu0YzKgRD5MfBS/8egXOkkxhSxCKva64PUoDej6B3rIDvMXMLFG5Qr wFwqnQ2OpBye2t6raAPEsD5s3XMZXfksyO5BX4wxxDuUZGjIa0nn9y5Kdf0hXA== X-Google-Smtp-Source: AGHT+IHOgHjrlMxD2zoM2IlOxDAItRRWCVLa9fyphfermgyfQ3vL8yGSyzT4jH4vijnNVzmVtvYQDQ== X-Received: by 2002:a05:6a00:178c:b0:70d:2fb5:f996 with SMTP id d2e1a72fcca58-71dc5c67164mr8309063b3a.11.1727938914540; Thu, 03 Oct 2024 00:01:54 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:01:54 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 3/9] arm64: dts: mediatek: mt8188: Add MIPI DSI nodes Date: Thu, 3 Oct 2024 14:59:57 +0800 Message-ID: <20241003070139.1461472-4-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MIPI DSI and the associated PHY node to support DSI panels. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 23101d316c4e..719d2409a7db 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1839,6 +1839,16 @@ pcieport: pcie-phy@0 { }; }; =20 + mipi_tx_phy: dsi-phy@11c80000 { + compatible =3D "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11c80000 0 0x1000>; + clocks =3D <&clk26m>; + clock-output-names =3D "mipi_tx0_pll"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + i2c1: i2c@11e00000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11e00000 0 0x1000>, @@ -2224,10 +2234,26 @@ larb19: smi@1a010000 { mediatek,smi =3D <&vdo_smi_common>; }; =20 + disp_dsi: dsi@1c008000 { + compatible =3D "mediatek,mt8188-dsi"; + reg =3D <0 0x1c008000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DSI0>, + <&vdosys0 CLK_VDO0_DSI0_DSI>, + <&mipi_tx_phy>; + clock-names =3D "engine", "digital", "hs"; + interrupts =3D ; + phys =3D <&mipi_tx_phy>; + phy-names =3D "dphy"; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + resets =3D <&vdosys0 MT8188_VDO0_RST_DSI0>; + status =3D "disabled"; + }; + vdosys0: syscon@1c01d000 { compatible =3D "mediatek,mt8188-vdosys0", "syscon"; reg =3D <0 0x1c01d000 0 0x1000>; #clock-cells =3D <1>; + #reset-cells =3D <1>; mboxes =3D <&gce0 0 CMDQ_THR_PRIO_4>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; }; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-oi1-f174.google.com (mail-oi1-f174.google.com [209.85.167.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0427312F588 for ; Thu, 3 Oct 2024 07:01:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938919; cv=none; b=bC0lmEke6qgivnBFRvEwSYAM+ePBsYGugk9E2XIyF9r+dg7nsJ3oZGYDuG6IMAsHJGot4+Jrum7psoNJ50ddRxvvJIkYB2lZ+FH9vItJE2bxe3ti4NzFAUwRbOJ9Y33Bu8Wfhp/61fUCj7ibzpKv/FedNaNwL9JEPxcD7REWezA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938919; c=relaxed/simple; bh=rK33i3jEG4kX5NudfttSmDhiUicK7UXMvpbOl5/ElaA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DNLM7xeYxex29GyEPXW7J87hB51XdILIDQsdy7GT8QXi+eB8vmUbziV19z7sBPNstpesxrjFRGMCQLpuXzRX9glAt5klHxqmuLlvDpq3GMmyYg8SVlOsUVnUveYGrcwRX0h/AxSEKE3CuBm3FtdfeoHd1vgUOPfRRERWz5cd30g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=iDuz8Yh8; arc=none smtp.client-ip=209.85.167.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="iDuz8Yh8" Received: by mail-oi1-f174.google.com with SMTP id 5614622812f47-3e03e9d1f8dso376448b6e.2 for ; Thu, 03 Oct 2024 00:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938917; x=1728543717; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x3JpBIk+dizy5e9goqMv92qE1UL5hLhhWiLghC/pf7k=; b=iDuz8Yh8DHYmxcjuzMTAXxsUxngMvH36HI84w1hjy0HQC8+ldnJiZ6nE2a3xMZqyD+ ImeNjZErtLhXfkxi9HUwVurpLqc2fDg47HVDydU4k44R6KmgLw/uFc1BgTmz0kKhcFVz LWadNmH+8RhC0l6+OkQEKmZaTsUKFjZEXtLjk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938917; x=1728543717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x3JpBIk+dizy5e9goqMv92qE1UL5hLhhWiLghC/pf7k=; b=MsiACwfUS6ohWvwh2DI1azURpVNMIlZ2o1qe0UhTXcc2P1ZvuqK0s+ej/g0vSMpdB9 f+67i9eS/WoKOlMUnzUFPPPxKRBdp4pIUxSIuNfwRD3U68mmktcTO7QXtCYXYDiga7at qPYdmYZCHR/eVyO86Giy1FJ233Rr88qsYgYWOZbpxBewBvk8uZ6LT3mV2Nj/OK5d16JP MW9eZU8m9PBssTB0g/qKrVTbI0rjV7ODcQM01uH3p2Zjv2xPeHFDMJKTqaShbEFT9A6v YzO0KCB3TXvBBJpI66gZ6levRBKA6e++hesvxwDBAaf5LLKNk6Hh0RTnBYND7BE6QYZn 025A== X-Forwarded-Encrypted: i=1; AJvYcCVmxE5u/o+moOSW5UvyVfNP06ypuIYv7PK9plH2Mp4Tmct8u2dVEP3HUyOdULn+E0yBfYisV5p3dSdnS/4=@vger.kernel.org X-Gm-Message-State: AOJu0Yw1hqNS1fc0Vvx3lq3yuYrJAhJEvVJnsyaT5dJU63l7gXKl4g45 6qgxifwzyQxnv0zbc/l5QPF/JOk3/HKN/4579Gln47qEyjfbn5+ta/zjbKoeKA== X-Google-Smtp-Source: AGHT+IFha9Fj/OXST1rmXZUQpjR/6jvkkRdPdpqAlTCawnloKZPpCJkNTYsOHYUG1EKOL7N+SHqhUg== X-Received: by 2002:a05:6808:13c3:b0:3e3:9f31:c8cc with SMTP id 5614622812f47-3e3b4181612mr4830531b6e.47.1727938917115; Thu, 03 Oct 2024 00:01:57 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:01:56 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 4/9] arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes Date: Thu, 3 Oct 2024 14:59:58 +0800 Message-ID: <20241003070139.1461472-5-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 719d2409a7db..49d4180595a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2183,6 +2183,64 @@ ccusys: clock-controller@17200000 { #clock-cells =3D <1>; }; =20 + video_decoder: video-decoder@18000000 { + compatible =3D "mediatek,mt8188-vcodec-dec"; + reg =3D <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges =3D <0 0 0 0x18000000 0 0x26000>; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + mediatek,scp =3D <&scp>; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x10000 0 0x800>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + larb23: smi@1800d000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1800d000 0 0x1000>; @@ -2234,6 +2292,31 @@ larb19: smi@1a010000 { mediatek,smi =3D <&vdo_smi_common>; }; =20 + video_encoder: video-encoder@1a020000 { + compatible =3D "mediatek,mt8188-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks =3D <&vencsys CLK_VENC1_VENC>; + clock-names =3D "venc_sel"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,scp =3D <&scp>; + }; + disp_dsi: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51337136328 for ; Thu, 3 Oct 2024 07:02:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938921; cv=none; b=jIaA+6QM5Wg2IXICQrZKsE5Oy6nJm9JHoQKNIQ3EpOTPVx4u27LmlD91UAK8Obe8IK1MU+7H748ayAziRti7Qx5Wh7VfQ71hCCBMa8YwDq76j9viTCx7VCsSIo6UBk32GzVGWdp1S8J3Wq+8Hzrcr55vt2ECE16/GU2TU3wPgC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938921; c=relaxed/simple; bh=BQd/K0GfhQ8esTLAa/m+wQzT5OPcp3nOxWz4nz8a98A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ag5+qYE78AdpH8/rvnwAGgjkQ5/4EfGLH7yRsYRvbBh/rFBJVtEyMkG8vt7VEXnJazXEBHOwWw2ZIiAw8Q1MZC2/4MycSuDiPoy1lC6Ip23OfJoxXDOLvLf3HIr8m4E4umLrIaRbcBo+dc6W/v+bnFAWtXHY8Ygi+480hHU37HI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=PBJ9IsPP; arc=none smtp.client-ip=209.85.210.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PBJ9IsPP" Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-718e2855479so510205b3a.1 for ; Thu, 03 Oct 2024 00:02:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938920; x=1728543720; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/d/o7lkyrEK7MdTXzGL48vZFksOeTQ6shmZULA6Dpk0=; b=PBJ9IsPP0cLyJCby0qJZuptJuJGYFUpRTnXZwInTFU4ZrFezrgdrHBvnce72smPuKY L7maUVOilyq8L0OtFEZtZM/5n9RG4Ip9nnQa+FYp1nRDezsgG6S/WEwVGIHpbV4+ov5w x5xR/mWF1BipQzLhi3ZiOjFmWpFEfjr2Nx9wg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938920; x=1728543720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/d/o7lkyrEK7MdTXzGL48vZFksOeTQ6shmZULA6Dpk0=; b=S/grNjqP1jAuTOo2DCdmMeMKkwbHvRf0xsyYVRgOxwJTyGpSuj6TiWWJArzq7d1qB1 kz47MYdLLl6F8xvS0vLbf2w3m0gWEEs8S7Md17FxP0fjFuGosSYRYgXRklRMvTEQVeo5 ekMspmb1r7LnKtTqEVQL2HT08nwsInuv2Bp964uJyrPAQkmGBT0Exq5caQDVcwdGI2zi O50PXLkW1iZNHFdwSno9RbeSTt0foZzMWeh2TEpVw4usTKgboiLlm1gK0hhf83dfWU2g btHESbC1frTTpKcayxvaT+ws+zQDZWuT0+ETnseLzMzU6i4c3a3Pt1XtotUgSGr/aJv7 s3HQ== X-Forwarded-Encrypted: i=1; AJvYcCWws0CGChnfkq6HW8LIJOQ2O+pY/3Svo6Cjl6pVaIfJCnOd5aOAymnJfi29boFrguoDdoyzkJWCGExYP0E=@vger.kernel.org X-Gm-Message-State: AOJu0YzPUeJXbiu34liioU1sFxRVbY5HrldwJA3x40M/VtScdjAFNLLf U1Xu/uHntzjTOyip+panCrq3WjQaSIrPR82PFhjFKQFXmBbrH8P8Y56LVIo50Q== X-Google-Smtp-Source: AGHT+IFh1+pRTF5QP2Z4S/FKW/7aJxh3DsNrBR5NMDBZX20D5QgF1Et4sk3LUOF99xcybVx+7A1zsw== X-Received: by 2002:a05:6a00:a14:b0:717:81b3:4c7a with SMTP id d2e1a72fcca58-71dc5d6e0dcmr9516899b3a.24.1727938919636; Thu, 03 Oct 2024 00:01:59 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:01:59 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 5/9] arm64: dts: mediatek: mt8188: Add JPEG decoder and encoder nodes Date: Thu, 3 Oct 2024 14:59:59 +0800 Message-ID: <20241003070139.1461472-6-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add JPEG encoder and decoder nodes for hardware-accelerated JPEG decoding and encoding support. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 49d4180595a9..0eb57f95bbaf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2317,6 +2317,35 @@ video_encoder: video-encoder@1a020000 { mediatek,scp =3D <&scp>; }; =20 + jpeg_encoder: jpeg-encoder@1a030000 { + compatible =3D "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; + reg =3D <0 0x1a030000 0 0x10000>; + clocks =3D <&vencsys CLK_VENC1_JPGENC>; + clock-names =3D "jpgenc"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, + <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, + <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, + <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VENC>; + }; + + jpeg_decoder: jpeg-decoder@1a040000 { + compatible =3D "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; + reg =3D <0 0x1a040000 0 0x10000>; + clocks =3D <&vencsys CLK_VENC1_LARB>, + <&vencsys CLK_VENC1_JPGDEC>; + clock-names =3D "jpgdec-smi", "jpgdec"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + disp_dsi: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E819E13A888 for ; Thu, 3 Oct 2024 07:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938924; cv=none; b=H7CCr3Ynwo3LdQe359PFW3RPfB2l3S1UxyRyPbUcv5vGDKTgTIlGrsFYebFCfdrd02Mwai5fJm0d0GbiGNGFi7V6hGkYp63nDn9KYnJae6tHoMXBup+5xRQEsirwiTMcCOn2yCYbYRYPJK92STZDHStgI/q4KnZP7h9z9ZQv1K8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938924; c=relaxed/simple; bh=Vr2xDeUGR7wn0IG1ujsn4pL0w26Sn9GhHyQQhGtQ1oY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k/RxUOh6+A9M6+ibKu0TIEuAchuIPrViGnuGVlnB684AlZGjuQ1gwoLfXp6Mw+TSiuJ8sb9MrBrlQf2FDNKB7S0h7O1qGnOi6yfxjq1n+QP3C3EMr8X5B8Kubw8sOOIruQZXmBF9R0a1nTTD0FJFalF1mku2NnIq994UKn57K7w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=FwNErA6N; arc=none smtp.client-ip=209.85.215.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="FwNErA6N" Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-7db4c1a54easo380099a12.1 for ; Thu, 03 Oct 2024 00:02:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938922; x=1728543722; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3DZWdl8216aZT8y3IXtxjhUrWkN3hJN2Yt08JxwRcJQ=; b=FwNErA6NehZaX0yN8a512PuCG7at+ZhXJVyYRYjDonRvNTUwjLrw0m/uM6P6ppTsvM wIagAQ4XdcKklVN6E1UmBn7ydlI1fzxfQzvKRPhkLzhzTMjqpu0w4faAvUClCgV40ASW vNmkmty8CqRsgNS8Lylg2LV63H9mcU6tGeQIU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938922; x=1728543722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3DZWdl8216aZT8y3IXtxjhUrWkN3hJN2Yt08JxwRcJQ=; b=YnSgWzoYyfkXtr5MwRycbz50y144BlpxVPLntZEm2ndRUSkGMOUCpUlDrOax43nZlO WJ84D8SAOfdTD9+2ZQ1TXa9Y90mWhWZEjPKmX9efhSB7TuOPOzkJxdYDc9yhVe+J+GQO 7ZTmSIqemF+OxoMqbJfzQMyzY0bnPVN2VoAocWLX2Pk8CcZ5zeesp9E6+ZGI7B+8kVEA hAEFNisZx/Km8UsvDrXZm4LEYAeRC2MomOpyP5O/8FeJOhybz0PWX900OGmNQIOhefCL d4WSjfpr1sxzShG7CBRgsk/mF/SxoolDTn9dUxe04BBGMr+pT+23Nf4Qy18iYIX5GViS XQqg== X-Forwarded-Encrypted: i=1; AJvYcCWgWJfNiq2GnbrO9IS2WL0dlTX4X4rAzwJlb4DQzX+3w8EvqbeqUppye2UU4Eu86TCBn6ioCMHqD8+MZPw=@vger.kernel.org X-Gm-Message-State: AOJu0YwM/j/1jzg4g1wSOvBk5rFO9mLHTmQI6ZVRF1VvkZ1NAx/JR9vb 0hSuf4LRkQLvtTJO7EwmRsgfK9wxC68PvtrOeLNirK3UaCwqiaUzTOusHetl2A== X-Google-Smtp-Source: AGHT+IE2SFaqb1OLYR+xEq8sUkTQwvxY9SfiKLM3jT+7mDigbRjSypSLlCdkbSzQtSVqhSe3ATAMiQ== X-Received: by 2002:a05:6a20:c886:b0:1cf:2862:beca with SMTP id adf61e73a8af0-1d5db136c5amr8275656637.13.1727938922335; Thu, 03 Oct 2024 00:02:02 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:02:01 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 6/9] arm64: dts: mediatek: mt8188: Add display nodes for vdosys0 Date: Thu, 3 Oct 2024 15:00:00 +0800 Message-ID: <20241003070139.1461472-7-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdosys0 display nodes to support the internal display pipeline. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 0eb57f95bbaf..c4026de18fd8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ / { aliases { gce0 =3D &gce0; gce1 =3D &gce1; + mutex0 =3D &mutex0; }; =20 cpus { @@ -2346,6 +2347,71 @@ jpeg_decoder: jpeg-decoder@1a040000 { power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; }; =20 + ovl0: ovl@1c000000 { + compatible =3D "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg =3D <0 0x1c000000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible =3D "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg =3D <0 0x1c002000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible =3D "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x1c003000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_COLOR0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible =3D "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccor= r"; + reg =3D <0 0x1c004000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_CCORR0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible =3D "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1c005000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_AAL0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible =3D "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamm= a"; + reg =3D <0 0x1c006000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible =3D "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x1c007000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_DITHER0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + disp_dsi: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; @@ -2361,6 +2427,26 @@ disp_dsi: dsi@1c008000 { status =3D "disabled"; }; =20 + mutex0: mutex@1c016000 { + compatible =3D "mediatek,mt8188-disp-mutex"; + reg =3D <0 0x1c016000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; + mediatek,gce-events =3D ; + }; + + postmask0: postmask@1c01a000 { + compatible =3D "mediatek,mt8188-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1c01a000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + }; + vdosys0: syscon@1c01d000 { compatible =3D "mediatek,mt8188-vdosys0", "syscon"; reg =3D <0 0x1c01d000 0 0x1000>; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C200713BAE7 for ; Thu, 3 Oct 2024 07:02:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938927; cv=none; b=KnudTRi2ssYQEkztZByXwm4+Bnt0jVeSXibcVf+y5quV9VxNydcGXg7bn4YiGDLGtwj2r5/yplIU2AAzj07cI/MxdmtxfzBQdQoej7fa4jOu1+QrJtjICzX9zM+OPS+vD24sbfF6GdZn8YHv5LCbkpftKH+5Sm0ybrUAW2v/WOY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938927; c=relaxed/simple; bh=kFd2zFR3PLHQUi9t7qCCRxG8mWOlDzI5jQoMX6E/bHA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b0l1EOk03rEMo+eSzBsKnhvPGohBtDDR+TiOOKa3gSI9OIkuoYUf0h/GgqRilUYJqMzCl+fpV+/qsBGdNLocm2BuyxWS4eqWQB3goViYvzzaBfwMVBnfkBsuLDsFm3iVesQsyz53AwqKfaInjnSdY3FMzcAgUSvaA8p2AuKvJ/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=PKeDJwUw; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="PKeDJwUw" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-71b00a97734so620574b3a.1 for ; Thu, 03 Oct 2024 00:02:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938925; x=1728543725; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4k2o/I2+UBi0xubeN2RcTfc2l9sMDWMvwW6OmAATdeU=; b=PKeDJwUwEnOiPVKl+f1jqhqVzqUAiONyhsKJ/EEXFQmgr2Ug7nxrrslnk9ni1QIq6G G7PwXiuzkVAc4tvZ2Qvcl6Ew3+GDv5wB36xvzu8AmL6HBWQQsZwR2pyTWKkjKqg1Nn/E MRNkYhBo5MgeW48HsoC0W+mR6tdgfEjq5jR2A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938925; x=1728543725; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4k2o/I2+UBi0xubeN2RcTfc2l9sMDWMvwW6OmAATdeU=; b=PAhVne3I+8D8EONxhSKAJ8Jz3U34l7IsPJ7bpqpPTHoGBpTkd+hvu/72/WTaeJV9kY T+m7uH+QJRrA2OrOolu8QgoF5rnQxpVnGzRFlqTVWwZiMdd00SSjqt8SH6Or/SoLIQ9t Ikno74hMffzMDoRqOg6R2jpvSUmFa4SzuPJw46g27qKbzgeTlTsbSBM4XqqLfLIUZ/EJ TiIQXhYdjG1Uym08PQaTdavvCk12CAvLiyyVWkT7kXPN3INs1cIIrlRU/sIPOU7cFaKS TGpgm1ffEKAkU5eif5hxGVsG4Y3nu5IM6x7E1UyalAyT1iGgGyMNOvR3DHRvv3w3nNLA 7yow== X-Forwarded-Encrypted: i=1; AJvYcCX8e5rg4Z2/RFMTHbaprrIlObhTKixBUEBX6cW7KMZBFi27bAYPWxwRIIdKMa8l5w9eG5YOFYc2YFoCUu0=@vger.kernel.org X-Gm-Message-State: AOJu0YyuLh6l0ENkbd2xkl89NvYDp6JmT8x6+tOoogAcE1pXbdmHnoxS SXlocpkvPTSKd7lr/umgsvatb+LkDmcWw2lhItB4ckwihDbJGdCFae74AP7BTQ== X-Google-Smtp-Source: AGHT+IEEV+Twz/qRb0YWbMBXSzMpp2pPI6Y9wOqdXQYwZTiPE3gnTEKFIyoXDi3D3wWX8a/nRu+Lfw== X-Received: by 2002:a05:6a00:2d94:b0:714:1f6d:11e5 with SMTP id d2e1a72fcca58-71dc5c67665mr9381827b3a.12.1727938924901; Thu, 03 Oct 2024 00:02:04 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:02:04 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 7/9] arm64: dts: mediatek: mt8188: Add display nodes for vdosys1 Date: Thu, 3 Oct 2024 15:00:01 +0800 Message-ID: <20241003070139.1461472-8-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdosys1 display nodes to support the external display pipeline. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 298 +++++++++++++++++++++++ 1 file changed, 298 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index c4026de18fd8..541eaed59e8b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -24,9 +24,32 @@ / { #size-cells =3D <2>; =20 aliases { + ethdr0 =3D ðdr0; gce0 =3D &gce0; gce1 =3D &gce1; + merge0 =3D &merge0; + merge1 =3D &merge1; + merge2 =3D &merge2; + merge3 =3D &merge3; + merge4 =3D &merge4; mutex0 =3D &mutex0; + mutex1 =3D &mutex1; + padding0 =3D &padding0; + padding1 =3D &padding1; + padding2 =3D &padding2; + padding3 =3D &padding3; + padding4 =3D &padding4; + padding5 =3D &padding5; + padding6 =3D &padding6; + padding7 =3D &padding7; + vdo1-rdma0 =3D &vdo1_rdma0; + vdo1-rdma1 =3D &vdo1_rdma1; + vdo1-rdma2 =3D &vdo1_rdma2; + vdo1-rdma3 =3D &vdo1_rdma3; + vdo1-rdma4 =3D &vdo1_rdma4; + vdo1-rdma5 =3D &vdo1_rdma5; + vdo1-rdma6 =3D &vdo1_rdma6; + vdo1-rdma7 =3D &vdo1_rdma7; }; =20 cpus { @@ -2507,6 +2530,16 @@ vdosys1: syscon@1c100000 { mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0 0x1000>; }; =20 + mutex1: mutex@1c101000 { + compatible =3D "mediatek,mt8188-disp-mutex"; + reg =3D <0 0x1c101000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_DISP_MUTEX>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; + mediatek,gce-events =3D ; + }; + larb2: smi@1c102000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1c102000 0 0x1000>; @@ -2528,5 +2561,270 @@ larb3: smi@1c103000 { mediatek,larb-id =3D ; mediatek,smi =3D <&vpp_smi_common>; }; + + vdo1_rdma0: rdma@1c104000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c104000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: rdma@1c105000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c105000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA1>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: rdma@1c106000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c106000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA2>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: rdma@1c107000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c107000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA3>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: rdma@1c108000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c108000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA4>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: rdma@1c109000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c109000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA5>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: rdma@1c10a000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c10a000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA6>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: rdma@1c10b000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c10b000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA7>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge0: merge@1c10c000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10c000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute; + }; + + merge1: merge@1c10d000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute; + }; + + merge2: merge@1c10e000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10e000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute; + }; + + merge3: merge@1c10f000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10f000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute; + }; + + merge4: merge@1c110000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c110000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en; + }; + + ethdr0: ethdr@1c114000 { + compatible =3D "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethd= r"; + reg =3D <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names =3D "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + + clocks =3D <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names =3D "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; + + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, + <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; + + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + }; + + padding0: padding@1c11d000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + + padding1: padding@1c11e000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11e000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; + }; + + padding2: padding@1c11f000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11f000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING2>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; + }; + + padding3: padding@1c120000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c120000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING3>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; + }; + + padding4: padding@1c121000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c121000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING4>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; + }; + + padding5: padding@1c122000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c122000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING5>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; + }; + + padding6: padding@1c123000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c123000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING6>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; + }; + + padding7: padding@1c124000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c124000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING7>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; + }; }; }; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 187AD13CF8E for ; Thu, 3 Oct 2024 07:02:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938929; cv=none; b=PMoCBk9WCvGMe+XAKlJtmhFOpHWI4S0mfEynVQPIkBMZ3LTiID5gp/AuXdMqQsRSY8qc/VnTgVL5I1HrBhWk0Af/LuwUaIjoNe0Yi3NpwUuF5zuxBB9tzWy3qbWVSs4sgCnGCRcERpsyCVHptETISnIbfTuVLEhi56i/YZchAVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938929; c=relaxed/simple; bh=hor02EnulX+vfYWXpRnGhzDiHxLZPjFZgTKDfIosOno=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sah2NkdhrOg6VdzU7b7oDBAiAtZh2D8Lo5bPulCUNnH99LkMB8E/iv9pAzVfKZFcseIFEzJytDjmkqNIkSw6PlSc5aZPfiiBoZhfmJ7icYOoc30kZoT0l4JicCSGsmu1Ucr1oSywY+DPYiBZXzPa5Z2STHjxWOEOrtiHIs0t24c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=Bp6TtwPt; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="Bp6TtwPt" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-7179069d029so488741b3a.2 for ; Thu, 03 Oct 2024 00:02:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938927; x=1728543727; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4SF5nwE8q+scLV0tbzUby7efs2QPmWoOdROYf5aDp40=; b=Bp6TtwPtXxp8kSpPEisbm3/sighWEwvEVjA7m16YGEb3aocwiHEjiNEsOAYXg7ocMR SRQqixYgV4fML3dJUY38lEkIrh6C7wuFlSCAeQWQALsyUADyBnIi7NPgfXP7vqOpcEo1 P1nRWw4odWUYigvY2txpmJz0TWSrP8JUvftsc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938927; x=1728543727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4SF5nwE8q+scLV0tbzUby7efs2QPmWoOdROYf5aDp40=; b=pLc70L2v2YE/Ha+M0Pkd0ADEzfiSwvZZpt1w9jr6Qyp55pjQsquTOEAVBTwnVJQrYO JyCLlqGUncasPuk/589s2xMFdh7ul2wixXEdAiv8F2Oc15IYflFZYVLeres8I8TLelXi fFEeR71W5hWHbDtu3WBnGMDbqS8jMhdrhnGSbTqF8A40OfzxxrkAwFWFaSHBIsoOVILH 8OEo09UNWBWaFtbe3VtDKlX2k/piUSYmhXA0h/KylzSNStiCIDXqTr/T6OXZELB5gVXJ AfHbIiVaPdfbDbugj4kGiyIgMzTlXAEkJS7+wP+6yVKXTkjnRa7sjdgQRJ+jaaXfoZy7 CG3A== X-Forwarded-Encrypted: i=1; AJvYcCXEH6H8GhgpNs1NWsMAhkWxC2PxlSAF2vNJR1mUfUb1dbVJLvHdC416GEdnq/oy7yLVAv5RPF+BFxcLnqs=@vger.kernel.org X-Gm-Message-State: AOJu0YxLf31JGW5dwLM/4ICbpfb+8yH5Fp23zoa13qy47YeshXyU7HpB f80RQfahVaMYYL7/TU6mDkhCZw7TkogZz0nHnBe0OUO6ZBK50uciMkkOCdWAig== X-Google-Smtp-Source: AGHT+IG4DLzVoYDK294Ku6Vjd08TVjHsUCzPROxKoUjkMR0faA4MYffuLo4qVtm78hvUVl9MUuy5bw== X-Received: by 2002:a05:6a00:23c6:b0:714:1a74:9953 with SMTP id d2e1a72fcca58-71dc5c9bc6fmr9630693b3a.16.1727938927450; Thu, 03 Oct 2024 00:02:07 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:02:07 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 8/9] arm64: dts: mediatek: mt8188: Add DP-INTF nodes Date: Thu, 3 Oct 2024 15:00:02 +0800 Message-ID: <20241003070139.1461472-9-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the primary and secondary dp-intf nodes. These DP-INTF hardware IPs are the sink of the vdosys0 and vdosys1 display pipelines for the internal and external displays, respectively. Individual board device tree should enable the nodes and connect input and output ports as needed. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 541eaed59e8b..e77bd2b76128 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -24,6 +24,8 @@ / { #size-cells =3D <2>; =20 aliases { + dp-intf0 =3D &dp_intf0; + dp-intf1 =3D &dp_intf1; ethdr0 =3D ðdr0; gce0 =3D &gce0; gce1 =3D &gce1; @@ -2450,6 +2452,18 @@ disp_dsi: dsi@1c008000 { status =3D "disabled"; }; =20 + dp_intf0: dp-intf@1c015000 { + compatible =3D "mediatek,mt8188-dp-intf"; + reg =3D <0 0x1c015000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&vdosys0 CLK_VDO0_DP_INTF0>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + status =3D "disabled"; + }; + mutex0: mutex@1c016000 { compatible =3D "mediatek,mt8188-disp-mutex"; reg =3D <0 0x1c016000 0 0x1000>; @@ -2715,6 +2729,18 @@ merge4: merge@1c110000 { mediatek,merge-fifo-en; }; =20 + dp_intf1: dp-intf@1c113000 { + compatible =3D "mediatek,mt8188-dp-intf"; + reg =3D <0 0x1c113000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_DPINTF>, + <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + status =3D "disabled"; + }; + ethdr0: ethdr@1c114000 { compatible =3D "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethd= r"; reg =3D <0 0x1c114000 0 0x1000>, --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 06:28:21 2024 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA12713F42A for ; Thu, 3 Oct 2024 07:02:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938932; cv=none; b=RpYID4D1NQKUCXCya4ZQFI0lMNIY4Pg+cZJlhmcnhyrmDWY0222yhUcBwSG41cQMYT3w/lCO3I2JnwHjSv3pmoBBhekenXka/eh12x+bK0kU2DEOL/1jDGwOfSL3mQDjMupqq7F46MbJn6iIIcRru4yWZLwkzwhYGbxEFJSx3G8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727938932; c=relaxed/simple; bh=Ye0siwcOaJvlxvSr6UbPhEw7tWXLtn2oIKJeHRX1aEQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GvCtAlrHZDld3T4Y4VUKPrdXSqlCOBHiSzRIFPm8CmNC+4cqzAespVYdU9dF9+ihYUn15itqKZX5ZcP+GaD8voLoXZc6f+yERDIEXtPkWZ/t8+vJxjw29OseJ09ixAv7dfEFM1bIueq2uWq6O/sHYclwIN9uUK8RnIKs53B3rGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=QJOCxWrd; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="QJOCxWrd" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-71c702b2d50so488640b3a.1 for ; Thu, 03 Oct 2024 00:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727938930; x=1728543730; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ftwFn9ZLUuKCLPPu13/3mAe7bDdVNGDECC9c6Eq3ZPM=; b=QJOCxWrdlq+lXIyC/qCmK8BTMum4ITnBt9IUYTDXmpPA05bIXvqTarjFENbUfa88ni gWbbEaqEvVWJYO7p7U1EbUvFZGZvcOqPm97XmOTfTAneCFvKPDBrl0bwBU6D8hpDfaa+ e0InDBNGCY4gFAq/1Yv7DgjOeEukZw+N7V9xg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727938930; x=1728543730; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ftwFn9ZLUuKCLPPu13/3mAe7bDdVNGDECC9c6Eq3ZPM=; b=mvMQyG7ZgVeMzQN00yaRzV5Q7TFEdAclvLf1BF3NqKzsD+djslDShRptLyVWpswVPG 803zeRK4SqbN4YnIjJpHdwpNTEinrWoOmTo08zPWbl2ZH06zJ1XRxwXf+jiKCZAZ4G/0 ZS2pa0hglrJBcYe20GdDmV/JxyrZMSQ4mWIrVfMNR5AK2QVnfHrT8/3WtfQmDG4e1t6a 6Y8Y+pzejM/wVVBuSFf3KzLrMx9bsJrMHWM+ddw/RvO/WihE845I7tOnu45ikML/0rtq UjjTwZFETkdFFOucupaczwQXcJpHJ9OW3QdHSh/ZJTHAYJ+YeqgLcMOI/pkSZhUy7v7k dWKQ== X-Forwarded-Encrypted: i=1; AJvYcCW3ZY4q5D6RlZzRYo50anFU4S7YWvZ8QM/q3vPCOnzysQV6jhKsLyZoX4QfIwruHtmuaZiK6Fti9dzluK8=@vger.kernel.org X-Gm-Message-State: AOJu0Yyi+JlHVD5NcyrzzJehbnqE1SPV0dMvcJ6erTiKaE/J8aSn4jO8 priMkvuVCjZZSRPGunNLEMNIKKHFT+0itxovAvCNIgvKZBt+yJ4dNZEwK6+ARQ== X-Google-Smtp-Source: AGHT+IHE/CCPGFNgWjWh9e6CyqMHQZblij2trHaQLpVyyZLVEj0BO/xQcou38wPPpQh6mNnsYlGS5A== X-Received: by 2002:a05:6a00:1829:b0:714:1a7c:b727 with SMTP id d2e1a72fcca58-71dc5c772bbmr9315186b3a.8.1727938930039; Thu, 03 Oct 2024 00:02:10 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dd9d8e473sm633782b3a.81.2024.10.03.00.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 00:02:09 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 9/9] arm64: dts: mediatek: mt8188: Add eDP and DP TX nodes Date: Thu, 3 Oct 2024 15:00:03 +0800 Message-ID: <20241003070139.1461472-10-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241003070139.1461472-1-fshao@chromium.org> References: <20241003070139.1461472-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add edp-tx and dp-tx nodes for the Embedded DisplayPort (eDP) and DisplayPort ports to connect to DP-INTF ports and panels, and add the efuse cell for the DP calibration data. Individual board device tree should enable the nodes and connect input and output ports as needed. Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index e77bd2b76128..92e71977c775 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2006,6 +2006,10 @@ efuse: efuse@11f20000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + dp_calib_data: dp-calib@1a0 { + reg =3D <0x1a0 0xc>; + }; + lvts_efuse_data1: lvts1-calib@1ac { reg =3D <0x1ac 0x40>; }; @@ -2852,5 +2856,27 @@ padding7: padding@1c124000 { power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; + + edp_tx: edp-tx@1c500000 { + compatible =3D "mediatek,mt8188-edp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + interrupts =3D ; + nvmem-cells =3D <&dp_calib_data>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8188_POWER_DOMAIN_EDP_TX>; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible =3D "mediatek,mt8188-dp-tx"; + reg =3D <0 0x1c600000 0 0x8000>; + interrupts =3D ; + nvmem-cells =3D <&dp_calib_data>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8188_POWER_DOMAIN_DP_TX>; + max-linkrate-mhz =3D <5400>; + status =3D "disabled"; + }; }; }; --=20 2.46.1.824.gd892dcdcdd-goog