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[79.54.25.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d116asm1703735f8f.90.2024.10.03.10.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 10:30:28 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Thu, 03 Oct 2024 19:28:58 +0200 Subject: [PATCH v4 01/11] iio: dac: adi-axi-dac: update register names Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-1-ceb157487329@baylibre.com> References: <20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-0-ceb157487329@baylibre.com> In-Reply-To: <20241003-wip-bl-ad3552r-axi-v0-iio-testing-v4-0-ceb157487329@baylibre.com> To: Lars-Peter Clausen , Michael Hennerich , Nuno Sa , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mihail Chindris , Olivier Moysan Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Cameron , devicetree@vger.kernel.org, dlechner@baylibre.com, Mark Brown , Angelo Dureghello X-Mailer: b4 0.14.1 From: Angelo Dureghello Non functional, readability change. Update register names so that register bitfields can be more easily linked to the register name. Signed-off-by: Angelo Dureghello --- drivers/iio/dac/adi-axi-dac.c | 137 +++++++++++++++++++++++---------------= ---- 1 file changed, 74 insertions(+), 63 deletions(-) diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c index 0cb00f3bec04..e83f70465b46 100644 --- a/drivers/iio/dac/adi-axi-dac.c +++ b/drivers/iio/dac/adi-axi-dac.c @@ -35,35 +35,37 @@ */ =20 /* Base controls */ -#define AXI_DAC_REG_CONFIG 0x0c -#define AXI_DDS_DISABLE BIT(6) +#define AXI_DAC_CONFIG_REG 0x0c +#define AXI_DAC_CONFIG_DDS_DISABLE BIT(6) =20 /* DAC controls */ -#define AXI_DAC_REG_RSTN 0x0040 -#define AXI_DAC_RSTN_CE_N BIT(2) -#define AXI_DAC_RSTN_MMCM_RSTN BIT(1) -#define AXI_DAC_RSTN_RSTN BIT(0) -#define AXI_DAC_REG_CNTRL_1 0x0044 -#define AXI_DAC_SYNC BIT(0) -#define AXI_DAC_REG_CNTRL_2 0x0048 -#define ADI_DAC_R1_MODE BIT(4) -#define AXI_DAC_DRP_STATUS 0x0074 -#define AXI_DAC_DRP_LOCKED BIT(17) +#define AXI_DAC_RSTN_REG 0x0040 +#define AXI_DAC_RSTN_CE_N BIT(2) +#define AXI_DAC_RSTN_MMCM_RSTN BIT(1) +#define AXI_DAC_RSTN_RSTN BIT(0) +#define AXI_DAC_CNTRL_1_REG 0x0044 +#define AXI_DAC_CNTRL_1_SYNC BIT(0) +#define AXI_DAC_CNTRL_2_REG 0x0048 +#define ADI_DAC_CNTRL_2_R1_MODE BIT(4) +#define AXI_DAC_DRP_STATUS_REG 0x0074 +#define AXI_DAC_DRP_STATUS_DRP_LOCKED BIT(17) + /* DAC Channel controls */ -#define AXI_DAC_REG_CHAN_CNTRL_1(c) (0x0400 + (c) * 0x40) -#define AXI_DAC_REG_CHAN_CNTRL_3(c) (0x0408 + (c) * 0x40) -#define AXI_DAC_SCALE_SIGN BIT(15) -#define AXI_DAC_SCALE_INT BIT(14) -#define AXI_DAC_SCALE GENMASK(14, 0) -#define AXI_DAC_REG_CHAN_CNTRL_2(c) (0x0404 + (c) * 0x40) -#define AXI_DAC_REG_CHAN_CNTRL_4(c) (0x040c + (c) * 0x40) -#define AXI_DAC_PHASE GENMASK(31, 16) -#define AXI_DAC_FREQUENCY GENMASK(15, 0) -#define AXI_DAC_REG_CHAN_CNTRL_7(c) (0x0418 + (c) * 0x40) -#define AXI_DAC_DATA_SEL GENMASK(3, 0) +#define AXI_DAC_CHAN_CNTRL_1_REG(c) (0x0400 + (c) * 0x40) +#define AXI_DAC_CHAN_CNTRL_3_REG(c) (0x0408 + (c) * 0x40) +#define AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN BIT(15) +#define AXI_DAC_CHAN_CNTRL_3_SCALE_INT BIT(14) +#define AXI_DAC_CHAN_CNTRL_3_SCALE GENMASK(14, 0) +#define AXI_DAC_CHAN_CNTRL_2_REG(c) (0x0404 + (c) * 0x40) +#define AXI_DAC_CHAN_CNTRL_2_PHASE GENMASK(31, 16) +#define AXI_DAC_CHAN_CNTRL_2_FREQUENCY GENMASK(15, 0) +#define AXI_DAC_CHAN_CNTRL_4_REG(c) (0x040c + (c) * 0x40) +#define AXI_DAC_CHAN_CNTRL_7_REG(c) (0x0418 + (c) * 0x40) +#define AXI_DAC_CHAN_CNTRL_7_DATA_SEL GENMASK(3, 0) =20 /* 360 degrees in rad */ -#define AXI_DAC_2_PI_MEGA 6283190 +#define AXI_DAC_2_PI_MEGA 6283190 + enum { AXI_DAC_DATA_INTERNAL_TONE, AXI_DAC_DATA_DMA =3D 2, @@ -89,7 +91,7 @@ static int axi_dac_enable(struct iio_backend *back) int ret; =20 guard(mutex)(&st->lock); - ret =3D regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN, + ret =3D regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, AXI_DAC_RSTN_MMCM_RSTN); if (ret) return ret; @@ -98,12 +100,14 @@ static int axi_dac_enable(struct iio_backend *back) * designs really use it but if they don't we still get the lock bit * set. So let's do it all the time so the code is generic. */ - ret =3D regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS, __val, - __val & AXI_DAC_DRP_LOCKED, 100, 1000); + ret =3D regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG, + __val, + __val & AXI_DAC_DRP_STATUS_DRP_LOCKED, + 100, 1000); if (ret) return ret; =20 - return regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN, + return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG, AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN); } =20 @@ -112,7 +116,7 @@ static void axi_dac_disable(struct iio_backend *back) struct axi_dac_state *st =3D iio_backend_get_priv(back); =20 guard(mutex)(&st->lock); - regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0); + regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); } =20 static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back, @@ -155,15 +159,15 @@ static int __axi_dac_frequency_get(struct axi_dac_sta= te *st, unsigned int chan, } =20 if (tone_2) - reg =3D AXI_DAC_REG_CHAN_CNTRL_4(chan); + reg =3D AXI_DAC_CHAN_CNTRL_4_REG(chan); else - reg =3D AXI_DAC_REG_CHAN_CNTRL_2(chan); + reg =3D AXI_DAC_CHAN_CNTRL_2_REG(chan); =20 ret =3D regmap_read(st->regmap, reg, &raw); if (ret) return ret; =20 - raw =3D FIELD_GET(AXI_DAC_FREQUENCY, raw); + raw =3D FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); *freq =3D DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16)); =20 return 0; @@ -194,17 +198,18 @@ static int axi_dac_scale_get(struct axi_dac_state *st, u32 reg, raw; =20 if (tone_2) - reg =3D AXI_DAC_REG_CHAN_CNTRL_3(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); else - reg =3D AXI_DAC_REG_CHAN_CNTRL_1(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); =20 ret =3D regmap_read(st->regmap, reg, &raw); if (ret) return ret; =20 - sign =3D FIELD_GET(AXI_DAC_SCALE_SIGN, raw); - raw =3D FIELD_GET(AXI_DAC_SCALE, raw); - scale =3D DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, AXI_DAC_SCALE_INT); + sign =3D FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw); + raw =3D FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw); + scale =3D DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA, + AXI_DAC_CHAN_CNTRL_3_SCALE_INT); =20 vals[0] =3D scale / MEGA; vals[1] =3D scale % MEGA; @@ -227,15 +232,15 @@ static int axi_dac_phase_get(struct axi_dac_state *st, int ret, vals[2]; =20 if (tone_2) - reg =3D AXI_DAC_REG_CHAN_CNTRL_4(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); else - reg =3D AXI_DAC_REG_CHAN_CNTRL_2(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); =20 ret =3D regmap_read(st->regmap, reg, &raw); if (ret) return ret; =20 - raw =3D FIELD_GET(AXI_DAC_PHASE, raw); + raw =3D FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw); phase =3D DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX); =20 vals[0] =3D phase / MEGA; @@ -260,18 +265,20 @@ static int __axi_dac_frequency_set(struct axi_dac_sta= te *st, unsigned int chan, } =20 if (tone_2) - reg =3D AXI_DAC_REG_CHAN_CNTRL_4(chan); + reg =3D AXI_DAC_CHAN_CNTRL_4_REG(chan); else - reg =3D AXI_DAC_REG_CHAN_CNTRL_2(chan); + reg =3D AXI_DAC_CHAN_CNTRL_2_REG(chan); =20 raw =3D DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate); =20 - ret =3D regmap_update_bits(st->regmap, reg, AXI_DAC_FREQUENCY, raw); + ret =3D regmap_update_bits(st->regmap, reg, + AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw); if (ret) return ret; =20 /* synchronize channels */ - return regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC); + return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, + AXI_DAC_CNTRL_1_SYNC); } =20 static int axi_dac_frequency_set(struct axi_dac_state *st, @@ -312,16 +319,16 @@ static int axi_dac_scale_set(struct axi_dac_state *st, =20 /* format is 1.1.14 (sign, integer and fractional bits) */ if (scale < 0) { - raw =3D FIELD_PREP(AXI_DAC_SCALE_SIGN, 1); + raw =3D FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1); scale *=3D -1; } =20 - raw |=3D div_u64((u64)scale * AXI_DAC_SCALE_INT, MEGA); + raw |=3D div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA); =20 if (tone_2) - reg =3D AXI_DAC_REG_CHAN_CNTRL_3(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_3_REG(chan->channel); else - reg =3D AXI_DAC_REG_CHAN_CNTRL_1(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_1_REG(chan->channel); =20 guard(mutex)(&st->lock); ret =3D regmap_write(st->regmap, reg, raw); @@ -329,7 +336,8 @@ static int axi_dac_scale_set(struct axi_dac_state *st, return ret; =20 /* synchronize channels */ - ret =3D regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC); + ret =3D regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, + AXI_DAC_CNTRL_1_SYNC); if (ret) return ret; =20 @@ -355,18 +363,19 @@ static int axi_dac_phase_set(struct axi_dac_state *st, raw =3D DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA); =20 if (tone_2) - reg =3D AXI_DAC_REG_CHAN_CNTRL_4(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_4_REG(chan->channel); else - reg =3D AXI_DAC_REG_CHAN_CNTRL_2(chan->channel); + reg =3D AXI_DAC_CHAN_CNTRL_2_REG(chan->channel); =20 guard(mutex)(&st->lock); - ret =3D regmap_update_bits(st->regmap, reg, AXI_DAC_PHASE, - FIELD_PREP(AXI_DAC_PHASE, raw)); + ret =3D regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE, + FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw)); if (ret) return ret; =20 /* synchronize channels */ - ret =3D regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_1, AXI_DAC_SYNC); + ret =3D regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG, + AXI_DAC_CNTRL_1_SYNC); if (ret) return ret; =20 @@ -437,7 +446,7 @@ static int axi_dac_extend_chan(struct iio_backend *back, =20 if (chan->type !=3D IIO_ALTVOLTAGE) return -EINVAL; - if (st->reg_config & AXI_DDS_DISABLE) + if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) /* nothing to extend */ return 0; =20 @@ -454,13 +463,14 @@ static int axi_dac_data_source_set(struct iio_backend= *back, unsigned int chan, switch (data) { case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE: return regmap_update_bits(st->regmap, - AXI_DAC_REG_CHAN_CNTRL_7(chan), - AXI_DAC_DATA_SEL, + AXI_DAC_CHAN_CNTRL_7_REG(chan), + AXI_DAC_CHAN_CNTRL_7_DATA_SEL, AXI_DAC_DATA_INTERNAL_TONE); case IIO_BACKEND_EXTERNAL: return regmap_update_bits(st->regmap, - AXI_DAC_REG_CHAN_CNTRL_7(chan), - AXI_DAC_DATA_SEL, AXI_DAC_DATA_DMA); + AXI_DAC_CHAN_CNTRL_7_REG(chan), + AXI_DAC_CHAN_CNTRL_7_DATA_SEL, + AXI_DAC_DATA_DMA); default: return -EINVAL; } @@ -475,7 +485,7 @@ static int axi_dac_set_sample_rate(struct iio_backend *= back, unsigned int chan, =20 if (!sample_rate) return -EINVAL; - if (st->reg_config & AXI_DDS_DISABLE) + if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE) /* sample_rate has no meaning if DDS is disabled */ return 0; =20 @@ -580,7 +590,7 @@ static int axi_dac_probe(struct platform_device *pdev) * Force disable the core. Up to the frontend to enable us. And we can * still read/write registers... */ - ret =3D regmap_write(st->regmap, AXI_DAC_REG_RSTN, 0); + ret =3D regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0); if (ret) return ret; =20 @@ -601,7 +611,7 @@ static int axi_dac_probe(struct platform_device *pdev) } =20 /* Let's get the core read only configuration */ - ret =3D regmap_read(st->regmap, AXI_DAC_REG_CONFIG, &st->reg_config); + ret =3D regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config); if (ret) return ret; =20 @@ -613,7 +623,8 @@ static int axi_dac_probe(struct platform_device *pdev) * want independent channels let's override the core's default value and * set the R1_MODE bit. */ - ret =3D regmap_set_bits(st->regmap, AXI_DAC_REG_CNTRL_2, ADI_DAC_R1_MODE); + ret =3D regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG, + ADI_DAC_CNTRL_2_R1_MODE); if (ret) return ret; =20 --=20 2.45.0.rc1