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[79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:12:58 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:50 +0200 Subject: [PATCH v8 01/12] drm/msm: Fix bv_fence being used as bv_rptr Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-1-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=1862; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=a7i9oji+Kb0tTlTXnErd/GxgUbRIJJuFO80e+whAz5c=; b=dFWbauOYlLyo1yIzbd6BN2HyYlM/JboGwxDZJeazXddSBkCqLThvPU4p1EwM1NUDIMPvVoTqE tfS/mBscX7hDVM6S57Z4XDeSbWutmxY8ic8c851HnaJ6DNaPohkCR14 X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= The bv_fence field of rbmemptrs was being used incorrectly as the BV rptr shadow pointer in some places. Add a bv_rptr field and change the code to use that instead. Reviewed-by: Akhil P Oommen Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index bcaec86ac67a5c90544922372cd46fbdd8cf359e..32a4faa93d7f072ea6b8d949f4d= c9d2a58cec6b9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1132,7 +1132,7 @@ static int hw_init(struct msm_gpu *gpu) /* ..which means "always" on A7xx, also for BV shadow */ if (adreno_is_a7xx(adreno_gpu)) { gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR, - rbmemptr(gpu->rb[0], bv_fence)); + rbmemptr(gpu->rb[0], bv_rptr)); } =20 /* Always come up on rb 0 */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm= _ringbuffer.h index 0d6beb8cd39a7b297e73741d2018915246a710d4..40791b2ade46ef0e16e2a408829= 1a575d3be9e82 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t rptr; volatile uint32_t fence; /* Introduced on A7xx */ + volatile uint32_t bv_rptr; volatile uint32_t bv_fence; =20 volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; --=20 2.46.1 From nobody Thu Nov 28 05:32:21 2024 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D1FE1A707B; Thu, 3 Oct 2024 16:13:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971984; cv=none; b=ZZoI5qupyleCsLCDPnW9yWCz1F3zIuHZ8gjnWorbblmmlC4HZtm1aoCIeD7PHi+QT7tn86dkfwJAKKn6940mg2fHJpSB1K0k94dWrKTm6zTrghFdNO78GZoWx5laMiEeKM7ltASc0ayZ06BebtqPJd3yAy0/r85Xm77Z6JoCaUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971984; c=relaxed/simple; bh=yIHp38RtvtLDCz+dKB6Vf596mZ26ig0Y5efzj1HIfzs=; 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[79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:13:00 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:51 +0200 Subject: [PATCH v8 02/12] drm/msm/a6xx: Track current_ctx_seqno per ring Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-2-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=8467; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=yIHp38RtvtLDCz+dKB6Vf596mZ26ig0Y5efzj1HIfzs=; b=4meiphr9KoscMKIvQ+6FRrwp0DsCf5Bwac0kh9dYNWa+hxu9vhNR25CqTEnkzHvDcEkFZwfdN pyCBNbyrXMpD7rW77J7T0YL3a7xlnPgDjcCBmN4kbzVA7PfsbqfD+lz X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= With preemption it is not enough to track the current_ctx_seqno globally as execution might switch between rings. This is especially problematic when current_ctx_seqno is used to determine whether a page table switch is necessary as it might lead to security bugs. Track current context per ring. Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 +++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++---- drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 11 ----------- drivers/gpu/drm/msm/msm_ringbuffer.h | 10 ++++++++++ 8 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a2xx_gpu.c index 0dc255ddf5ceba87090f64d5cb9f078b61104063..379a3d346c300f3ccc9e9bd08ef= 2a32aa3e24ceb 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -22,7 +22,7 @@ static void a2xx_submit(struct msm_gpu *gpu, struct msm_g= em_submit *submit) break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */ - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a3xx_gpu.c index 5273dc8498381ce09e878894f4eb56263900be39..945fe64f835cc6094f1880ea20f= 20584de74a464 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -40,7 +40,7 @@ static void a3xx_submit(struct msm_gpu *gpu, struct msm_g= em_submit *submit) break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */ - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a4xx_gpu.c index 8b4cdf95f4453bb76e7efb93d86080ef678c9f68..50c490b492f08a1a7ebfe33b2f2= 06cafd91a84ba 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -34,7 +34,7 @@ static void a4xx_submit(struct msm_gpu *gpu, struct msm_g= em_submit *submit) break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: /* ignore if there has not been a ctx switch: */ - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index c0b5373e90d7139caa023aec6f272545456acb0a..80b441fe8e3a823c5bd1f74cd8c= 7bb418d0674fb 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -75,7 +75,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct= msm_gem_submit *submit case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: @@ -129,7 +129,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) unsigned int i, ibs =3D 0; =20 if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) { - gpu->cur_ctx_seqno =3D 0; + ring->cur_ctx_seqno =3D 0; a5xx_submit_in_rb(gpu, submit); return; } @@ -164,7 +164,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 32a4faa93d7f072ea6b8d949f4dc9d2a58cec6b9..6e065500b64d6d95599d89c33e6= 703c92f210047 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -109,7 +109,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gp= u, u32 asid; u64 memptr =3D rbmemptr(ring, ttbr0); =20 - if (ctx->seqno =3D=3D a6xx_gpu->base.base.cur_ctx_seqno) + if (ctx->seqno =3D=3D ring->cur_ctx_seqno) return; =20 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) @@ -219,7 +219,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: @@ -305,7 +305,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) case MSM_SUBMIT_CMD_IB_TARGET_BUF: break; case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: - if (gpu->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) + if (ring->cur_ctx_seqno =3D=3D submit->queue->ctx->seqno) break; fallthrough; case MSM_SUBMIT_CMD_BUF: @@ -843,6 +843,7 @@ static int hw_init(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; u64 gmem_range_min; + unsigned int i; int ret; =20 if (!adreno_has_gmu_wrapper(adreno_gpu)) { @@ -1138,7 +1139,8 @@ static int hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring =3D gpu->rb[0]; =20 - gpu->cur_ctx_seqno =3D 0; + for (i =3D 0; i < gpu->nr_rings; i++) + gpu->rb[i]->cur_ctx_seqno =3D 0; =20 /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 3666b42b4ecd7f91b24302d7f229eeefdc3c39b7..c063b3896dc1c193e41b8fc380a= 91a9076376811 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -783,7 +783,7 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem= _submit *submit) mutex_unlock(&gpu->active_lock); =20 gpu->funcs->submit(gpu, submit); - gpu->cur_ctx_seqno =3D submit->queue->ctx->seqno; + submit->ring->cur_ctx_seqno =3D submit->queue->ctx->seqno; =20 pm_runtime_put(&gpu->pdev->dev); hangcheck_timer_reset(gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 1f02bb9956be2720a2760646ccdf92f8bead7dd0..7cabc8480d7c5461ab8d8726fcc= 21690cbaf7366 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -193,17 +193,6 @@ struct msm_gpu { */ refcount_t sysprof_active; =20 - /** - * cur_ctx_seqno: - * - * The ctx->seqno value of the last context to submit rendering, - * and the one with current pgtables installed (for generations - * that support per-context pgtables). Tracked by seqno rather - * than pointer value to avoid dangling pointers, and cases where - * a ctx can be freed and a new one created with the same address. - */ - int cur_ctx_seqno; - /** * lock: * diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm= _ringbuffer.h index 40791b2ade46ef0e16e2a4088291a575d3be9e82..174f83137a49940ec80b1fbf548= e214fa3c32784 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -100,6 +100,16 @@ struct msm_ringbuffer { * preemption. Can be aquired from irq context. */ spinlock_t preempt_lock; + + /** + * cur_ctx_seqno: + * + * The ctx->seqno value of the last context to submit to this ring + * Tracked by seqno rather than pointer value to avoid dangling + * pointers, and cases where a ctx can be freed and a new one created + * with the same address. + */ + int cur_ctx_seqno; }; =20 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, --=20 2.46.1 From nobody Thu Nov 28 05:32:21 2024 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FF441A7266; Thu, 3 Oct 2024 16:13:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971986; cv=none; b=Va6h7HZlLvTBzxtEmK4gO26sned8V8FscjDH5h2j14P10dcbTN/PtZnDQFXFxpwuq5JWl8oeVF6pj+ihx6k3t742/jREvo34/ukMGpkvDD6MdwkJPILVUu+z6FNRyX5BZ8lastWX6C/C/FCDj2GTaatOcYVO0TNbH1UYt0IkRwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971986; c=relaxed/simple; bh=mw98QEzBIwYx44vG8hfTrLa/RurlCEDImHR+oHkKWF4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RoRQhsGUH8i72EidrAxhOSRz9qdnhqq/NZFHwqEOJx//3bdZMnbm2SLefGwYL0ny9Vscqd5EEZ0mfWMxvm5QIEilg2kqKcpY6775KncAn2ws8ju6nPbKOypBUUhMi/FVnw/pT7utgehVESzdGYg6YfkASRkW+9sVc/2Nidn90Bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=i78SLyLR; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i78SLyLR" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a93c1cc74fdso197992066b.3; Thu, 03 Oct 2024 09:13:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727971982; x=1728576782; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wyb3geUIdOaiHlo8mwWpCyJKar3stgK5wmtiUF5Pomg=; b=i78SLyLRY/PK+TdyA3wqO+OG8a3CvV5MukDpAC2cx6GMQ+XcLVHdvxmKgD0Tz0ZucI dP2OkF787bBfCbWdAeDjYy+kfCXPckl5jQZgDAJqZbKdS/YwGs/4XrLgMenx0ZCBr5Br KEn/ttMwLPoaiTXy03/S7MUuUdZEqa1zTONU16LgxoEbwueoNBmY+KcTmsdRwMrdEhzp 16JXHKNp53gwY5x4t25a2TCAH2ui6uRR8AoIwWvE1m2Gv9upsXUIXwtZzLS2F0IfUkbx Rq7iDyR89EfMGxHBHVh9H/sxv6qlUz9MfXKZGFazJbdjy40GSPPUePYUYHsUKuw9oJfu PqVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727971982; x=1728576782; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wyb3geUIdOaiHlo8mwWpCyJKar3stgK5wmtiUF5Pomg=; b=aYHMKilrZ6deW/EkR+o0CG4aHx9PjGXrNCBCkaeLll70dkHaeoZKGgIpxTSdm7J28M LJlc8JOaocAF5pHlSVJHYrTRsFg48WF4loGP5iA1kSOJiTFAMqfc9+MAQqXhXiJX34MR 1EumShzELV8U819ENHOHxej2FDhrkGHJyF6hzVjam2LlESQplBFAcC+mjz/tunmKSluF Jxj++wnvYw+yqE8gmEjRNAZnh1xkWIB5yrqw2yvPU4BtFbbIOn/iSGSsV/N/51SMMDOU dpWGNW56RNMf093vXxUAgM7CIl+wT2OGCK+YS0y0LIwB2TH54c229xGdCDpXX9tRkWbg MgUQ== X-Forwarded-Encrypted: i=1; AJvYcCU7nOeD4fl6K3R1RamzYZAWCGM4NvXY9IQ03uHNWZK6VaEppGAFA9bmfCqwUCw8tvNFIjrOehE4xZMNhYKO@vger.kernel.org, AJvYcCWiggCsU9yAs4CJcUSzh/JMF9SlgBzGNbo8ZDHDV39hkhm83L0zcj4ESu3l9HifRnQVARU9nwZMm9I=@vger.kernel.org X-Gm-Message-State: AOJu0YzUgSlOVtFpDWWIDZph+OeRi/WFgXSULdIPzvARfOVObSCnAAfO eh51F4EzOdwlCf5r3ScCV7jCWLCLPJZXnliz7lxq1cUQ2QcmI/pw X-Google-Smtp-Source: AGHT+IGfZEdpncoLihfFB8ebzwOnEY+Udb2v0k7UqgH0GTJchQuHmXd0rMuPF5wDpj9ySOR443QKlg== X-Received: by 2002:a17:907:7fa5:b0:a90:c411:24e0 with SMTP id a640c23a62f3a-a98f8250998mr675116666b.23.1727971982159; Thu, 03 Oct 2024 09:13:02 -0700 (PDT) Received: from [192.168.1.17] (host-79-12-161-203.retail.telecomitalia.it. [79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:13:01 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:52 +0200 Subject: [PATCH v8 03/12] drm/msm: Add a `preempt_record_size` field Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-3-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=2480; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=mw98QEzBIwYx44vG8hfTrLa/RurlCEDImHR+oHkKWF4=; b=z+/TNgc/HPX9gfeh5PlsvknjTcGVNf8DSg7n/ZXpQRoD7DYcCFOy5ZKWUWnxKEuLXuL7m92bs 92Sdo8PrHFaCVVaxCYxlJoFortKUOrShPVLahPPteVCI9FpX7tfmpvb X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Adds a field to `adreno_info` to store the GPU specific preempt record size. Reviewed-by: Akhil P Oommen Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 68ba9aed5506ea2f367ff0282a73fdd1122f2526..316f23ca91671d973797f2a5b69= 344f376707325 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1190,6 +1190,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, }, .address_space_size =3D SZ_16G, + .preempt_record_size =3D 2860 * SZ_1K, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */ .family =3D ADRENO_7XX_GEN2, @@ -1209,6 +1210,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7020100, }, .address_space_size =3D SZ_16G, + .preempt_record_size =3D 4192 * SZ_1K, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family =3D ADRENO_7XX_GEN2, @@ -1227,6 +1229,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7050001, }, .address_space_size =3D SZ_256G, + .preempt_record_size =3D 4192 * SZ_1K, }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family =3D ADRENO_7XX_GEN3, @@ -1245,6 +1248,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7090100, }, .address_space_size =3D SZ_16G, + .preempt_record_size =3D 3572 * SZ_1K, } }; DECLARE_ADRENO_GPULIST(a7xx); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 1ab523a163a00b333a85b099e9eb9209e6a2e646..6b1888280a83e6288c4b071733d= 5d6097afe3a99 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -111,6 +111,7 @@ struct adreno_info { * {SHRT_MAX, 0} sentinal. */ struct adreno_speedbin *speedbins; + u64 preempt_record_size; }; =20 #define ADRENO_CHIP_IDS(tbl...) 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[79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:13:03 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:53 +0200 Subject: [PATCH v8 04/12] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-4-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=1523; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=95uWYhYXrJwsS/Si/bR6gRgvDdDmC6nz9iFGaH/gMIk=; b=NMHsNg8FHqzK322WlIXiE3vzgXWMVxXgrSoNw2PJTSBYYSgtHyE+fwI/sJiv3kXLNY42Kh38j AzstkrtmzP+Daw+BJi1y/uCfEMROet/14ww3bE8Iz9B0L8F+Uaxs+4d X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml. Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/dr= m/msm/registers/adreno/a6xx.xml index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc= 1034f6b7a2e41 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1337,7 +1337,12 @@ to upconvert to 32b float internally? =20 - + + + + + + --=20 2.46.1 From nobody Thu Nov 28 05:32:21 2024 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EDD91A7AD6; Thu, 3 Oct 2024 16:13:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971988; cv=none; b=CrPy21R7BzS3Alpuko7Y/CtY+xwETdYU3cKiY9hjujeQ0wlAS/y0W/gwC1FB3qY+k7jib/5ZybHRCKM4QWLMrj7AJeatAIWBmpBDdDpBlfaa686nmqal4MU1+bXfKxerafM1RyVUQ3fSdzLOScdvRmAPl0RsFlAlIALqn1oDk4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971988; c=relaxed/simple; bh=7OY9AiaQ19Ia+PqqCV6YZvq+XDpZw+wy+7bMWhQ2Bvs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Eq+nDQ1HYmcT86xF7L65PpzgNgCoqEL4Zu4ovric6S24Nn/uZunhN3Xmn3J7m6EDCi1zqLKloJCsVd9/7V57vM8r9MQCK3LcK98engyahE5VLoPs+hup3L2iI0ghum4B7cwA44Rw7hW/TvcjEcWpCOVuLVZ6S/TYg0XbN8L2M9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UAG4qHF+; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UAG4qHF+" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-5c5cf26b95aso1462554a12.3; Thu, 03 Oct 2024 09:13:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727971986; x=1728576786; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/V/6a2TW5ipcM35DEEW7Cwm4LM4Qc3jfg/uzlisxQGI=; b=UAG4qHF+zUwgKER5ohKa2GLt+0h0qC1Dnf3pnob+Ix+C2YU31aB81prwFZ5DIqJdXl GNgpjLwUALCmzKDK8RBF4rqXcaWN0rFW4kE1tyr7cIlievqzHm5jhFoGTmuLiNDnb42q K1Jfcr0IX/sOeVU2ZkP/IWH5qbX+QY8SWrg++uBV6WxkFs7q9XJvUsn/KmwePr27dRTv 1sH8TUAOA8mAocHmWoc2jwcn+P7a/3L7OYdzX93F6TUr1+AXfC0G3j8iAaAKeKkGT7CV VDJpJWHcgFSMbbRM7RV4ye4RE1m2e7Judcgjf37eZ1qzwoSrF6wox9OfM+IGkhaQ1mM2 /liA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727971986; x=1728576786; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/V/6a2TW5ipcM35DEEW7Cwm4LM4Qc3jfg/uzlisxQGI=; b=dryLgaxmhkiNCEzNOKW4fVEhvf7p9lFLanKIch+DORJeT1JooWjnV/FkIL2P95yfm3 t6N1LlwwBf0S/mPIS7YLlviy94BNK8rFTHbQ4MEbk3eihna0TUTd0yM9uZ+CMjcOfrhY M4WjKlt6XZZ6TXhmSybJyOtAZWMtRWexyiQzPjvaUT2S8q9TMaFbMeasr7lHP0IcsFOn HfhpI/G/JGuOEqT/1lHISFK6p7Q+xVTskoYSFUWQO3mqsKMZK4kVpI4YMBL4J6NLgnpg f+YLTnc2mmzY52A9/D12isBA/96BRBez8gjrxgBHQ6nTAlgMfcNo8zwQcuzPJBBi17t0 FMig== X-Forwarded-Encrypted: i=1; AJvYcCWoB7alOsZRx/5UWIK+h9HUeMb9LBwTXqKETtYSI8ZySEcBi6k2IS2qZaW2cOcGJ/tpcEq+obDec20=@vger.kernel.org, AJvYcCXjIC2o9z9DLsRm+hEVYxzg4EoZlRFypVvHl4+v6LnG5icAW+xzo/oM0kvuDC58+KYQYQDzBiAP1Fag9sMQ@vger.kernel.org X-Gm-Message-State: AOJu0YwpnKOw1x4bA0nKpEZedh2Ohp2tZiQZkYPgE+S0bom3Iq4IX7KA nS7RPh1CNmj4gdE+Ou0nNKpyItEOA+VXRvwi71yMzXtsc3dBG/Pr8a/dE/QVxKvm5w== X-Google-Smtp-Source: AGHT+IGDWP3v0Di8kvxDzdey+AWcUqDj4gsqUQxdxWrG+YC8QFPIY1Q5HcSXjl682jM68aq3k1TFHA== X-Received: by 2002:a17:907:2d88:b0:a86:83f8:f5a2 with SMTP id a640c23a62f3a-a98f823cbc9mr655096566b.19.1727971985501; Thu, 03 Oct 2024 09:13:05 -0700 (PDT) Received: from [192.168.1.17] (host-79-12-161-203.retail.telecomitalia.it. [79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.13.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:13:05 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:54 +0200 Subject: [PATCH v8 05/12] drm/msm/a6xx: Add a pwrup_list field to a6xx_info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-5-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=4169; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=7OY9AiaQ19Ia+PqqCV6YZvq+XDpZw+wy+7bMWhQ2Bvs=; b=ZXywTzS1ODfgZc7HTXviCdSKY2foHZWt7a3poRCQsi7lB7WZIDdCZtCtaffDCzVRd8KYC1Euc CxBP4/NwGrMCqvKyp2m0N26oXTsRQwGC+C2sPxuUrCW7Yw/cxNmwP65 X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= Add a field to contain the pwup_reglist needed for preemption. Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 13 +++++++++++++ 3 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 316f23ca91671d973797f2a5b69344f376707325..e4d271fa89cc66f188be04206e2= 67fabd83cca83 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1150,6 +1150,28 @@ static const u32 a730_protect_regs[] =3D { }; DECLARE_ADRENO_PROTECT(a730_protect, 48); =20 +static const uint32_t a7xx_pwrup_reglist_regs[] =3D { + REG_A6XX_UCHE_TRAP_BASE, + REG_A6XX_UCHE_TRAP_BASE + 1, + REG_A6XX_UCHE_WRITE_THRU_BASE, + REG_A6XX_UCHE_WRITE_THRU_BASE + 1, + REG_A6XX_UCHE_GMEM_RANGE_MIN, + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1, + REG_A6XX_UCHE_GMEM_RANGE_MAX, + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1, + REG_A6XX_UCHE_CACHE_WAYS, + REG_A6XX_UCHE_MODE_CNTL, + REG_A6XX_RB_NC_MODE_CNTL, + REG_A6XX_RB_CMP_DBG_ECO_CNTL, + REG_A7XX_GRAS_NC_MODE_CNTL, + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, + REG_A6XX_UCHE_GBIF_GX_CONFIG, + REG_A6XX_UCHE_CLIENT_PF, + REG_A6XX_TPL1_DBG_ECO_CNTL1, +}; + +DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist); + static const struct adreno_info a7xx_gpus[] =3D { { .chip_ids =3D ADRENO_CHIP_IDS(0x07000200), @@ -1188,6 +1210,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a730_hwcg, .protect =3D &a730_protect, + .pwrup_reglist =3D &a7xx_pwrup_reglist, }, .address_space_size =3D SZ_16G, .preempt_record_size =3D 2860 * SZ_1K, @@ -1207,6 +1230,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, + .pwrup_reglist =3D &a7xx_pwrup_reglist, .gmu_chipid =3D 0x7020100, }, .address_space_size =3D SZ_16G, @@ -1226,6 +1250,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, .protect =3D &a730_protect, + .pwrup_reglist =3D &a7xx_pwrup_reglist, .gmu_chipid =3D 0x7050001, }, .address_space_size =3D SZ_256G, @@ -1245,6 +1270,7 @@ static const struct adreno_info a7xx_gpus[] =3D { .zapfw =3D "gen70900_zap.mbn", .a6xx =3D &(const struct a6xx_info) { .protect =3D &a730_protect, + .pwrup_reglist =3D &a7xx_pwrup_reglist, .gmu_chipid =3D 0x7090100, }, .address_space_size =3D SZ_16G, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index e3e5c53ae8af2cc59a21160f05c59fd125cb94b1..2f5f307ac3b6845197b06ca3754= abc88d698007c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -17,10 +17,12 @@ extern bool hang_debug; * * @hwcg: hw clock gating register sequence * @protect: CP_PROTECT settings + * @pwrup_reglist pwrup reglist for preemption */ struct a6xx_info { const struct adreno_reglist *hwcg; const struct adreno_protect *protect; + const struct adreno_reglist_list *pwrup_reglist; u32 gmu_chipid; }; =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 6b1888280a83e6288c4b071733d5d6097afe3a99..58c63d0fbbff9818393fc62ee3c= f2703365bec23 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -157,6 +157,19 @@ static const struct adreno_protect name =3D { \ .count_max =3D __count_max, \ }; =20 +struct adreno_reglist_list { + /** @reg: List of register **/ + const u32 *regs; + /** @count: Number of registers in the list **/ + u32 count; +}; + +#define DECLARE_ADRENO_REGLIST_LIST(name) \ +static const struct adreno_reglist_list name =3D { \ + .regs =3D name ## _regs, \ + .count =3D ARRAY_SIZE(name ## _regs), \ +}; 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[79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:13:07 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:55 +0200 Subject: [PATCH v8 06/12] drm/msm/a6xx: Implement preemption for a7xx targets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-6-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong , Sharat Masetty X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=32233; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=la2yYs2rvztdmbAN8YutY92BLRLI4ynYhLnG47NiSsY=; b=evJfdR5Ggwy3OiiuYiKpP73tb8flcUL53pAYfsxaoF+gPiIKtSu02TpSmIJPCmtJtGbDP85Ql 6tRqvdzpveXAuMZtJIXSMhJlUJGtZljy9oWUAdUIxF2IB3vsB7MDg+C X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= This patch implements preemption feature for A6xx targets, this allows the GPU to switch to a higher priority ringbuffer if one is ready. A6XX hardware as such supports multiple levels of preemption granularities, ranging from coarse grained(ringbuffer level) to a more fine grained such as draw-call level or a bin boundary level preemption. This patch enables the basic preemption level, with more fine grained preemption support to follow. Reviewed-by: Akhil P Oommen Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Sharat Masetty Signed-off-by: Antonino Maniscalco --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 193 ++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 162 ++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 393 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/msm_ringbuffer.h | 7 + 5 files changed, 745 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index f5e2838c6a76505b353f83c9fe9c997f1c282701..32e915109a59dda96ed76ddd2b4= f57bb225f4572 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -23,6 +23,7 @@ adreno-y :=3D \ adreno/a6xx_gpu.o \ adreno/a6xx_gmu.o \ adreno/a6xx_hfi.o \ + adreno/a6xx_preempt.o \ =20 adreno-$(CONFIG_DEBUG_FS) +=3D adreno/a5xx_debugfs.o \ =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6e065500b64d6d95599d89c33e6703c92f210047..b4cd562f1dd8660c77430e1aeac= 7e4b7af32bfc7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -68,6 +68,8 @@ static void update_shadow_rptr(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) =20 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); uint32_t wptr; unsigned long flags; =20 @@ -81,12 +83,17 @@ static void a6xx_flush(struct msm_gpu *gpu, struct msm_= ringbuffer *ring) /* Make sure to wrap wptr if we need to */ wptr =3D get_wptr(ring); =20 - spin_unlock_irqrestore(&ring->preempt_lock, flags); - - /* Make sure everything is posted before making a decision */ - mb(); + /* Update HW if this is the current ring and we are not in preempt*/ + if (!a6xx_in_preempt(a6xx_gpu)) { + if (a6xx_gpu->cur_ring =3D=3D ring) + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + else + ring->restore_wptr =3D true; + } else { + ring->restore_wptr =3D true; + } =20 - gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + spin_unlock_irqrestore(&ring->preempt_lock, flags); } =20 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, @@ -138,12 +145,14 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_= gpu, =20 /* * Write the new TTBR0 to the memstore. This is good for debugging. + * Needed for preemption */ - OUT_PKT7(ring, CP_MEM_WRITE, 4); + OUT_PKT7(ring, CP_MEM_WRITE, 5); OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); OUT_RING(ring, lower_32_bits(ttbr)); - OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); + OUT_RING(ring, upper_32_bits(ttbr)); + OUT_RING(ring, ctx->seqno); =20 /* * Sync both threads after switching pagetables and enable BR only @@ -268,6 +277,34 @@ static void a6xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) a6xx_flush(gpu, ring); } =20 +static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring, + struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue) +{ + OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12); + + OUT_RING(ring, SMMU_INFO); + /* don't save SMMU, we write the record from the kernel instead */ + OUT_RING(ring, 0); + OUT_RING(ring, 0); + + /* privileged and non secure buffer save */ + OUT_RING(ring, NON_SECURE_SAVE_ADDR); + OUT_RING(ring, lower_32_bits( + a6xx_gpu->preempt_iova[ring->id])); + OUT_RING(ring, upper_32_bits( + a6xx_gpu->preempt_iova[ring->id])); + + /* user context buffer save, seems to be unnused by fw */ + OUT_RING(ring, NON_PRIV_SAVE_ADDR); + OUT_RING(ring, 0); + OUT_RING(ring, 0); + + OUT_RING(ring, COUNTER); + /* seems OK to set to 0 to disable it */ + OUT_RING(ring, 0); + OUT_RING(ring, 0); +} + static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index =3D submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; @@ -285,6 +322,13 @@ static void a7xx_submit(struct msm_gpu *gpu, struct ms= m_gem_submit *submit) =20 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); =20 + /* + * If preemption is enabled, then set the pseudo register for the save + * sequence + */ + if (gpu->nr_rings > 1) + a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue); + get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0), rbmemptr_stats(ring, index, cpcycles_start)); get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, @@ -376,6 +420,8 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm= _gem_submit *submit) OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence))); OUT_RING(ring, submit->seqno); =20 + a6xx_gpu->last_seqno[ring->id] =3D submit->seqno; + /* write the ringbuffer timestamp */ OUT_PKT7(ring, CP_EVENT_WRITE, 4); OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27)); @@ -389,10 +435,32 @@ static void a7xx_submit(struct msm_gpu *gpu, struct m= sm_gem_submit *submit) OUT_PKT7(ring, CP_SET_MARKER, 1); OUT_RING(ring, 0x100); /* IFPC enable */ =20 + /* If preemption is enabled */ + if (gpu->nr_rings > 1) { + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + + /* + * If dword[2:1] are non zero, they specify an address for + * the CP to write the value of dword[3] to on preemption + * complete. Write 0 to skip the write + */ + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Data value - not used if the address above is 0 */ + OUT_RING(ring, 0x01); + /* generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + } + + trace_msm_gpu_submit_flush(submit, gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); =20 a6xx_flush(gpu, ring); + + /* Check to see if we need to start preemption */ + a6xx_preempt_trigger(gpu); } =20 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) @@ -588,6 +656,77 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21); } =20 +static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + const struct adreno_reglist_list *reglist; + void *ptr =3D a6xx_gpu->pwrup_reglist_ptr; + struct cpu_gpu_lock *lock =3D ptr; + u32 *dest =3D (u32 *)&lock->regs[0]; + int i; + + reglist =3D adreno_gpu->info->a6xx->pwrup_reglist; + + lock->gpu_req =3D lock->cpu_req =3D lock->turn =3D 0; + lock->ifpc_list_len =3D 0; + lock->preemption_list_len =3D reglist->count; + + /* + * For each entry in each of the lists, write the offset and the current + * register value into the GPU buffer + */ + for (i =3D 0; i < reglist->count; i++) { + *dest++ =3D reglist->regs[i]; + *dest++ =3D gpu_read(gpu, reglist->regs[i]); + } + + /* + * The overall register list is composed of + * 1. Static IFPC-only registers + * 2. Static IFPC + preemption registers + * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects) + * + * The first two lists are static. Size of these lists are stored as + * number of pairs in ifpc_list_len and preemption_list_len + * respectively. With concurrent binning, Some of the perfcounter + * registers being virtualized, CP needs to know the pipe id to program + * the aperture inorder to restore the same. Thus, third list is a + * dynamic list with triplets as + * (
), and the length is + * stored as number for triplets in dynamic_list_len. + */ + lock->dynamic_list_len =3D 0; +} + +static int a7xx_preempt_start(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct msm_ringbuffer *ring =3D gpu->rb[0]; + + if (gpu->nr_rings <=3D 1) + return 0; + + /* Turn CP protection off */ + OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); + OUT_RING(ring, 0); + + a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL); + + /* Yield the floor on command completion */ + OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + OUT_RING(ring, 0x00); + /* Generate interrupt on preemption completion */ + OUT_RING(ring, 0x00); + + a6xx_flush(gpu, ring); + + return a6xx_idle(gpu, ring) ? 0 : -EINVAL; +} + static int a6xx_cp_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring =3D gpu->rb[0]; @@ -619,6 +758,8 @@ static int a6xx_cp_init(struct msm_gpu *gpu) =20 static int a7xx_cp_init(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); struct msm_ringbuffer *ring =3D gpu->rb[0]; u32 mask; =20 @@ -656,11 +797,11 @@ static int a7xx_cp_init(struct msm_gpu *gpu) =20 /* *Don't* send a power up reg list for concurrent binning (TODO) */ /* Lo address */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova)); /* Hi address */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova)); /* BIT(31) set =3D> read the regs from the list */ - OUT_RING(ring, 0x00000000); + OUT_RING(ring, BIT(31)); =20 a6xx_flush(gpu, ring); return a6xx_idle(gpu, ring) ? 0 : -EINVAL; @@ -784,6 +925,16 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); } =20 + a6xx_gpu->pwrup_reglist_ptr =3D msm_gem_kernel_new(gpu->dev, PAGE_SIZE, + MSM_BO_WC | MSM_BO_MAP_PRIV, + gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, + &a6xx_gpu->pwrup_reglist_iova); + + if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr)) + return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr); + + msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist"); + return 0; } =20 @@ -1128,6 +1279,8 @@ static int hw_init(struct msm_gpu *gpu) if (a6xx_gpu->shadow_bo) { gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0])); + for (unsigned int i =3D 0; i < gpu->nr_rings; i++) + a6xx_gpu->shadow[i] =3D 0; } =20 /* ..which means "always" on A7xx, also for BV shadow */ @@ -1136,6 +1289,8 @@ static int hw_init(struct msm_gpu *gpu) rbmemptr(gpu->rb[0], bv_rptr)); } =20 + a6xx_preempt_hw_init(gpu); + /* Always come up on rb 0 */ a6xx_gpu->cur_ring =3D gpu->rb[0]; =20 @@ -1145,6 +1300,11 @@ static int hw_init(struct msm_gpu *gpu) /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); =20 + if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) { + a7xx_patch_pwrup_reglist(gpu); + a6xx_gpu->pwrup_reglist_emitted =3D true; + } + ret =3D adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu= ); if (ret) goto out; @@ -1182,6 +1342,10 @@ static int hw_init(struct msm_gpu *gpu) out: if (adreno_has_gmu_wrapper(adreno_gpu)) return ret; + + /* Last step - yield the ringbuffer */ + a7xx_preempt_start(gpu); + /* * Tell the GMU that we are done touching the GPU and it can start power * management @@ -1559,8 +1723,13 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) a7xx_sw_fuse_violation_irq(gpu); =20 - if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) { msm_gpu_retire(gpu); + a6xx_preempt_trigger(gpu); + } + + if (status & A6XX_RBBM_INT_0_MASK_CP_SW) + a6xx_preempt_irq(gpu); =20 return IRQ_HANDLED; } @@ -2333,6 +2502,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_fault_handler); =20 a6xx_calc_ubwc_config(adreno_gpu); + /* Set up the preemption specific bits and pieces for each ringbuffer */ + a6xx_preempt_init(gpu); =20 return gpu; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index 2f5f307ac3b6845197b06ca3754abc88d698007c..070bce058d3ff92aa7452b69776= 3a16ab7e2faee 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -12,6 +12,24 @@ =20 extern bool hang_debug; =20 +struct cpu_gpu_lock { + uint32_t gpu_req; + uint32_t cpu_req; + uint32_t turn; + union { + struct { + uint16_t list_length; + uint16_t list_offset; + }; + struct { + uint8_t ifpc_list_len; + uint8_t preemption_list_len; + uint16_t dynamic_list_len; + }; + }; + uint64_t regs[62]; +}; + /** * struct a6xx_info - a6xx specific information from device table * @@ -33,6 +51,23 @@ struct a6xx_gpu { uint64_t sqe_iova; =20 struct msm_ringbuffer *cur_ring; + struct msm_ringbuffer *next_ring; + + struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; + void *preempt[MSM_GPU_MAX_RINGS]; + uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; + struct drm_gem_object *preempt_smmu_bo[MSM_GPU_MAX_RINGS]; + void *preempt_smmu[MSM_GPU_MAX_RINGS]; + uint64_t preempt_smmu_iova[MSM_GPU_MAX_RINGS]; + uint32_t last_seqno[MSM_GPU_MAX_RINGS]; + + atomic_t preempt_state; + spinlock_t eval_lock; + struct timer_list preempt_timer; + + unsigned int preempt_level; + bool uses_gmem; + bool skip_save_restore; =20 struct a6xx_gmu gmu; =20 @@ -40,6 +75,11 @@ struct a6xx_gpu { uint64_t shadow_iova; uint32_t *shadow; =20 + struct drm_gem_object *pwrup_reglist_bo; + void *pwrup_reglist_ptr; + uint64_t pwrup_reglist_iova; + bool pwrup_reglist_emitted; + bool has_whereami; =20 void __iomem *llc_mmio; @@ -51,6 +91,100 @@ struct a6xx_gpu { =20 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) =20 +/* + * In order to do lockless preemption we use a simple state machine to pro= gress + * through the process. + * + * PREEMPT_NONE - no preemption in progress. Next state START. + * PREEMPT_START - The trigger is evaluating if preemption is possible. Ne= xt + * states: TRIGGERED, NONE + * PREEMPT_FINISH - An intermediate state before moving back to NONE. Next + * state: NONE. + * PREEMPT_TRIGGERED: A preemption has been executed on the hardware. Next + * states: FAULTED, PENDING + * PREEMPT_FAULTED: A preemption timed out (never completed). This will tr= igger + * recovery. Next state: N/A + * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is + * checking the success of the operation. Next state: FAULTED, NONE. + */ + +enum a6xx_preempt_state { + PREEMPT_NONE =3D 0, + PREEMPT_START, + PREEMPT_FINISH, + PREEMPT_TRIGGERED, + PREEMPT_FAULTED, + PREEMPT_PENDING, +}; + +/* + * struct a6xx_preempt_record is a shared buffer between the microcode and= the + * CPU to store the state for preemption. The record itself is much larger + * (2112k) but most of that is used by the CP for storage. + * + * There is a preemption record assigned per ringbuffer. When the CPU trig= gers a + * preemption, it fills out the record with the useful information (wptr, = ring + * base, etc) and the microcode uses that information to set up the CP fol= lowing + * the preemption. When a ring is switched out, the CP will save the ring= buffer + * state back to the record. In this way, once the records are properly se= t up + * the CPU can quickly switch back and forth between ringbuffers by only + * updating a few registers (often only the wptr). + * + * These are the CPU aware registers in the record: + * @magic: Must always be 0xAE399D6EUL + * @info: Type of the record - written 0 by the CPU, updated by the CP + * @errno: preemption error record + * @data: Data field in YIELD and SET_MARKER packets, Written and used by = CP + * @cntl: Value of RB_CNTL written by CPU, save/restored by CP + * @rptr: Value of RB_RPTR written by CPU, save/restored by CP + * @wptr: Value of RB_WPTR written by CPU, save/restored by CP + * @_pad: Reserved/padding + * @rptr_addr: Value of RB_RPTR_ADDR_LO|HI written by CPU, save/restored b= y CP + * @rbase: Value of RB_BASE written by CPU, save/restored by CP + * @counter: GPU address of the storage area for the preemption counters + * @bv_rptr_addr: Value of BV_RB_RPTR_ADDR_LO|HI written by CPU, save/rest= ored by CP + */ +struct a6xx_preempt_record { + u32 magic; + u32 info; + u32 errno; + u32 data; + u32 cntl; + u32 rptr; + u32 wptr; + u32 _pad; + u64 rptr_addr; + u64 rbase; + u64 counter; + u64 bv_rptr_addr; +}; + +#define A6XX_PREEMPT_RECORD_MAGIC 0xAE399D6EUL + +#define PREEMPT_SMMU_INFO_SIZE 4096 + +#define PREEMPT_RECORD_SIZE(adreno_gpu) \ + ((adreno_gpu->info->preempt_record_size) =3D=3D 0 ? \ + 4192 * SZ_1K : (adreno_gpu->info->preempt_record_size)) + +/* + * The preemption counter block is a storage area for the value of the + * preemption counters that are saved immediately before context switch. We + * append it on to the end of the allocation for the preemption record. + */ +#define A6XX_PREEMPT_COUNTER_SIZE (16 * 4) + +struct a7xx_cp_smmu_info { + u32 magic; + u32 _pad4; + u64 ttbr0; + u32 asid; + u32 context_idr; + u32 context_bank; +}; + +#define GEN7_CP_SMMU_INFO_MAGIC 0x241350d5UL + /* * Given a register and a count, return a value to program into * REG_CP_PROTECT_REG(n) - this will block both reads and writes for @@ -108,6 +242,34 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct de= vice_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *n= ode); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); =20 +void a6xx_preempt_init(struct msm_gpu *gpu); +void a6xx_preempt_hw_init(struct msm_gpu *gpu); +void a6xx_preempt_trigger(struct msm_gpu *gpu); +void a6xx_preempt_irq(struct msm_gpu *gpu); +void a6xx_preempt_fini(struct msm_gpu *gpu); +int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); +void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu, + struct msm_gpu_submitqueue *queue); + +/* Return true if we are in a preempt state */ +static inline bool a6xx_in_preempt(struct a6xx_gpu *a6xx_gpu) +{ + /* + * Make sure the read to preempt_state is ordered with respect to reads + * of other variables before ... + */ + smp_rmb(); + + int preempt_state =3D atomic_read(&a6xx_gpu->preempt_state); + + /* ... and after. */ + smp_rmb(); + + return !(preempt_state =3D=3D PREEMPT_NONE || + preempt_state =3D=3D PREEMPT_FINISH); +} + void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended); unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/ms= m/adreno/a6xx_preempt.c new file mode 100644 index 0000000000000000000000000000000000000000..fd2a90360740591d45758f7311e= c5cdda1855b20 --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023 Collabora, Ltd. */ +/* Copyright (c) 2024 Valve Corporation */ + +#include "msm_gem.h" +#include "a6xx_gpu.h" +#include "a6xx_gmu.xml.h" +#include "msm_mmu.h" + +/* + * Try to transition the preemption state from old to new. Return + * true on success or false if the original state wasn't 'old' + */ +static inline bool try_preempt_state(struct a6xx_gpu *a6xx_gpu, + enum a6xx_preempt_state old, enum a6xx_preempt_state new) +{ + enum a6xx_preempt_state cur =3D atomic_cmpxchg(&a6xx_gpu->preempt_state, + old, new); + + return (cur =3D=3D old); +} + +/* + * Force the preemption state to the specified state. This is used in cas= es + * where the current state is known and won't change + */ +static inline void set_preempt_state(struct a6xx_gpu *gpu, + enum a6xx_preempt_state new) +{ + /* + * preempt_state may be read by other cores trying to trigger a + * preemption or in the interrupt handler so barriers are needed + * before... + */ + smp_mb__before_atomic(); + atomic_set(&gpu->preempt_state, new); + /* ... and after*/ + smp_mb__after_atomic(); +} + +/* Write the most recent wptr for the given ring into the hardware */ +static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer = *ring) +{ + unsigned long flags; + uint32_t wptr; + + spin_lock_irqsave(&ring->preempt_lock, flags); + + if (ring->restore_wptr) { + wptr =3D get_wptr(ring); + + gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); + + ring->restore_wptr =3D false; + } + + spin_unlock_irqrestore(&ring->preempt_lock, flags); +} + +/* Return the highest priority ringbuffer with something in it */ +static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + + unsigned long flags; + int i; + + for (i =3D 0; i < gpu->nr_rings; i++) { + bool empty; + struct msm_ringbuffer *ring =3D gpu->rb[i]; + + spin_lock_irqsave(&ring->preempt_lock, flags); + empty =3D (get_wptr(ring) =3D=3D gpu->funcs->get_rptr(gpu, ring)); + if (!empty && ring =3D=3D a6xx_gpu->cur_ring) + empty =3D ring->memptrs->fence =3D=3D a6xx_gpu->last_seqno[i]; + spin_unlock_irqrestore(&ring->preempt_lock, flags); + + if (!empty) + return ring; + } + + return NULL; +} + +static void a6xx_preempt_timer(struct timer_list *t) +{ + struct a6xx_gpu *a6xx_gpu =3D from_timer(a6xx_gpu, t, preempt_timer); + struct msm_gpu *gpu =3D &a6xx_gpu->base.base; + struct drm_device *dev =3D gpu->dev; + + if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED)) + return; + + dev_err(dev->dev, "%s: preemption timed out\n", gpu->name); + kthread_queue_work(gpu->worker, &gpu->recover_work); +} + +void a6xx_preempt_irq(struct msm_gpu *gpu) +{ + uint32_t status; + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + struct drm_device *dev =3D gpu->dev; + + if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING)) + return; + + /* Delete the preemption watchdog timer */ + del_timer(&a6xx_gpu->preempt_timer); + + /* + * The hardware should be setting the stop bit of CP_CONTEXT_SWITCH_CNTL + * to zero before firing the interrupt, but there is a non zero chance + * of a hardware condition or a software race that could set it again + * before we have a chance to finish. If that happens, log and go for + * recovery + */ + status =3D gpu_read(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL); + if (unlikely(status & A6XX_CP_CONTEXT_SWITCH_CNTL_STOP)) { + DRM_DEV_ERROR(&gpu->pdev->dev, + "!!!!!!!!!!!!!!!! preemption faulted !!!!!!!!!!!!!! irq\n"); + set_preempt_state(a6xx_gpu, PREEMPT_FAULTED); + dev_err(dev->dev, "%s: Preemption failed to complete\n", + gpu->name); + kthread_queue_work(gpu->worker, &gpu->recover_work); + return; + } + + a6xx_gpu->cur_ring =3D a6xx_gpu->next_ring; + a6xx_gpu->next_ring =3D NULL; + + set_preempt_state(a6xx_gpu, PREEMPT_FINISH); + + update_wptr(gpu, a6xx_gpu->cur_ring); + + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + + /* + * Retrigger preemption to avoid a deadlock that might occur when preempt= ion + * is skipped due to it being already in flight when requested. + */ + a6xx_preempt_trigger(gpu); +} + +void a6xx_preempt_hw_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings =3D=3D 1) + return; + + for (i =3D 0; i < gpu->nr_rings; i++) { + struct a6xx_preempt_record *record_ptr =3D a6xx_gpu->preempt[i]; + + record_ptr->wptr =3D 0; + record_ptr->rptr =3D 0; + record_ptr->rptr_addr =3D shadowptr(a6xx_gpu, gpu->rb[i]); + record_ptr->info =3D 0; + record_ptr->data =3D 0; + record_ptr->rbase =3D gpu->rb[i]->iova; + } + + /* Write a 0 to signal that we aren't switching pagetables */ + gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0); + + /* Enable the GMEM save/restore feature for preemption */ + gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x1); + + /* Reset the preemption state */ + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + + spin_lock_init(&a6xx_gpu->eval_lock); + + /* Always come up on rb 0 */ + a6xx_gpu->cur_ring =3D gpu->rb[0]; +} + +void a6xx_preempt_trigger(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + unsigned long flags; + struct msm_ringbuffer *ring; + unsigned int cntl; + + if (gpu->nr_rings =3D=3D 1) + return; + + /* + * Lock to make sure another thread attempting preemption doesn't skip it + * while we are still evaluating the next ring. This makes sure the other + * thread does start preemption if we abort it and avoids a soft lock. + */ + spin_lock_irqsave(&a6xx_gpu->eval_lock, flags); + + /* + * Try to start preemption by moving from NONE to START. If + * unsuccessful, a preemption is already in flight + */ + if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) { + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + return; + } + + cntl =3D A6XX_CP_CONTEXT_SWITCH_CNTL_LEVEL(a6xx_gpu->preempt_level); + + if (a6xx_gpu->skip_save_restore) + cntl |=3D A6XX_CP_CONTEXT_SWITCH_CNTL_SKIP_SAVE_RESTORE; + + if (a6xx_gpu->uses_gmem) + cntl |=3D A6XX_CP_CONTEXT_SWITCH_CNTL_USES_GMEM; + + cntl |=3D A6XX_CP_CONTEXT_SWITCH_CNTL_STOP; + + /* Get the next ring to preempt to */ + ring =3D get_next_ring(gpu); + + /* + * If no ring is populated or the highest priority ring is the current + * one do nothing except to update the wptr to the latest and greatest + */ + if (!ring || (a6xx_gpu->cur_ring =3D=3D ring)) { + set_preempt_state(a6xx_gpu, PREEMPT_FINISH); + update_wptr(gpu, a6xx_gpu->cur_ring); + set_preempt_state(a6xx_gpu, PREEMPT_NONE); + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + return; + } + + spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags); + + spin_lock_irqsave(&ring->preempt_lock, flags); + + struct a7xx_cp_smmu_info *smmu_info_ptr =3D + a6xx_gpu->preempt_smmu[ring->id]; + struct a6xx_preempt_record *record_ptr =3D a6xx_gpu->preempt[ring->id]; + u64 ttbr0 =3D ring->memptrs->ttbr0; + u32 context_idr =3D ring->memptrs->context_idr; + + smmu_info_ptr->ttbr0 =3D ttbr0; + smmu_info_ptr->context_idr =3D context_idr; + record_ptr->wptr =3D get_wptr(ring); + + /* + * The GPU will write the wptr we set above when we preempt. Reset + * restore_wptr to make sure that we don't write WPTR to the same + * thing twice. It's still possible subsequent submissions will update + * wptr again, in which case they will set the flag to true. This has + * to be protected by the lock for setting the flag and updating wptr + * to be atomic. + */ + ring->restore_wptr =3D false; + + spin_unlock_irqrestore(&ring->preempt_lock, flags); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, + a6xx_gpu->preempt_smmu_iova[ring->id]); + + gpu_write64(gpu, + REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR, + a6xx_gpu->preempt_iova[ring->id]); + + a6xx_gpu->next_ring =3D ring; + + /* Start a timer to catch a stuck preemption */ + mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000)); + + /* Set the preemption state to triggered */ + set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED); + + /* Trigger the preemption */ + gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl); +} + +static int preempt_init_ring(struct a6xx_gpu *a6xx_gpu, + struct msm_ringbuffer *ring) +{ + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; + struct drm_gem_object *bo =3D NULL; + phys_addr_t ttbr; + u64 iova =3D 0; + void *ptr; + int asid; + + ptr =3D msm_gem_kernel_new(gpu->dev, + PREEMPT_RECORD_SIZE(adreno_gpu), + MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova); + + if (IS_ERR(ptr)) + return PTR_ERR(ptr); + + memset(ptr, 0, PREEMPT_RECORD_SIZE(adreno_gpu)); + + msm_gem_object_set_name(bo, "preempt_record ring%d", ring->id); + + a6xx_gpu->preempt_bo[ring->id] =3D bo; + a6xx_gpu->preempt_iova[ring->id] =3D iova; + a6xx_gpu->preempt[ring->id] =3D ptr; + + struct a6xx_preempt_record *record_ptr =3D ptr; + + ptr =3D msm_gem_kernel_new(gpu->dev, + PREEMPT_SMMU_INFO_SIZE, + MSM_BO_WC | MSM_BO_MAP_PRIV | MSM_BO_GPU_READONLY, + gpu->aspace, &bo, &iova); + + if (IS_ERR(ptr)) + return PTR_ERR(ptr); + + memset(ptr, 0, PREEMPT_SMMU_INFO_SIZE); + + msm_gem_object_set_name(bo, "preempt_smmu_info ring%d", ring->id); + + a6xx_gpu->preempt_smmu_bo[ring->id] =3D bo; + a6xx_gpu->preempt_smmu_iova[ring->id] =3D iova; + a6xx_gpu->preempt_smmu[ring->id] =3D ptr; + + struct a7xx_cp_smmu_info *smmu_info_ptr =3D ptr; + + msm_iommu_pagetable_params(gpu->aspace->mmu, &ttbr, &asid); + + smmu_info_ptr->magic =3D GEN7_CP_SMMU_INFO_MAGIC; + smmu_info_ptr->ttbr0 =3D ttbr; + smmu_info_ptr->asid =3D 0xdecafbad; + smmu_info_ptr->context_idr =3D 0; + + /* Set up the defaults on the preemption record */ + record_ptr->magic =3D A6XX_PREEMPT_RECORD_MAGIC; + record_ptr->info =3D 0; + record_ptr->data =3D 0; + record_ptr->rptr =3D 0; + record_ptr->wptr =3D 0; + record_ptr->cntl =3D MSM_GPU_RB_CNTL_DEFAULT; + record_ptr->rbase =3D ring->iova; + record_ptr->counter =3D 0; + record_ptr->bv_rptr_addr =3D rbmemptr(ring, bv_rptr); + + return 0; +} + +void a6xx_preempt_fini(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int i; + + for (i =3D 0; i < gpu->nr_rings; i++) + msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->aspace); +} + +void a6xx_preempt_init(struct msm_gpu *gpu) +{ + struct adreno_gpu *adreno_gpu =3D to_adreno_gpu(gpu); + struct a6xx_gpu *a6xx_gpu =3D to_a6xx_gpu(adreno_gpu); + int i; + + /* No preemption if we only have one ring */ + if (gpu->nr_rings <=3D 1) + return; + + for (i =3D 0; i < gpu->nr_rings; i++) { + if (preempt_init_ring(a6xx_gpu, gpu->rb[i])) + goto fail; + } + + /* TODO: make this configurable? */ + a6xx_gpu->preempt_level =3D 1; + a6xx_gpu->uses_gmem =3D 1; + a6xx_gpu->skip_save_restore =3D 1; + + timer_setup(&a6xx_gpu->preempt_timer, a6xx_preempt_timer, 0); + + return; +fail: + /* + * On any failure our adventure is over. Clean up and + * set nr_rings to 1 to force preemption off + */ + a6xx_preempt_fini(gpu); + gpu->nr_rings =3D 1; + + DRM_DEV_ERROR(&gpu->pdev->dev, + "preemption init failed, disabling preemption\n"); + + return; +} diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm= _ringbuffer.h index 174f83137a49940ec80b1fbf548e214fa3c32784..d1e49f701c8176e50d2b9a5cca3= 5acee67f75209 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -36,6 +36,7 @@ struct msm_rbmemptrs { =20 volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT]; volatile u64 ttbr0; + volatile u32 context_idr; }; =20 struct msm_cp_state { @@ -101,6 +102,12 @@ struct msm_ringbuffer { */ spinlock_t preempt_lock; =20 + /* + * Whether we skipped writing wptr and it needs to be updated in the + * future when the ring becomes current. + */ + bool restore_wptr; + /** * cur_ctx_seqno: * --=20 2.46.1 From nobody Thu Nov 28 05:32:21 2024 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BDCE1AB51B; Thu, 3 Oct 2024 16:13:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971992; cv=none; b=dRqIlh3OcibwmOlTbZe4kvtuilwLeLapnb0Q+zLQ5ADrxLwTaVDo9MFp5LXGH/ZEw/MqDTNeHCs4M8EgDzFLfRkBjwoIDVgLMftum5G6qf8fcMuc6pSXf+EoNLYlUfkDbHRzpzkpZNhl7QcG4/WRzOgPOd6ilPX6+PqMe9z04yQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727971992; c=relaxed/simple; bh=/wWoq9phTQOtf3DbnY9akGSVrFARm8V71ASGyLN3bu4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NWtn9JHcBdTiX49XwYZXcxe50BN7/JBkk6pEywoIPdpKbxpslUuALlsknt3tQMAixIC2YJetWPs7iL+x+Cy8Rv4pGyYqt1T4Xzh4le0vxWcNGMfU5LqwBV43Nl/z7ayKoFd/3r3T5uywRkTRAIyYQIE5wX0/Rqged2kuO/sRGVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VQPvzEMN; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VQPvzEMN" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-5c896b9b4e0so1628528a12.3; Thu, 03 Oct 2024 09:13:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727971989; x=1728576789; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=U8vL189vTh8iXNA4lYnscfArOlPBvDZ3K4+HECdKLUM=; b=VQPvzEMN75+VUsGSSw5uoLcldyoaOEeWiWQ11GvylLPtvFfrhDSho0NcwOKcGQ/U1Q 5XlLxM4xNUexucbf0SByNNOq1tczCjbkct5UKhukdNen5SnZ9sqseCEE1GdHB5+G7uR0 YMlf2MLoDLP92/EPpJPYZYZIb2hFkON698kWdsSiailVDc5zztJwr6mnd96wCjWHmFo5 a486mYr0nlN4bLFxfBB2cF7KMbunItDA7aSs4KfWgVe8JS7ljbRRwoYcwes0TiRIs249 Q9oq7IRgfbtr2Ky5U/Ct01NPStkOUm3WQTl5tW7deWZ1unNqj9ZbNbsjpuax4QYCd40b uMVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727971989; x=1728576789; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U8vL189vTh8iXNA4lYnscfArOlPBvDZ3K4+HECdKLUM=; b=W4m7Ckay0unK1kFtIQ8MPdjjYAvPl2J/W/k88+El+QdyFAbZeAUqRhOeDv20E3qpVa qeTULLUMH3VrldAvRkMx1POH75SdStgC28UW/Kk2Fw4qWZUPJSFbDRj7OLnxqHj8jXyI iJAizSPdvrqllXiZXZ2D6Tjd0NeuBVu90cRpkcxJrNMXqGtW62Mkr+y/AS1iUSFRdIiW t2umqFHplUq/GVI46PqmSk3pleLsHDPfj1OBZ9os+6YqcRGH2PQYV3PHFjpTaWw2bMQs gNyKVHfACdwmMYzfNWiggBOS3kxD6eQXo8oDvtgaMqeBHrUAUYzuV9IqS2YQwexMPyiI wpOA== X-Forwarded-Encrypted: i=1; AJvYcCWY1ZtrWbNf/QOdsQ+5Vk7n8U0HGKEnIe1lmxIDmE6PVJZdPm1iG2bfZIHtYtLW7ZvNkGv2EBY/Db+nvX17@vger.kernel.org, AJvYcCXfTax0pmV9pBdharOImKeqb+y5WaKdh4bbHeFy77WY/GBbrVMuQXP6gpPa5RMmNzuA2vbIw2qc6kc=@vger.kernel.org X-Gm-Message-State: AOJu0YzU/96bnxb+c/2mzSAemkc1BlAkcrY+Epmb25e5iD9ufF0uKwJW H0ZKuxSAbmBI6CPW6j+E8IEJ1oMPN+xneFMthYaAoJezHLRMVhjw X-Google-Smtp-Source: AGHT+IGg/TDD/UYldRFd8ivNHm2MIlLo9pvXM/gzWhUsgFDb2pAQT6s+UHg74nIw8fWIUyKnZdcvcA== X-Received: by 2002:a17:907:97c7:b0:a8b:6ee7:ba2c with SMTP id a640c23a62f3a-a98f824db49mr738159766b.16.1727971989285; Thu, 03 Oct 2024 09:13:09 -0700 (PDT) Received: from [192.168.1.17] (host-79-12-161-203.retail.telecomitalia.it. [79.12.161.203]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99103b314asm102382366b.103.2024.10.03.09.13.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 09:13:08 -0700 (PDT) From: Antonino Maniscalco Date: Thu, 03 Oct 2024 18:12:56 +0200 Subject: [PATCH v8 07/12] drm/msm/a6xx: Sync relevant adreno_pm4.xml changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-preemption-a750-t-v8-7-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727971975; l=4077; i=antomani103@gmail.com; s=20240815; h=from:subject:message-id; bh=/wWoq9phTQOtf3DbnY9akGSVrFARm8V71ASGyLN3bu4=; b=5854X32F856DjAwSnBjK85C7m0P/bTPK8DLJl9ecjF/Dxr1LQ433uDvWULajpwG9UmztXaDfi p9alhQFBtD8DhF7RkhdiORt79G5Rllz6wp2f91q4f5ZFdXMksUrDJOk X-Developer-Key: i=antomani103@gmail.com; a=ed25519; pk=0zicFb38tVla+iHRo4kWpOMsmtUrpGBEa7LkFF81lyY= In mesa CP_SET_CTXSWITCH_IB is renamed to CP_SET_AMBLE and some other names are changed to match KGSL. Import those changes. The changes have not been merged yet in mesa but are necessary for this series. Tested-by: Rob Clark Tested-by: Neil Armstrong # on SM8650-QRD Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Neil Armstrong # on SM8450-HDK Signed-off-by: Antonino Maniscalco --- .../gpu/drm/msm/registers/adreno/adreno_pm4.xml | 39 ++++++++++--------= ---- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/= gpu/drm/msm/registers/adreno/adreno_pm4.xml index cab01af55d22268ccf88f1a5032b6081d8e4e475..55a35182858ccac3292849faaf1= 2727257e053c7 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -581,8 +581,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fr= eedreno/ rules-fd.xsd"> and forcibly switch to the indicated context. - - + =20