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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-dt-binding-display-msm-merge-v1-3-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4802; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=M70OZAtivNRGOLcaQJi4OpyfB+gup8mxOQUxCSAPC3I=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJhOPfdZ5V1aYsZIliza2UvaapHm8tgeUCrw olfeMvDH1qJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYQAKCRDBN2bmhouD 18DeEACG12eR34P9hg1YN3zIF9k5PLLvau56aXFJnH9mm5fk6+FQcDOphwIqZo6K7LJpBGMYCdq /952tDwVpCfoegkyc9mCXLl5K4YNM+MdpdqF430dOaYnmvN2XcCGy+1pxU7EbFB0Q1ke1UofYhV hRYe+1PhZ7kJwKUX99uN+r1NhIIoZ+wwO3KgS+I0fMSsgpCknJ4SI6T9ztvCDd4e1T5CwS4GzdQ Dhw2TjTKvk9pHKMwE0avmYZWIva7YsO7do/bVJvSmbR6F7DEvT53O6rforR0Tuzd7WAGhV095eT v5CgBQegilINyggMwZWWRzL/JTcY/O4fU84k0kywgc/wm2/CkeYOD9ZbqHnFp7/lqgvhjdlRRbu UcUA3FFdlzZd2KkABBwfYeeXotA0cARexYYVOQ0NMYWfkaHR+fnkBp2KWCpzqogzbLIXQetopGX GXdSEHumIM5hVna/wAjh5mV+PH1WzIWGaeODimGNt2d5EJ1cV4KMq1/dKam13yaCHbPwi+76wwo KTUk2bQzqA/xOpXb/lOUiP7nc1Vh6ahSqb+RvmO5ZpfL+cXVmZKnI0YVixDURlStmwh4ThjwprW 8KtdH47jcqHqjosUBR0Cqrw+1ZL/ndaoTW254d3CtefHenxJla9+zt2ivWC9Uu/33V2XPT3aZtI c0VZ2PozLhr9FXw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8350, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 1 + .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 -----------------= ---- 2 files changed, 1 insertion(+), 120 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index fab7a3b9a20e..3d69a573b450 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,sc7280-dpu - qcom,sc8280xp-dpu + - qcom,sm8350-dpu =20 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml deleted file mode 100644 index 96ef2d9c3512..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml +++ /dev/null @@ -1,120 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8350 Display DPU - -maintainers: - - Robert Foss - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8350-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible =3D "qcom,sm8350-dpu"; - reg =3D <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names =3D "mdp", "vbif"; - - clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names =3D "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates =3D <19200000>; - - operating-points-v2 =3D <&mdp_opp_table>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent =3D <&mdss>; - interrupts =3D <0>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - dpu_intf1_out: endpoint { - remote-endpoint =3D <&dsi0_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-200000000 { - opp-hz =3D /bits/ 64 <200000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz =3D /bits/ 64 <300000000>; - required-opps =3D <&rpmhpd_opp_svs>; - }; - - opp-345000000 { - opp-hz =3D /bits/ 64 <345000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - - opp-460000000 { - opp-hz =3D /bits/ 64 <460000000>; - required-opps =3D <&rpmhpd_opp_nom>; - }; - }; - }; -... --=20 2.43.0