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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-dt-binding-display-msm-merge-v1-1-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5123; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=I5gkxxh+/Kn7rSd5JE9ZVp0kaBODXFkfmbSKaf1DYHc=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJgpCz5PczWvVC4MOIIKhlQ6KLXaZenlrYJI drKKpzFNpOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYAAKCRDBN2bmhouD 10fcD/4547yeLqXfKNqq/CjO1tHYFMiWiDA6JArchwq/G4NWZyVC+Xq8hEdf7u3a7ycQb0rs3cL 0huBzw5X9Ufag9yLBEM3iS8noXXPgJuWSh/WqX8DTWpOvg1E3Bu8+w55lf/zy8GuUqGF4h1o7W0 qOmxHVECt5X4Ny+VxP5b6kxsezf4wUbVipwfW45ykmdqijK6D2qgrfF2CZMB+/aOZkVnUdavGtJ gjMIYp5Pf/r9uGsCitHgUB0rULcJEippVF59cFhZdGD9ESFbSuuyS/CdaFmO9bmN3mPq/7UpD+i kA8s7BwUumRlLjkhjAnSfC1+sg6vJln4nvp84XpySm80dTf6rRC8D3zfBlk2leVrq+eKr/4r8bF 7x/I6rPiTHgPRHpsiwiVyR9BpzxnmvjQeCjlCHlGxW3Db+O3bbP6xvezxKYnHd6DTWm9ydIlNrU UpONUCnuUvGy/SGhA6la9MlpRTcPlVCywjDAWVXW+U9ninUzNQqctGNSigCb9sgcp/oQEhgdrbG XShEwlMGR1T1Co9HkghLDyQVMIqNGSc7htte0RjHVWqQadeLFyE/O+o2yA98PTrhN/PKR0A8Zj3 DNK0MrBAfS0fTQlkz0RNU2LrYSvNF51+fkpAQexMN5NMDH6zif5WdABJIKysAlQllhnMYh/63wo KmkfVBAKxFOlbzA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SC8280XP, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 5 +- .../bindings/display/msm/qcom,sc8280xp-dpu.yaml | 122 -----------------= ---- 2 files changed, 4 insertions(+), 123 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index b0fbe86219d1..fab7a3b9a20e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -7,13 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU on SC7280 =20 maintainers: + - Bjorn Andersson - Krishna Manikandan =20 $ref: /schemas/display/msm/dpu-common.yaml# =20 properties: compatible: - const: qcom,sc7280-dpu + enum: + - qcom,sc7280-dpu + - qcom,sc8280xp-dpu =20 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dp= u.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.ya= ml deleted file mode 100644 index d19e3bec4600..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml +++ /dev/null @@ -1,122 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SC8280XP Display Processing Unit - -maintainers: - - Bjorn Andersson - -description: - Device tree bindings for SC8280XP Display Processing Unit. - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sc8280xp-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible =3D "qcom,sc8280xp-dpu"; - reg =3D <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names =3D "mdp", "vbif"; - - clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc0 DISP_CC_MDSS_AHB_CLK>, - <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc0 DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; - clock-names =3D "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates =3D <460000000>, - <19200000>; - - operating-points-v2 =3D <&mdp_opp_table>; - power-domains =3D <&rpmhpd SC8280XP_MMCX>; - - interrupt-parent =3D <&mdss0>; - interrupts =3D <0>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - endpoint { - remote-endpoint =3D <&mdss0_dp0_in>; - }; - }; - - port@4 { - reg =3D <4>; - endpoint { - remote-endpoint =3D <&mdss0_dp1_in>; - }; - }; - - port@5 { - reg =3D <5>; - endpoint { - remote-endpoint =3D <&mdss0_dp3_in>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SM8150 and SM8250, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sm8150-dpu.yaml | 4 +- .../bindings/display/msm/qcom,sm8250-dpu.yaml | 99 ------------------= ---- 2 files changed, 3 insertions(+), 100 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml index 13146b3f053c..a88d22f30a60 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# =20 properties: compatible: - const: qcom,sm8150-dpu + enum: + - qcom,sm8150-dpu + - qcom,sm8250-dpu =20 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml deleted file mode 100644 index ffa5047e901f..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8250 Display DPU - -maintainers: - - Dmitry Baryshkov - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8250-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display hf axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible =3D "qcom,sm8250-dpu"; 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Thu, 03 Oct 2024 01:14:35 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:35 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:20 +0200 Subject: [PATCH 3/5] dt-bindings: display/msm: merge SM8350 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-dt-binding-display-msm-merge-v1-3-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8350, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 1 + .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 -----------------= ---- 2 files changed, 1 insertion(+), 120 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index fab7a3b9a20e..3d69a573b450 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,sc7280-dpu - qcom,sc8280xp-dpu + - qcom,sm8350-dpu =20 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml deleted file mode 100644 index 96ef2d9c3512..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml +++ /dev/null @@ -1,120 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8350 Display DPU - -maintainers: - - Robert Foss - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8350-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible =3D "qcom,sm8350-dpu"; - reg =3D <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names =3D "mdp", "vbif"; - - clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names =3D "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates =3D <19200000>; - - operating-points-v2 =3D <&mdp_opp_table>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent =3D <&mdss>; - interrupts =3D <0>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - dpu_intf1_out: endpoint { - remote-endpoint =3D <&dsi0_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-200000000 { - opp-hz =3D /bits/ 64 <200000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz =3D /bits/ 64 <300000000>; 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Thu, 03 Oct 2024 01:14:36 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:21 +0200 Subject: [PATCH 4/5] dt-bindings: display/msm: merge SM8450 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-dt-binding-display-msm-merge-v1-4-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8450, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 2 + .../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 -----------------= ---- 2 files changed, 2 insertions(+), 139 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 3d69a573b450..750230839fc9 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -8,6 +8,7 @@ title: Qualcomm Display DPU on SC7280 =20 maintainers: - Bjorn Andersson + - Dmitry Baryshkov - Krishna Manikandan =20 $ref: /schemas/display/msm/dpu-common.yaml# @@ -18,6 +19,7 @@ properties: - qcom,sc7280-dpu - qcom,sc8280xp-dpu - qcom,sm8350-dpu + - qcom,sm8450-dpu =20 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml deleted file mode 100644 index 2a5d3daed0e1..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml +++ /dev/null @@ -1,139 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8450 Display DPU - -maintainers: - - Dmitry Baryshkov - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8450-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi - - description: Display sf axi - - description: Display ahb - - description: Display lut - - description: Display core - - description: Display vsync - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible =3D "qcom,sm8450-dpu"; - reg =3D <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names =3D "mdp", "vbif"; - - clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names =3D "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates =3D <19200000>; - - operating-points-v2 =3D <&mdp_opp_table>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent =3D <&mdss>; - interrupts =3D <0>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - dpu_intf1_out: endpoint { - remote-endpoint =3D <&dsi0_in>; - }; - }; - - port@1 { - reg =3D <1>; - dpu_intf2_out: endpoint { - remote-endpoint =3D <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-172000000{ - opp-hz =3D /bits/ 64 <172000000>; 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Thu, 03 Oct 2024 01:14:38 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:22 +0200 Subject: [PATCH 5/5] dt-bindings: display/msm: merge SM8550 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241003-dt-binding-display-msm-merge-v1-5-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8550, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 2 + .../bindings/display/msm/qcom,sm8550-dpu.yaml | 133 -----------------= ---- 2 files changed, 2 insertions(+), 133 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 750230839fc9..6902795b4e2c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -8,6 +8,7 @@ title: Qualcomm Display DPU on SC7280 =20 maintainers: - Bjorn Andersson + - Neil Armstrong - Dmitry Baryshkov - Krishna Manikandan =20 @@ -20,6 +21,7 @@ properties: - qcom,sc8280xp-dpu - qcom,sm8350-dpu - qcom,sm8450-dpu + - qcom,sm8550-dpu =20 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml deleted file mode 100644 index 16a541fca66f..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml +++ /dev/null @@ -1,133 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8550 Display DPU - -maintainers: - - Neil Armstrong - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8550-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display AHB - - description: Display hf axi - - description: Display MDSS ahb - - description: Display lut - - description: Display core - - description: Display vsync - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - - display-controller@ae01000 { - compatible =3D "qcom,sm8550-dpu"; - reg =3D <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names =3D "mdp", "vbif"; - - clocks =3D <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names =3D "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates =3D <19200000>; - - operating-points-v2 =3D <&mdp_opp_table>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent =3D <&mdss>; - interrupts =3D <0>; - - ports { - #address-cells =3D <1>; - #size-cells =3D <0>; - - port@0 { - reg =3D <0>; - dpu_intf1_out: endpoint { - remote-endpoint =3D <&dsi0_in>; - }; - }; - - port@1 { - reg =3D <1>; - dpu_intf2_out: endpoint { - remote-endpoint =3D <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible =3D "operating-points-v2"; - - opp-200000000 { - opp-hz =3D /bits/ 64 <200000000>; - required-opps =3D <&rpmhpd_opp_low_svs>; - }; - - opp-325000000 { - opp-hz =3D /bits/ 64 <325000000>; - required-opps =3D <&rpmhpd_opp_svs>; - }; - - opp-375000000 { - opp-hz =3D /bits/ 64 <375000000>; - required-opps =3D <&rpmhpd_opp_svs_l1>; - }; - - opp-514000000 { - opp-hz =3D /bits/ 64 <514000000>; - required-opps =3D <&rpmhpd_opp_nom>; - }; - }; - }; -... --=20 2.43.0