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AJvYcCWl8DicBXC0jVgomug4KXG+jpUwONabYnkZQM6tQxCeabhAwOyxZ660YSDb34KY1KvKo4MxJGaHL/wB51U=@vger.kernel.org X-Gm-Message-State: AOJu0Yz9sWhC23jhZ3/83D+hBrG2y0A0+pwRAhFfbWNrPxo7+nABYf8G taa28A+b5OY2+kOAWmX6Rmldi1y/ot52ZDEHcSYN7eiyAZuVCurHa5GWv3qEUJk= X-Google-Smtp-Source: AGHT+IFwyFuXYth7A8vslCHMAnUaIkp4wEUm+Zkv+c4fkaTohWk+qBC9lfK+MVzuhuapcRpBsdVkkA== X-Received: by 2002:adf:eac9:0:b0:374:b6f3:728d with SMTP id ffacd0b85a97d-37cfba07ac2mr2755315f8f.46.1727900176783; Wed, 02 Oct 2024 13:16:16 -0700 (PDT) Received: from gpeter-l.lan ([145.224.66.77]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd564d2e8sm14850600f8f.18.2024.10.02.13.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 13:16:16 -0700 (PDT) From: Peter Griffin To: vkoul@kernel.org, kishon@kernel.org, krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Peter Griffin Subject: [PATCH 3/3] phy: samsung: gs101-ufs: Add hibern8 enter and exit specific tuning values Date: Wed, 2 Oct 2024 21:15:55 +0100 Message-ID: <20241002201555.3332138-4-peter.griffin@linaro.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002201555.3332138-1-peter.griffin@linaro.org> References: <20241002201555.3332138-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the gs101 specific phy calibration values that need to be programmed when entering and exiting hibern8 state. Signed-off-by: Peter Griffin --- drivers/phy/samsung/phy-gs101-ufs.c | 31 ++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/phy/samsung/phy-gs101-ufs.c b/drivers/phy/samsung/phy-= gs101-ufs.c index 17b798da5b57..5363d8be6c76 100644 --- a/drivers/phy/samsung/phy-gs101-ufs.c +++ b/drivers/phy/samsung/phy-gs101-ufs.c @@ -108,10 +108,35 @@ static const struct samsung_ufs_phy_cfg tensor_gs101_= post_pwr_hs_config[] =3D { END_UFS_PHY_CFG, }; =20 +static const struct samsung_ufs_phy_cfg tensor_gs101_post_h8_enter[] =3D { + PHY_TRSV_REG_CFG_GS101(0x262, 0x08, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_GS101(0x265, 0x0A, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x1, 0x8, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x0, 0x86, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_HS_ANY), + END_UFS_PHY_CFG, +}; + +static const struct samsung_ufs_phy_cfg tensor_gs101_pre_h8_exit[] =3D { + PHY_COMN_REG_CFG(0x0, 0xC6, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x1, 0x0C, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_GS101(0x262, 0x00, PWR_MODE_ANY), + PHY_TRSV_REG_CFG_GS101(0x265, 0x00, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x8, 0xE0, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG_GS101(0x222, 0x18, PWR_MODE_HS_ANY), + END_UFS_PHY_CFG, +}; + + static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG= _MAX] =3D { - [CFG_PRE_INIT] =3D tensor_gs101_pre_init_cfg, - [CFG_PRE_PWR_HS] =3D tensor_gs101_pre_pwr_hs_config, - [CFG_POST_PWR_HS] =3D tensor_gs101_post_pwr_hs_config, + [CFG_PRE_INIT] =3D tensor_gs101_pre_init_cfg, + [CFG_PRE_PWR_HS] =3D tensor_gs101_pre_pwr_hs_config, + [CFG_POST_PWR_HS] =3D tensor_gs101_post_pwr_hs_config, + [CFG_POST_HIBERN8_ENTER] =3D tensor_gs101_post_h8_enter, + [CFG_PRE_HIBERN8_EXIT] =3D tensor_gs101_pre_h8_exit, }; =20 static const char * const tensor_gs101_ufs_phy_clks[] =3D { --=20 2.46.1.824.gd892dcdcdd-goog