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Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index bf15ac9901da..10195a4e4e9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -23,6 +23,11 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + gce0 =3D &gce0; + gce1 =3D &gce1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 10:50:32 2024 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB21C20012E for ; Wed, 2 Oct 2024 11:46:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; 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Wed, 02 Oct 2024 04:46:53 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 2/9] arm64: dts: mediatek: mt8188: Add PCIe nodes Date: Wed, 2 Oct 2024 19:41:42 +0800 Message-ID: <20241002114614.847553-3-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002114614.847553-1-fshao@chromium.org> References: <20241002114614.847553-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PCIe node and the associated PHY node. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 10195a4e4e9d..9431f3c5c228 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1763,6 +1763,53 @@ xhci0: usb@112b0000 { status =3D "disabled"; }; =20 + pcie: pcie@112f0000 { + compatible =3D "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; + reg =3D <0 0x112f0000 0 0x2000>; + reg-names =3D "pcie-mac"; + ranges =3D <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; + bus-range =3D <0 0xff>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", "tl_32k", + "peri_26m", "peri_mem"; + + #interrupt-cells =3D <1>; + interrupts =3D ; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask =3D <0 0 0 7>; + + iommu-map =3D <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; + iommu-map-mask =3D <0>; + + phys =3D <&pcieport PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + + power-domains =3D <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; + + resets =3D <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; + reset-names =3D "mac"; + + status =3D "disabled"; + + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + nor_flash: spi@1132c000 { compatible =3D "mediatek,mt8188-nor", "mediatek,mt8186-nor"; reg =3D <0 0x1132c000 0 0x1000>; @@ -1775,6 +1822,21 @@ nor_flash: spi@1132c000 { status =3D "disabled"; }; =20 + pciephy: t-phy@11c20700 { + compatible =3D "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; 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charset="utf-8" Add MIPI DSI and the associated PHY node to support DSI panels. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 9431f3c5c228..ff639418bebe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1837,6 +1837,16 @@ pcieport: pcie-phy@0 { }; }; =20 + mipi_tx_phy: dsi-phy@11c80000 { + compatible =3D "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg =3D <0 0x11c80000 0 0x1000>; + clocks =3D <&clk26m>; + clock-output-names =3D "mipi_tx0_pll"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + i2c1: i2c@11e00000 { compatible =3D "mediatek,mt8188-i2c"; reg =3D <0 0x11e00000 0 0x1000>, @@ -2222,10 +2232,26 @@ larb19: smi@1a010000 { mediatek,smi =3D <&vdo_smi_common>; }; =20 + disp_dsi: dsi@1c008000 { + compatible =3D "mediatek,mt8188-dsi"; + reg =3D <0 0x1c008000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DSI0>, + <&vdosys0 CLK_VDO0_DSI0_DSI>, + <&mipi_tx_phy>; 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Wed, 02 Oct 2024 04:46:58 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 4/9] arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes Date: Wed, 2 Oct 2024 19:41:44 +0800 Message-ID: <20241002114614.847553-5-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002114614.847553-1-fshao@chromium.org> References: <20241002114614.847553-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index ff639418bebe..dbea562ee8ba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2181,6 +2181,64 @@ ccusys: clock-controller@17200000 { #clock-cells =3D <1>; }; =20 + video_decoder: video-decoder@18000000 { + compatible =3D "mediatek,mt8188-vcodec-dec"; + reg =3D <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges =3D <0 0 0 0x18000000 0 0x26000>; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells =3D <2>; + #size-cells =3D <2>; + mediatek,scp =3D <&scp>; + + video-codec@10000 { + compatible =3D "mediatek,mtk-vcodec-lat"; + reg =3D <0 0x10000 0 0x800>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible =3D "mediatek,mtk-vcodec-core"; + reg =3D <0 0x25000 0 0x1000>; + assigned-clocks =3D <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks =3D <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names =3D "sel", "vdec", "lat", "top"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + larb23: smi@1800d000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1800d000 0 0x1000>; @@ -2232,6 +2290,31 @@ larb19: smi@1a010000 { mediatek,smi =3D <&vdo_smi_common>; }; =20 + video_encoder: video-encoder@1a020000 { + compatible =3D "mediatek,mt8188-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks =3D <&vencsys CLK_VENC1_VENC>; + clock-names =3D "venc_sel"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; 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charset="utf-8" Add JPEG encoder and decoder nodes for hardware-accelerated JPEG decoding and encoding support. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 29 ++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index dbea562ee8ba..c1b057166aa3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2315,6 +2315,35 @@ video_encoder: video-encoder@1a020000 { mediatek,scp =3D <&scp>; }; =20 + jpeg_encoder: jpeg-encoder@1a030000 { + compatible =3D "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; + reg =3D <0 0x1a030000 0 0x10000>; + clocks =3D <&vencsys CLK_VENC1_JPGENC>; + clock-names =3D "jpgenc"; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, + <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, + <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, + <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VENC>; + }; + + jpeg_decoder: jpeg-decoder@1a040000 { + compatible =3D "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; 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charset="utf-8" Add the vdosys0 display nodes to support the internal display pipeline. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index c1b057166aa3..79e007b619b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ / { aliases { gce0 =3D &gce0; gce1 =3D &gce1; + mutex0 =3D &mutex0; }; =20 cpus { @@ -2344,6 +2345,71 @@ jpeg_decoder: jpeg-decoder@1a040000 { power-domains =3D <&spm MT8188_POWER_DOMAIN_VDEC0>; }; =20 + ovl0: ovl@1c000000 { + compatible =3D "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg =3D <0 0x1c000000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible =3D "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg =3D <0 0x1c002000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible =3D "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x1c003000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_COLOR0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible =3D "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccor= r"; + reg =3D <0 0x1c004000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_CCORR0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible =3D "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1c005000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_AAL0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible =3D "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamm= a"; + reg =3D <0 0x1c006000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible =3D "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x1c007000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_DITHER0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + disp_dsi: dsi@1c008000 { compatible =3D "mediatek,mt8188-dsi"; reg =3D <0 0x1c008000 0 0x1000>; @@ -2359,6 +2425,26 @@ disp_dsi: dsi@1c008000 { status =3D "disabled"; }; =20 + mutex0: mutex@1c016000 { + compatible =3D "mediatek,mt8188-disp-mutex"; + reg =3D <0 0x1c016000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; + mediatek,gce-events =3D ; + }; + + postmask0: postmask@1c01a000 { + compatible =3D "mediatek,mt8188-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1c01a000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + }; + vdosys0: syscon@1c01d000 { compatible =3D "mediatek,mt8188-vdosys0", "syscon"; reg =3D <0 0x1c01d000 0 0x1000>; --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 10:50:32 2024 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00489205E38 for ; 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Wed, 02 Oct 2024 04:47:07 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b2652baefsm9639627b3a.180.2024.10.02.04.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 04:47:06 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 7/9] arm64: dts: mediatek: mt8188: Add display nodes for vdosys1 Date: Wed, 2 Oct 2024 19:41:47 +0800 Message-ID: <20241002114614.847553-8-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002114614.847553-1-fshao@chromium.org> References: <20241002114614.847553-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the vdosys1 display nodes to support the external display pipeline. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 298 +++++++++++++++++++++++ 1 file changed, 298 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 79e007b619b7..5410469e5fd8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -24,9 +24,32 @@ / { #size-cells =3D <2>; =20 aliases { + ethdr0 =3D ðdr0; gce0 =3D &gce0; gce1 =3D &gce1; + merge0 =3D &merge0; + merge1 =3D &merge1; + merge2 =3D &merge2; + merge3 =3D &merge3; + merge4 =3D &merge4; mutex0 =3D &mutex0; + mutex1 =3D &mutex1; + padding0 =3D &padding0; + padding1 =3D &padding1; + padding2 =3D &padding2; + padding3 =3D &padding3; + padding4 =3D &padding4; + padding5 =3D &padding5; + padding6 =3D &padding6; + padding7 =3D &padding7; + vdo1-rdma0 =3D &vdo1_rdma0; + vdo1-rdma1 =3D &vdo1_rdma1; + vdo1-rdma2 =3D &vdo1_rdma2; + vdo1-rdma3 =3D &vdo1_rdma3; + vdo1-rdma4 =3D &vdo1_rdma4; + vdo1-rdma5 =3D &vdo1_rdma5; + vdo1-rdma6 =3D &vdo1_rdma6; + vdo1-rdma7 =3D &vdo1_rdma7; }; =20 cpus { @@ -2505,6 +2528,16 @@ vdosys1: syscon@1c100000 { mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0 0x1000>; }; =20 + mutex1: mutex@1c101000 { + compatible =3D "mediatek,mt8188-disp-mutex"; + reg =3D <0 0x1c101000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_DISP_MUTEX>; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; + mediatek,gce-events =3D ; + }; + larb2: smi@1c102000 { compatible =3D "mediatek,mt8188-smi-larb"; reg =3D <0 0x1c102000 0 0x1000>; @@ -2526,5 +2559,270 @@ larb3: smi@1c103000 { mediatek,larb-id =3D ; mediatek,smi =3D <&vpp_smi_common>; }; + + vdo1_rdma0: rdma@1c104000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c104000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA0>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: rdma@1c105000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c105000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA1>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: rdma@1c106000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c106000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA2>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: rdma@1c107000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c107000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA3>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: rdma@1c108000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c108000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA4>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: rdma@1c109000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c109000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA5>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: rdma@1c10a000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c10a000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA6>; + interrupts =3D ; + iommus =3D <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: rdma@1c10b000 { + compatible =3D "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg =3D <0 0x1c10b000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_MDP_RDMA7>; + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells =3D <1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge0: merge@1c10c000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10c000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute; + }; + + merge1: merge@1c10d000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute; + }; + + merge2: merge@1c10e000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10e000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute; + }; + + merge3: merge@1c10f000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c10f000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute; + }; + + merge4: merge@1c110000 { + compatible =3D "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merg= e"; + reg =3D <0 0x1c110000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names =3D "merge", "merge_async"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en; + }; + + ethdr0: ethdr@1c114000 { + compatible =3D "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethd= r"; + reg =3D <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names =3D "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + + clocks =3D <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names =3D "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; + + interrupts =3D ; + iommus =3D <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, + <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets =3D <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; + + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + }; + + padding0: padding@1c11d000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11d000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING0>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + + padding1: padding@1c11e000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11e000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING1>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; + }; + + padding2: padding@1c11f000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c11f000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING2>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; + }; + + padding3: padding@1c120000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c120000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING3>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; + }; + + padding4: padding@1c121000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c121000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING4>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; + }; + + padding5: padding@1c122000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c122000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING5>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; + }; + + padding6: padding@1c123000 { + compatible =3D "mediatek,mt8188-disp-padding"; + reg =3D <0 0x1c123000 0 0x1000>; + clocks =3D <&vdosys1 CLK_VDO1_PADDING6>; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; + }; + + padding7: padding@1c124000 { + compatible =3D "mediatek,mt8188-disp-padding"; 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charset="utf-8" Add the primary and secondary dp-intf nodes. These DP-INTF hardware IPs are the sink of the vdosys0 and vdosys1 display pipelines for the internal and external displays, respectively. Individual board device tree should enable the nodes and connect input and output ports as needed. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 5410469e5fd8..943333d2567f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -24,6 +24,8 @@ / { #size-cells =3D <2>; =20 aliases { + dp-intf0 =3D &dp_intf0; + dp-intf1 =3D &dp_intf1; ethdr0 =3D ðdr0; gce0 =3D &gce0; gce1 =3D &gce1; @@ -2448,6 +2450,18 @@ disp_dsi: dsi@1c008000 { status =3D "disabled"; }; =20 + dp_intf0: dp-intf@1c015000 { + compatible =3D "mediatek,mt8188-dp-intf"; + reg =3D <0 0x1c015000 0 0x1000>; + clocks =3D <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&vdosys0 CLK_VDO0_DP_INTF0>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names =3D "pixel", "engine", "pll"; + interrupts =3D ; + power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + status =3D "disabled"; + }; + mutex0: mutex@1c016000 { compatible =3D "mediatek,mt8188-disp-mutex"; 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charset="utf-8" Add edp-tx and dp-tx nodes for the Embedded DisplayPort (eDP) and DisplayPort ports to connect to DP-INTF ports and panels, and add the efuse cell for the DP calibration data. Individual board device tree should enable the nodes and connect input and output ports as needed. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 943333d2567f..67c539e5d146 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2004,6 +2004,10 @@ efuse: efuse@11f20000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + dp_calib_data: dp-calib@1a0 { + reg =3D <0x1a0 0xc>; + }; + lvts_efuse_data1: lvts1-calib@1ac { reg =3D <0x1ac 0x40>; }; @@ -2850,5 +2854,27 @@ padding7: padding@1c124000 { power-domains =3D <&spm MT8188_POWER_DOMAIN_VDOSYS1>; mediatek,gce-client-reg =3D <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; + + edp_tx: edp-tx@1c500000 { + compatible =3D "mediatek,mt8188-edp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + interrupts =3D ; + nvmem-cells =3D <&dp_calib_data>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8188_POWER_DOMAIN_EDP_TX>; + max-linkrate-mhz =3D <8100>; + status =3D "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible =3D "mediatek,mt8188-dp-tx"; + reg =3D <0 0x1c600000 0 0x8000>; + interrupts =3D ; + nvmem-cells =3D <&dp_calib_data>; + nvmem-cell-names =3D "dp_calibration_data"; + power-domains =3D <&spm MT8188_POWER_DOMAIN_DP_TX>; + max-linkrate-mhz =3D <5400>; + status =3D "disabled"; + }; }; }; --=20 2.46.1.824.gd892dcdcdd-goog