From nobody Thu Nov 28 10:53:17 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 723292F44; Wed, 2 Oct 2024 02:21:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727835716; cv=none; b=IA2Du6pIVvwaCkaRpSMeG1QUaEEMGCGBpj4CWOxouuHe0xE5EK3qunovnoSpGurnlnGtnxuLesFd3eofmCG7ssfyQbY1Kj0HPa8bvIn3OkwRdkUJ+wonjXw4rnFtWbOYUM4Ckw2GBP+xVnZidpK9uyx1bDc5AytYWpvPbE+smOw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727835716; c=relaxed/simple; bh=p0xljmztD31PYSFLyL5vp1xd2x8LHHqqamlWrvyrZ3g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LD/wrOJhGdId3LcHxZit7lpVz0yY2+YKmDzjtBmzKJ0a0sNghZqe7XIhqDYYYGEt6wDl0eU8hTivgkZKLKABG6EBt3kDFfFk+3+Yi2Mt67zBQcBnRTtCFLA8dIcuoBjdgFTWB0zKX3FjWm+F1zRF6chxTC6v13BAuSoQPCr71ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=ICfCR4S1; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ICfCR4S1" X-UUID: 14148b34806511ef8b96093e013ec31c-20241002 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=sx3Vdwociw+7bgWqHeh3LpMurxRj0XhtssaWVj1YGYE=; b=ICfCR4S1l6K7avnpTP+noOXhCmb42nmsI/n7oizxGtdB9t5sEGKZkyGWaDhrKiFhM6L7h2njhjKjERMjCb2sAU+0escZDPNfXmWqo3m+oq+rlBBqzOXyLsQlBwOvKt5l2YJdcJn5ZUu5PdH6IU1JS07179V7Ya6Uz79K1Hilbuc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:f3575a45-8ee4-4d2d-866d-674f0e5f362f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:023888b6-067a-45ef-ad40-860f1548309a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 14148b34806511ef8b96093e013ec31c-20241002 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1080636259; Wed, 02 Oct 2024 10:21:48 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 2 Oct 2024 10:21:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 2 Oct 2024 10:21:46 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Pablo Sun Subject: [PATCH v3 1/6] arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain Date: Wed, 2 Oct 2024 10:21:33 +0800 Message-ID: <20241002022138.29241-2-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241002022138.29241-1-pablo.sun@mediatek.com> References: <20241002022138.29241-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.548300-8.000000 X-TMASE-MatchedRID: PcZ0mOXO/jwPRVepDWIjx/fLKp/JCt7h6SXuwUgGH0iyrCkM9r1bWnTv v/bTZRlobaFo1bdWCGaQJkPYvdXnnwzyMxeMEX6wFEUknJ/kEl7dB/CxWTRRu+rAZ8KTspSzetP JfHqWaH9JLwBSa8cIhAW80jAWz86QWJqqfG38YMr34hqv8Qa5Lzd2iAQV2uozvjeXXjV9ouogrK mwTJoL/Ns19EgxHqqiF0aD5ljt43pMcHZD6gqu7wxMjfifIXfowkvVoA11Twp+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.548300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2E5731F8DCEDE1326F76D329AE748F85559A3ABF2C5A0CA0200AF644AB264D732000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock index "CLK_APMIXED_MFGPLL" belongs to the "apmixedsys" provider, so fix the index. In addition, add a "mfg1" label so following commits could set domain-supply for MFG1 power domain. Fixes: eaf73e4224a3 ("arm64: dts: mediatek: mt8188: Add support for SoC pow= er domains") Signed-off-by: Pablo Sun Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index cd27966d2e3c..02a5bb4dbd1f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -956,9 +956,9 @@ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { #size-cells =3D <0>; #power-domain-cells =3D <1>; =20 - power-domain@MT8188_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { reg =3D ; - clocks =3D <&topckgen CLK_APMIXED_MFGPLL>, + clocks =3D <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; clock-names =3D "mfg", "alt"; mediatek,infracfg =3D <&infracfg_ao>; --=20 2.45.2 From nobody Thu Nov 28 10:53:17 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E51D23BB; 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Wed, 02 Oct 2024 10:21:50 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 2 Oct 2024 10:21:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 2 Oct 2024 10:21:49 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Pablo Sun Subject: [PATCH v3 2/6] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp Date: Wed, 2 Oct 2024 10:21:34 +0800 Message-ID: <20241002022138.29241-3-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241002022138.29241-1-pablo.sun@mediatek.com> References: <20241002022138.29241-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when setting mfgpll clock rate. If we keep the univpll parents from mfg_core_tmp, when setting GPU frequency to 390000000, the common clock framework would switch the parent to univpll, instead of setting mfgpll to 390000000: mfgpll 0 0 0 949999756 univpll 2 2 0 2340000000 univpll_d6 1 1 0 390000000 top_mfg_core_tmp 1 1 0 390000000 mfg_ck_fast_ref 1 1 0 390000000 mfgcfg_bg3d 1 1 0 390000000 This results in failures when subsequent devfreq operations need to switch to other frequencies. So remove univpll from the parent list. This solution is taken from commit 72d38ed720e9 ("clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents") Signed-off-by: Pablo Sun Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8188-topckgen.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/media= tek/clk-mt8188-topckgen.c index c4baf4076ed6..6b07abe9a8f5 100644 --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -342,11 +342,14 @@ static const char * const dsp7_parents[] =3D { "univpll_d3" }; =20 +/* + * MFG can be also parented to "univpll_d6" and "univpll_d7": + * these have been removed from the parents list to let us + * achieve GPU DVFS without any special clock handlers. + */ static const char * const mfg_core_tmp_parents[] =3D { "clk26m", - "mainpll_d5_d2", - "univpll_d6", - "univpll_d7" + "mainpll_d5_d2" }; =20 static const char * const camtg_parents[] =3D { --=20 2.45.2 From nobody Thu Nov 28 10:53:17 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EE37C13D; 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charset="utf-8" mt8188 has the same GPU speed binning efuse field just like mt8186, which requires post-processing to convert to the bit field format specified by OPP table. Add the binding for the compatible list: "mediatek,mt8188-efuse", "mediatek,mt8186-efuse" so mt8188 uses the same conversion. Suggested-by: AngeloGioacchino Del Regno Signed-off-by: Pablo Sun --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/= Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 32b8c1eb4e80..70815a3329bf 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -39,6 +39,10 @@ properties: - mediatek,mt8195-efuse - mediatek,mt8516-efuse - const: mediatek,efuse + - items: + - enum: + - mediatek,mt8188-efuse + - const: mediatek,mt8186-efuse - const: mediatek,mt8173-efuse deprecated: true =20 --=20 2.45.2 From nobody Thu Nov 28 10:53:17 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 688E18BE8; Wed, 2 Oct 2024 02:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The OPP table of mt8188 GPU contains duplicated frequencies for different speed bins. In order to support OPP table, we need to provide the speed bin info in the efuse data so the GPU driver could properly set the supported hardware speed bin. Same as mt8186, the efuse data for mt8188's GPU speed binning requires post-process to convert the bit field format expected by the OPP table. Signed-off-by: Pablo Sun --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 02a5bb4dbd1f..2d9378c16e42 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1744,7 +1744,7 @@ imp_iic_wrap_en: clock-controller@11ec2000 { }; =20 efuse: efuse@11f20000 { - compatible =3D "mediatek,mt8188-efuse", "mediatek,efuse"; + compatible =3D "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; reg =3D <0 0x11f20000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; @@ -1752,6 +1752,11 @@ efuse: efuse@11f20000 { lvts_efuse_data1: lvts1-calib@1ac { reg =3D <0x1ac 0x40>; }; + + gpu_speedbin: gpu-speedbin@580 { + reg =3D <0x581 0x1>; + bits =3D <0 3>; + }; }; =20 gpu: gpu@13000000 { @@ -1763,6 +1768,8 @@ gpu: gpu@13000000 { , ; interrupt-names =3D "job", "mmu", "gpu"; + nvmem-cells =3D <&gpu_speedbin>; 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Wed, 2 Oct 2024 10:22:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 2 Oct 2024 10:22:02 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Pablo Sun Subject: [PATCH v3 5/6] soc: mediatek: mediatek-regulator-coupler: Support mt8188 Date: Wed, 2 Oct 2024 10:21:37 +0800 Message-ID: <20241002022138.29241-6-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241002022138.29241-1-pablo.sun@mediatek.com> References: <20241002022138.29241-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Mali GPU in mt8188 also requires coupled power supplies, that is, the "vsram" voltage should follow the "vgpu" voltage. Therefore add the compatible to enable this coupling behavior. Signed-off-by: Pablo Sun Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-regulator-coupler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-regulator-coupler.c b/drivers/soc/med= iatek/mtk-regulator-coupler.c index ad2ed42aa697..0b6a2884145e 100644 --- a/drivers/soc/mediatek/mtk-regulator-coupler.c +++ b/drivers/soc/mediatek/mtk-regulator-coupler.c @@ -147,6 +147,7 @@ static int mediatek_regulator_coupler_init(void) { if (!of_machine_is_compatible("mediatek,mt8183") && !of_machine_is_compatible("mediatek,mt8186") && + !of_machine_is_compatible("mediatek,mt8188") && !of_machine_is_compatible("mediatek,mt8192")) return 0; =20 --=20 2.45.2 From nobody Thu Nov 28 10:53:17 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E60C58BE8; Wed, 2 Oct 2024 02:22:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 02 Oct 2024 10:22:06 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 2 Oct 2024 10:22:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 2 Oct 2024 10:22:04 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Pablo Sun Subject: [PATCH v3 6/6] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU Date: Wed, 2 Oct 2024 10:21:38 +0800 Message-ID: <20241002022138.29241-7-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241002022138.29241-1-pablo.sun@mediatek.com> References: <20241002022138.29241-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.748400-8.000000 X-TMASE-MatchedRID: M6m/rk6FrQxcgzmua3ALxodlc1JaOB1TIfZjRfGTydjCJQ8asLA2F7DW HFry+EP4rgnTk236K6go59mvNdf5O4vTpuEjuIpknVTWWiNp+v8adfsoBn8KlbKsKQz2vVta+4w NuQyQe6mjkL1tNPFpRqBjuNhZcYw1QkfxbJAyTm7r/EBmiNuXt1VDM0QjJZ5DmyiLZetSf8mfop 0ytGwvXiq2rl3dzGQ1zZk/ADR33yL9eqS9TsKMChGHbBOHfyCLJGGjpNIwYaJasW5PvkLnF6Qwj W1eRoC+Aw44L2WMxzIHWGA9o1ZuoRzevJ3An0JpYODWiKq2wvZ0BNB20+SxH7f8mJY57oZddJaB DYald1lvF9+X2GEIHA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.748400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 9F6F30D13840FA44F3EE82DAECC8688D34F0A906778796E2D3E209B0B9A3F3DA2000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Configure GPU regulator supplies and enable GPU for GENIO 700 EVK. The GPU in MT8390 & MT8188 has two power inputs: "DVDD_GPU" and "DVDD_SRAM_GPU". In Genio 700 EVK, DVDD_GPU is supplied by mt6359_vproc2_buck_reg, and DVDD_SRAM_GPU is supplied by mt6359_vsram_others_ldo_reg. According to section 5.2 "Recommended Operating Conditions" in MT8390 IoT Application Processor Datasheet v1.9, The recommended operating voltage ranges are: - DVDD_GPU: min 0.55V, max 0.86V, typical 0.75V - DVDD_SRAM_GPU: min 0.71V, max 0.92V, typical 0.85V To further optimize power saving, we couple DVDD_SRAM_GPU to DVDD_GPU according to the following relation: - For opp-880000000 or lower frequency, keep 0.75V - For opp-915000000 and higher, DVDD_SRAM_GPU should follow DVDD_GPU. The exact voltage for DVDD_GPU should be decided by speed binning. This rule is derived from the OPP table in the link. In addition, set the voltage spread to 6250 uV, the step size of 'ldo_vsram_others' regulator of mt6359, otherwise the regulator set_voltage operation fails. Link: https://gitlab.com/mediatek/aiot/rity/meta-mediatek-bsp/-/blob/eedd6a= edd4b0cfc0ee79b9c9b9650dfa73cf87f6/recipes-kernel/dtbo/mt8390/gpu-mali.dts Signed-off-by: Pablo Sun Suggested-by: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-700-evk.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/a= rm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 1474bef7e754..0a6c9871b41e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -190,6 +190,11 @@ usb_p2_vbus: regulator-10 { }; }; =20 +&gpu { + mali-supply =3D <&mt6359_vproc2_buck_reg>; + status =3D "okay"; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0_pins>; @@ -253,6 +258,14 @@ &i2c6 { status =3D "okay"; }; =20 +&mfg0 { + domain-supply =3D <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6359_vsram_others_ldo_reg>; +}; + &mmc0 { status =3D "okay"; pinctrl-names =3D "default", "state_uhs"; @@ -314,6 +327,15 @@ &mt6359_vpa_buck_reg { regulator-max-microvolt =3D <3100000>; }; =20 +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vgpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + &mt6359_vpu_buck_reg { regulator-always-on; }; @@ -326,6 +348,15 @@ &mt6359_vsim1_ldo_reg { regulator-enable-ramp-delay =3D <480>; }; =20 +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vsram_gpu"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + &mt6359_vufs_ldo_reg { regulator-always-on; }; --=20 2.45.2