From nobody Thu Nov 28 10:01:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C29D1E130F; Wed, 2 Oct 2024 10:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866096; cv=none; b=WQVFZ0Z7j2psrSjNm7UrlIpIERC2Dh65r5oK9PpmV8i3sLXYQq5DBZQ/SIydGuAkHzdMZIkjKC9taeV37Ys6Tg2/2+qGaXXc098rzso1svSZ9gO6fnHQ0wrLMNwRt/HBY4x/pYGcjpCnYw/N4evexzhGCiYvcsVcm2Myl8FDdIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866096; c=relaxed/simple; bh=w1Hu48WwSe36hDwxxCLQSb4anYqbbgR4csAAzUyw8CQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I/Y4RpfQKFbm5NVdrMWoBy8v9gxQ2RTYHu7AlYn3Uq1Hw5vSOhpatgpFYh9XW9bgWKUp0DTUU9TUdlOgn8ish/yCthDnqIElW876SjcF+LdQmlHKfbFnPxmJcnmmDv6CbS/rk70nkZGVuDpZBqDNMR1hisRL1xbHSFWMAM9EA70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n9IeHa1j; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n9IeHa1j" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25BA6C4CED2; Wed, 2 Oct 2024 10:48:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866095; bh=w1Hu48WwSe36hDwxxCLQSb4anYqbbgR4csAAzUyw8CQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n9IeHa1jphL9ex86hNVHAPTc3840PN+lmtU2/VSkMf1/9a3DlKzRkFSnPvJGO3ZQQ bTID8vjjAslTkiauvWcmX/O0kOiZOniWrCUP/YKgySHeNk6+/8j1IrHHHMW6D+yz2v HkyVc11TMXxiLg/eiljYe5u22prkkGWt40THrt2q7ThMkHnfR0nLHobe/eBQh8QEqI sv6LcLeWMfMBCjQW7UCuqInhqaDpgbhsVCJr5GtJc4W+ZjjzTyBpDTslRDoetRhAnD z5cwrXmeEvAOIjUjBdQf6hklMw7pz5ll9uuSNRAaFc3NpPJ0/mcp3eP6ZUcPDjS1Al An4idv6KpixvQ== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 01/11] dt-bindings: mailbox: mpfs: fix reg properties Date: Wed, 2 Oct 2024 11:47:59 +0100 Message-ID: <20241002-stingily-condone-576e948e6d67@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2523; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Wlw0Jwuc/8eGDJh454E9EF1WuAuS4lI9nJV8z679wP8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/Ve5HirypeJvb+expSafkiYYUR76TvBp95qISbb9OP bwVmr+8o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABN5l8HIsP1/U4wy75IFdaY+ lgvqtmq/VrdLsD38V3bCqqtHF7x13M/IcGcFq9L7HlOGM2Wb6uzSc7+95fu068SE2y+2mkSnX8p N5AAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for this was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. This is now coming to a head, because the control/status registers share a register region with the "tvs" (temperature & voltage sensors) registers and, as it turns out, people do want to monitor temperatures and voltages... Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) --- .../bindings/mailbox/microchip,mpfs-mailbox.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailb= ox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.= yaml index 404477910f029..1332aab9a888f 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -15,6 +15,8 @@ properties: =20 reg: oneOf: + - items: + - description: mailbox data registers - items: - description: mailbox control & data registers - description: mailbox interrupt registers @@ -23,6 +25,7 @@ properties: - description: mailbox control registers - description: mailbox interrupt registers - description: mailbox data registers + deprecated: true =20 interrupts: maxItems: 1 @@ -41,12 +44,12 @@ additionalProperties: false examples: - | soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - mbox: mailbox@37020000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x37020800 0x100>; interrupt-parent =3D <&L1>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.45.2 From nobody Thu Nov 28 10:01:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7CC1E766D; Wed, 2 Oct 2024 10:48:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866101; cv=none; b=YaOxmk6Xj7Hacw4cLMpLjs2E9crZVWhNgJWppuIvAzWD+FdZQlxfs46v4jegLuJb2IByhoPi5TCmAZNd7vDCWWYrefOAJDwKR2fBjIY/mTNbFSzZGGp5RLBo35qoX8z9H7ITg8ao1gWhC2HQ9BGECoWVyRPIpAVqgjJ9ZbKHuxQ= ARC-Message-Signature: i=1; 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b=mT6FcBm+9NPas0k19bmjFgo4pekonLTMebgeSQLTomYODQ9ItjiLn/SR0g+BfHVgb Zo3xYCsBnH6FmANCbXNNF6QjoQKYfFVr1kRviUd+5LHbrnemLFvYcdBTTcjb4ef9wE tTK1k4JFcYqsuQs+45qxZbzcuirI3Pkm+we+laYm/XrG8yCGI1dGjIEeRT8z6zpxaT VO0kj3EbemoK/30qON4gEdd2e7l9jl9Q2HsEQEfbDznsKG4UVoTGirZFrGLDsV9N+A fmb4Rwx4qfHchdB2NAndzljctxUZPqvFIw9o4o/rs70owmpdm0Qx4mc+kOO0n5rLuS hnNJkgfplAWAQ== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 02/11] mailbox: mpfs: support new, syscon based, devicetree configuration Date: Wed, 2 Oct 2024 11:48:00 +0100 Message-ID: <20241002-elated-emit-6302c32557c0@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6215; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=c/sHcacLDgEtukJOKU2YjxEWf026tjRvMuKbrhVqPno=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR7wHYx+eTHzaqTK3Rq33578O/zWlH7se2hwxPtnp skHv80VHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhIghzDH25B/o2T/KM6pznI eprcrtfmveKccO9xheqnNzZ35u40y2BkWJxZrbvv/ZorAQ7xy1RnTrkmePDLGfMdCaVGtT1TRGL cGAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The two previous bindings for this hardware were incorrect, as the control/status and interrupt register regions should have been described as syscons and dealt with via regmap in the driver. Add support for accessing these registers using that method now, so that the hwmon driver can be supported without using auxdev or hacks with io_remap(). Signed-off-by: Conor Dooley --- drivers/mailbox/Kconfig | 1 + drivers/mailbox/mailbox-mpfs.c | 87 +++++++++++++++++++++++++++------- 2 files changed, 71 insertions(+), 17 deletions(-) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 6fb995778636a..f856e01429aae 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -168,6 +168,7 @@ config MAILBOX_TEST config POLARFIRE_SOC_MAILBOX tristate "PolarFire SoC (MPFS) Mailbox" depends on HAS_IOMEM + depends on MFD_SYSCON depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST help This driver adds support for the PolarFire SoC (MPFS) mailbox controlle= r. diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 20ee283a04cc6..4df546e3b7eae 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -13,12 +13,15 @@ #include #include #include +#include #include +#include #include #include #include #include =20 +#define MESSAGE_INT_OFFSET 0x18cu #define SERVICES_CR_OFFSET 0x50u #define SERVICES_SR_OFFSET 0x54u #define MAILBOX_REG_OFFSET 0x800u @@ -68,6 +71,7 @@ struct mpfs_mbox { void __iomem *int_reg; struct mbox_chan chans[1]; struct mpfs_mss_response *response; + struct regmap *sysreg_scb, *control_scb; u16 resp_offset; }; =20 @@ -75,7 +79,10 @@ static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) { u32 status; =20 - status =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + if (mbox->control_scb) + regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &status); + else + status =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); =20 return status & SCB_STATUS_BUSY_MASK; } @@ -95,7 +102,11 @@ static bool mpfs_mbox_last_tx_done(struct mbox_chan *ch= an) * Failed services are intended to generated interrupts, but in reality * this does not happen, so the status must be checked here. */ - val =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + if (mbox->control_scb) + regmap_read(mbox->control_scb, SERVICES_SR_OFFSET, &val); + else + val =3D readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + response->resp_status =3D (val & SCB_STATUS_MASK) >> SCB_STATUS_POS; =20 return true; @@ -143,7 +154,12 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan,= void *data) =20 tx_trigger =3D (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK; tx_trigger |=3D SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK; - writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); + + if (mbox->control_scb) + regmap_write(mbox->control_scb, SERVICES_CR_OFFSET, tx_trigger); + else + writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); + =20 return 0; } @@ -185,7 +201,10 @@ static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *= data) struct mbox_chan *chan =3D data; struct mpfs_mbox *mbox =3D (struct mpfs_mbox *)chan->con_priv; =20 - writel_relaxed(0, mbox->int_reg); + if (mbox->control_scb) + regmap_write(mbox->sysreg_scb, MESSAGE_INT_OFFSET, 0); + else + writel_relaxed(0, mbox->int_reg); =20 mpfs_mbox_rx_data(chan); =20 @@ -221,28 +240,62 @@ static const struct mbox_chan_ops mpfs_mbox_ops =3D { .last_tx_done =3D mpfs_mbox_last_tx_done, }; =20 +static inline int mpfs_mbox_syscon_probe(struct mpfs_mbox *mbox, struct pl= atform_device *pdev) +{ + mbox->control_scb =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-= control-scb"); + if (IS_ERR(mbox->control_scb)) + return PTR_ERR(mbox->control_scb); + + mbox->sysreg_scb =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-s= ysreg-scb"); + if (IS_ERR(mbox->sysreg_scb)) + return PTR_ERR(mbox->sysreg_scb); + + mbox->mbox_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mbox->ctrl_base)) + return PTR_ERR(mbox->mbox_base); + + return 0; +} + +static inline int mpfs_mbox_old_format_probe(struct mpfs_mbox *mbox, struc= t platform_device *pdev) +{ + dev_warn(&pdev->dev, "falling back to old devicetree format"); + + mbox->ctrl_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(mbox->ctrl_base)) + return PTR_ERR(mbox->ctrl_base); + + mbox->int_reg =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(mbox->int_reg)) + return PTR_ERR(mbox->int_reg); + + mbox->mbox_base =3D devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs + mbox->mbox_base =3D mbox->ctrl_base + MAILBOX_REG_OFFSET; + + return 0; +} + static int mpfs_mbox_probe(struct platform_device *pdev) { struct mpfs_mbox *mbox; - struct resource *regs; int ret; =20 mbox =3D devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL); if (!mbox) return -ENOMEM; =20 - mbox->ctrl_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, ®s= ); - if (IS_ERR(mbox->ctrl_base)) - return PTR_ERR(mbox->ctrl_base); - - mbox->int_reg =3D devm_platform_get_and_ioremap_resource(pdev, 1, ®s); - if (IS_ERR(mbox->int_reg)) - return PTR_ERR(mbox->int_reg); - - mbox->mbox_base =3D devm_platform_get_and_ioremap_resource(pdev, 2, ®s= ); - if (IS_ERR(mbox->mbox_base)) // account for the old dt-binding w/ 2 regs - mbox->mbox_base =3D mbox->ctrl_base + MAILBOX_REG_OFFSET; - + ret =3D mpfs_mbox_syscon_probe(mbox, pdev); + if (ret) { + /* + * set this to null, so it can be used as the decision for to + * regmap or not to regmap + */ + mbox->control_scb =3D NULL; + ret =3D mpfs_mbox_old_format_probe(mbox, pdev); + if (ret) + return ret; + } mbox->irq =3D platform_get_irq(pdev, 0); if (mbox->irq < 0) return mbox->irq; --=20 2.45.2 From nobody Thu Nov 28 10:01:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 148B71E765A; Wed, 2 Oct 2024 10:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866106; cv=none; b=aNdKm8B5vX94RypFWBEEuH0swBUzIAinWPDNzZeAQsl+HdLbMYUUMFXyTl3vSnnFcig5e2PDTCGhTycu/nAgcntL9/2FGcgg3AbyuwXaf/j28ichNS6hOYrDvJ9D8S98LYTmyAD4P+vwuS5R+8YroScFiVc4uAiQcPLF5QiSPI4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866106; c=relaxed/simple; bh=iu6oBhUAOuMmbpup1hHGDc3avXmUfIwkO7bEe63eIVQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tvKwP+XomGEn/9hjQ+TcjqEsr7A6T1TOuswK1wADAwqI5nglcsiBnkxaudpeiYk65gODMH3tOJlKa7LBRDRpGgHqTFeultryUaMzrQBZGybAkb+B9QKalxbRGVawwvnxsNkGBhWMa+InfsNsIuDxQGBIuWC3BrIoLXZzq/0MqnA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JiPqEWpA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JiPqEWpA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F1B7C4CED3; Wed, 2 Oct 2024 10:48:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866105; bh=iu6oBhUAOuMmbpup1hHGDc3avXmUfIwkO7bEe63eIVQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JiPqEWpA5nCcwtH33o4XrUpfxikAz42cs9nDFndHzMGuHNTCjXb+ICf0oeNIliQf3 GwlERzS5SJiIUh6pZkI4IMUxPNvQtxFJUegF6Gj27hT5OtSvEi6lyPDcTFyZ5yPHNg X6ouQE/epC1rKvWrNVwMSIfwsCyTGJ1t5XSIWSw6tgOdFIA5NQBWvzf8zmoXWkYNSs Nkav9oHPhx8HR2DtervWg795PO7eInVxsDHf0U/k4ud6VXXsYoFz/9D9oP9cNnAjUR L+qEpzHqYkEJ5Gvk7F6KwyT1eOgsLSQi9zyVkWG/ECMWYxRnsP+qG4u4mVIJtcnDlu 1vFUrfidcIr1Q== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 03/11] dt-bindings: mfd: syscon document the non simple-mfd syscon on PolarFire SoC Date: Wed, 2 Oct 2024 11:48:01 +0100 Message-ID: <20241002-clambake-raider-a8cbb3a021a8@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1358; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=tHRWpiyQ8iCGyCWP4whQFJhUVatxkKCTPz6PLOlptNk=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR7YfD0Ty3S3cb+Hf9Cfmd9/Nc6qfPvSy3v2Tbbv0 z/+2mTT01HKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICbfJnhF3NBYWLgZ7vXazy6 eOpnnTe7J+IzN6ZqRdKTWclH63ZfusbIcOAHi8fUy9PcLW9997Tut9AuXHDl9KKWCVo7JwZL3rE 4wgEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "mss_top_scb" register region on PolarFire SoC contains many different functions, including controls for the AXI bus and other things mainly of interest to the bootloader. The interrupt register for the system controller's mailbox is also in here, which is needed by the operating system. Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index cc9b17ad69f23..b414de4fa779b 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -88,6 +88,7 @@ select: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon @@ -185,6 +186,7 @@ properties: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon --=20 2.45.2 From nobody Thu Nov 28 10:01:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE8431EBFE1; Wed, 2 Oct 2024 10:48:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866111; cv=none; b=rkAvDjlXhgZP+yo2crsH2QYIXKyubgh3+Fb0EjGj7lB1v3k08zbd6/R6WVdFG89dQZWFDhWdB/qecWxMsAixWuTUBkrFaNZ1wlp7M8dBikL2Qo0/eB45j42LOx+V4Eiv+bR+LBbUOpmnkN8Z/Tzk990Lw/mErrMu7WDCd/xFsHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866111; c=relaxed/simple; bh=KK+BcsuRJN2IOP669Lit6r47G+i7DjeNaOKrR0WxAuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bfEP7XXzD9FRcGYS0dnxz8ljG5BpKHgOG3D2zdoe1nyTdSqFjyrfu8TKH7io7ypJKN1N7unbzUT/kbsTdmWsmXGgIWTkLBdZPIkBnIwhi/QzbSQoLDTk4gUjQavcPngIZqn/Ub5duvCTVxEeytDLM3h9uAR4Ch2rNmui8abeDhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h4dDEoN1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h4dDEoN1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D86CC4CECD; Wed, 2 Oct 2024 10:48:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866110; bh=KK+BcsuRJN2IOP669Lit6r47G+i7DjeNaOKrR0WxAuc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h4dDEoN1NJoAdiCx4sX6sJTdfUEH32BAxlOp155DHNynwFcMEfMcjJueGjAQhAyP3 N3rijFSFfPqvIoo+YIvp7yRvyWSW/u8TNiMHpP43KX1cY2GDqGjTQhLVAPK8YAWFof DIANwA+glWNgin8PxtTbboXuo+rGfrJPV2MUeSSyHlyaB3mx95iqaJX4wEJ5bGg2BX qflJiD8LyR7bJJ3uvE9/j4OyGlo+CpHXmV2Bak5VJDNuJNZm76p5pZD932/gusDZvn gBghleQ2FMFlne0NCGQEZTS66B+vpCdlmyHiFdCV0+ZxLcaOGCOVHqMJoOpeZxF+Fw y0vh1fI4THvdw== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 04/11] dt-bindings: soc: microchip: document the two simple-mfd syscons on PolarFire SoC Date: Wed, 2 Oct 2024 11:48:02 +0100 Message-ID: <20241002-unvaried-clever-374b4d763849@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4842; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=seCx3G0dokXhsXdE+ckJ6wFNG9AN2iOsqmMg73QRyzA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR7cKntxc7H+lki1DLObUgz3TpjK3edhcDpivKeQY cdjzWOhHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIy+0M/ysPqmy0tE9+1zNj RW6sj2FhmA2D1umNPpZefJ8F3O4teMjwz5Dpg/9+w13CyS7SXHscJ154fD1oreiDN6d0vnpvm7N nMQ8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley There are two syscons on PolarFire SoC that provide various functionality of use to the OS. The first of these is the "control-scb" region, that contains the "tvs" temperature and voltage sensors and the control/status registers for the system controller's mailbox. The mailbox has a dedicated node, so there's no need for a child node describing it, looking the syscon up by compatible is sufficient. The second, "mss-top-sysreg", contains clocks, pinctrl, resets, and interrupt controller and more. At this point, only the reset controller child is described as that's all that is described by the existing bindings. The clock controller already has a dedicated node, and will retain it as there are other clock regions, so like the mailbox, a compatible-based lookup of the syscon is sufficient to keep the clock driver working as before so no child is needed. There's also an interrupt multiplexing service provided by this syscon, for which there is work in progress at [1]. Link: https://lore.kernel.org/linux-gpio/20240723-uncouple-enforcer-7c48e4a= 4fefe@wendy/ [1] Signed-off-by: Conor Dooley --- .../microchip/microchip,mpfs-control-scb.yaml | 44 +++++++++++++++ .../microchip,mpfs-mss-top-sysreg.yaml | 54 +++++++++++++++++++ 2 files changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-control-scb.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-mss-top-sysreg.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -control-scb.yaml b/Documentation/devicetree/bindings/soc/microchip/microch= ip,mpfs-control-scb.yaml new file mode 100644 index 0000000000000..4f9168320243c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-contro= l-scb.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-control-sc= b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC System Controller Bus (SCB) Control Registe= r region + +maintainers: + - Conor Dooley + +description: + An assortment of system controller related registers, including voltage = and + temperature sensors and the status/control registers for the system + controller's mailbox. + +properties: + compatible: + items: + - const: microchip,mpfs-control-scb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon", "simple-mfd= "; + reg =3D <0x37020000 0x100>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs= -mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/micr= ochip,mpfs-mss-top-sysreg.yaml new file mode 100644 index 0000000000000..98ccec3caad51 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-to= p-sysreg.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sy= sreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg Regis= ter region + +maintainers: + - Conor Dooley + +description: + An wide assortment of registers that control elements of the MSS on Pola= rFire + SoC, including pinmuxing, resets and clocks among others. + +properties: + compatible: + items: + - const: microchip,mpfs-mss-top-sysreg + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#reset-cells': + description: | + The AHB/AXI peripherals on the PolarFire SoC have reset support, so + from CLK_ENVM to CLK_CFM. The reset consumer should specify the + desired peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full li= st + of PolarFire clock/reset IDs. + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-= mfd"; + reg =3D <0x20002000 0x1000>; + #reset-cells =3D <1>; + }; + }; + --=20 2.45.2 From nobody Thu Nov 28 10:01:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B3181EBFEE; Wed, 2 Oct 2024 10:48:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866117; cv=none; b=sKUMPCHzkqyLMIVXKDJ00ucW2QqLNCxcIz5QpjeK9uQnHo0J/Ik63duiyszxCdUG3r7poyS3oIZ+h9CnhcNZPP3HVFO2Ct30UKT2+FFG0S6INq9WYFBznY+CQdjm77bZAj3uEBI79QhCdG29+7Ooq8dYX8paLwtw2zz5hjhHi1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866117; c=relaxed/simple; bh=7jVhqVGAjc9ZFGXbZZzkY3dEWfHE6F5nEf5rIqPjM64=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PLd0t41/n/sLmHIA4MJGht7ESQkNUIyf+G9oQPtICW3LudmvoQA/GEkFLIKCTpEN3K2SehWXa/lF3tk/upsRNSkbmz++m2GLiazs+cU6xPozmb813Y6X8tc0N2pV/1CiZhXigwF4W1VtnvU54rIm2hqQ1qX16uL1k+B5KixSlE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E5qfyIJk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E5qfyIJk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2120BC4CEC5; Wed, 2 Oct 2024 10:48:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866115; bh=7jVhqVGAjc9ZFGXbZZzkY3dEWfHE6F5nEf5rIqPjM64=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E5qfyIJknPt90hR8jblJ5EMIV13XykjXFwAOzgIGlnyaKdczVFLPP+NWlvI+nBKI0 bQ2SqOBZnjWUqAyWcod0rubjlCU+SXknM0UQX4MW9PAy/axP6kQM04MQX2mfVUV2Wl WS1AjX3gBgmwXRSL04vB1auwim+oSJGkLGK2bya4bJZ6v+5lLLWzzQiBlzq844NFT2 BSX8usk7NJdxkM7JBEN2U1lUmoFJ4T2M5onVTlm6CjDvkhYHp6WJyo29Smzeye0TcY siIoHYAY+PIBz4K5GP9KToLO9WcDejuJerveDcqQrleLuuUQ4yM5GMPB6dD8V1f4Gd HsJKLcwO47LSg== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 05/11] soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC Date: Wed, 2 Oct 2024 11:48:03 +0100 Message-ID: <20241002-undead-imply-3d240d0cff5e@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4881; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=P0KwHlFPlXIpFEUesBiUq9EexeIVzEEKS9WSONg93nU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR56xJ27Xrj2vIVW3pTbF++UTTsZ5bDO+XOI6ub9d hpdDRNjO0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjARc1GG/77RUwTSL++K/1L3 5d6/99lOnxQmhvFevZ9te+raResnrtYM/4xOTGrcsiGia/NGoSaO8CVn7yhrLX/qobvCKWpfw5m afdwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The control-scb and mss-top-sysreg regions on PolarFire SoC both fulfill multiple purposes. The former is used for mailbox functions in addition to the temperature & voltage sensor while the latter is used for clocks, resets, interrupt muxing and pinctrl. Signed-off-by: Conor Dooley --- drivers/soc/microchip/Kconfig | 13 ++++++ drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-control-scb.c | 45 +++++++++++++++++++ drivers/soc/microchip/mpfs-mss-top-sysreg.c | 48 +++++++++++++++++++++ 4 files changed, 107 insertions(+) create mode 100644 drivers/soc/microchip/mpfs-control-scb.c create mode 100644 drivers/soc/microchip/mpfs-mss-top-sysreg.c diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig index 19f4b576f822b..31d188311e05f 100644 --- a/drivers/soc/microchip/Kconfig +++ b/drivers/soc/microchip/Kconfig @@ -9,3 +9,16 @@ config POLARFIRE_SOC_SYS_CTRL module will be called mpfs_system_controller. =20 If unsure, say N. + +config POLARFIRE_SOC_SYSCONS + bool "PolarFire SoC (MPFS) syscon drivers" + default y + depends on ARCH_MICROCHIP + select MFD_CORE + help + These drivers add support for the syscons on PolarFire SoC (MPFS). + Without these drivers core parts of the kernel such as clocks + and resets will not function correctly. + + If unsure, and on a PolarFire SoC, say y. + diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile index 14489919fe4b3..1a3a1594b089b 100644 --- a/drivers/soc/microchip/Makefile +++ b/drivers/soc/microchip/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) +=3D mpfs-sys-controller.o +obj-$(CONFIG_POLARFIRE_SOC_SYSCONS) +=3D mpfs-control-scb.o mpfs-mss-top-s= ysreg.o diff --git a/drivers/soc/microchip/mpfs-control-scb.c b/drivers/soc/microch= ip/mpfs-control-scb.c new file mode 100644 index 0000000000000..d1a8e79c232e3 --- /dev/null +++ b/drivers/soc/microchip/mpfs-control-scb.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_control_scb_devs[] =3D { + { .name =3D "mpfs-tvs", }, +}; + +static int mpfs_control_scb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_control_scb_devs, + 1, NULL, 0, NULL); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id mpfs_control_scb_of_match[] =3D { + {.compatible =3D "microchip,mpfs-control-scb", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_control_scb_of_match); + +static struct platform_driver mpfs_control_scb_driver =3D { + .driver =3D { + .name =3D "mpfs-control-scb", + .of_match_table =3D mpfs_control_scb_of_match, + }, + .probe =3D mpfs_control_scb_probe, +}; +module_platform_driver(mpfs_control_scb_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC control scb driver"); diff --git a/drivers/soc/microchip/mpfs-mss-top-sysreg.c b/drivers/soc/micr= ochip/mpfs-mss-top-sysreg.c new file mode 100644 index 0000000000000..9b2e7b84cdba2 --- /dev/null +++ b/drivers/soc/microchip/mpfs-mss-top-sysreg.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell mpfs_mss_top_sysreg_devs[] =3D { + { .name =3D "mpfs-reset", }, +}; + +static int mpfs_mss_top_sysreg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D mfd_add_devices(dev, PLATFORM_DEVID_NONE, mpfs_mss_top_sysreg_dev= s, + 1, NULL, 0, NULL); + if (ret) + return ret; + + if (devm_of_platform_populate(dev)) + dev_err(dev, "Error populating children\n"); + + return 0; +} + +static const struct of_device_id mpfs_mss_top_sysreg_of_match[] =3D { + {.compatible =3D "microchip,mpfs-mss-top-sysreg", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_mss_top_sysreg_of_match); + +static struct platform_driver mpfs_mss_top_sysreg_driver =3D { + .driver =3D { + .name =3D "mpfs-mss-top-sysreg", + .of_match_table =3D mpfs_mss_top_sysreg_of_match, + }, + .probe =3D mpfs_mss_top_sysreg_probe, +}; +module_platform_driver(mpfs_mss_top_sysreg_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("PolarFire SoC mss top sysreg driver"); --=20 2.45.2 From nobody Thu Nov 28 10:01:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39C7320125B; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KuxCWszQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1B0F1C4CECF; Wed, 2 Oct 2024 10:48:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866120; bh=aO/B5sOpOxYNDl2NnVgAoNdJHBau2D0IQZssejD8wN4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KuxCWszQEiOTLxYShOLqf1wvo1xjoc0uyEKUXsZGcXfBoUydX7yRQ5gVt+SHtInch lD/QqnAXK7g2wWxR5ma+NKH2tqS44Jp0moFVzFkzMvt1SfeWXHdCWv2QtkD72FgJAX YJELvmMxa7y/02Fqb3NAkyVoxDZ/QgdvVmJgV3EneD+QJRgwfq51z+XcqlxnVZ+WIl B8NNd0tRFKF+1jARSRlUKd5/SiMIzXd8Rhe9r9JbTEgPLBy6VNizK2SGewSgeiq9wv juBNdYJFFTQap1Nd5xkSwuSkl3tWXiaWERUOQdwjYXbI/JeDHvqGOrZF5F1vAqT2px pgu3gjpB0BM5g== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 06/11] reset: mpfs: add non-auxiliary bus probing Date: Wed, 2 Oct 2024 11:48:04 +0100 Message-ID: <20241002-breeze-anywhere-4114da636ec6@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5754; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=i35+CsFCV6sYfJT3KjLRVBUt7UkYZ1HKKhA4wN86iUQ=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR6eDFO8tGTeB5GOJKuovLnZ50Jmp+88oLrKMq3ts 09enm54RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbC78nwP+KTgmbztesTTtTa WS9XXcj5U0ohW7nR0OX5k+Yj/OsKrzMy7LX5YqEg/G1yF6vTlJrZRqcfnakPjpc4s+KFYsJMa7V CTgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley While the auxiliary bus was a nice bandaid, and meant that re-writing the representation of the clock regions in devicetree was not required, it has run its course. The "mss_top_sysreg" region that contains the clock and reset regions, also contains pinctrl and an interrupt controller, so the time has come rewrite the devicetree and probe the reset controller from an mfd devicetree node, rather than implement those drivers using the auxiliary bus. Wanting to avoid propagating this naive/incorrect description of the hardware to the new pic64gx SoC is a major motivating factor here. Signed-off-by: Conor Dooley --- drivers/reset/reset-mpfs.c | 83 ++++++++++++++++++++++++++++++++------ 1 file changed, 71 insertions(+), 12 deletions(-) diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index 710f9c1676f93..ac72e0fc405ed 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -9,10 +9,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -27,14 +29,37 @@ #define MPFS_SLEEP_MIN_US 100 #define MPFS_SLEEP_MAX_US 200 =20 +#define REG_SUBBLK_RESET_CR 0x88u + /* block concurrent access to the soft reset register */ static DEFINE_SPINLOCK(mpfs_reset_lock); =20 struct mpfs_reset { void __iomem *base; + struct regmap *regmap; struct reset_controller_dev rcdev; }; =20 +static inline u32 mpfs_reset_read(struct mpfs_reset *rst) +{ + u32 ret; + + if (rst->regmap) + regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, &ret); + else + ret =3D readl(rst->base); + + return ret; +} + +static inline void mpfs_reset_write(struct mpfs_reset *rst, u32 val) +{ + if (rst->regmap) + regmap_write(rst->regmap, REG_SUBBLK_RESET_CR, val); + else + writel(val, rst->base); +} + static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev= *rcdev) { return container_of(rcdev, struct mpfs_reset, rcdev); @@ -51,9 +76,9 @@ static int mpfs_assert(struct reset_controller_dev *rcdev= , unsigned long id) =20 spin_lock_irqsave(&mpfs_reset_lock, flags); =20 - reg =3D readl(rst->base); + reg =3D mpfs_reset_read(rst); reg |=3D BIT(id); - writel(reg, rst->base); + mpfs_reset_write(rst, reg); =20 spin_unlock_irqrestore(&mpfs_reset_lock, flags); =20 @@ -68,9 +93,9 @@ static int mpfs_deassert(struct reset_controller_dev *rcd= ev, unsigned long id) =20 spin_lock_irqsave(&mpfs_reset_lock, flags); =20 - reg =3D readl(rst->base); + reg =3D mpfs_reset_read(rst); reg &=3D ~BIT(id); - writel(reg, rst->base); + mpfs_reset_write(rst, reg); =20 spin_unlock_irqrestore(&mpfs_reset_lock, flags); =20 @@ -80,7 +105,7 @@ static int mpfs_deassert(struct reset_controller_dev *rc= dev, unsigned long id) static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) { struct mpfs_reset *rst =3D to_mpfs_reset(rcdev); - u32 reg =3D readl(rst->base); + u32 reg =3D mpfs_reset_read(rst); =20 /* * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit @@ -130,11 +155,45 @@ static int mpfs_reset_xlate(struct reset_controller_d= ev *rcdev, return index - MPFS_PERIPH_OFFSET; } =20 -static int mpfs_reset_probe(struct auxiliary_device *adev, - const struct auxiliary_device_id *id) +static int mpfs_reset_mfd_probe(struct platform_device *pdev) { - struct device *dev =3D &adev->dev; struct reset_controller_dev *rcdev; + struct device *dev =3D &pdev->dev; + struct mpfs_reset *rst; + + rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); + if (!rst) + return -ENOMEM; + + rcdev =3D &rst->rcdev; + rcdev->dev =3D dev; + rcdev->ops =3D &mpfs_reset_ops; + + rcdev->of_node =3D pdev->dev.parent->of_node; + rcdev->of_reset_n_cells =3D 1; + rcdev->of_xlate =3D mpfs_reset_xlate; + rcdev->nr_resets =3D MPFS_NUM_RESETS; + + rst->regmap =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rst->regmap)) + dev_err_probe(dev, PTR_ERR(rst->regmap), "Failed to find syscon regmap\n= "); + + return devm_reset_controller_register(dev, rcdev); +} + +static struct platform_driver mpfs_reset_mfd_driver =3D { + .probe =3D mpfs_reset_mfd_probe, + .driver =3D { + .name =3D "mpfs-reset", + }, +}; +module_platform_driver(mpfs_reset_mfd_driver); + +static int mpfs_reset_adev_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct reset_controller_dev *rcdev; + struct device *dev =3D &adev->dev; struct mpfs_reset *rst; =20 rst =3D devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); @@ -145,8 +204,8 @@ static int mpfs_reset_probe(struct auxiliary_device *ad= ev, =20 rcdev =3D &rst->rcdev; rcdev->dev =3D dev; - rcdev->dev->parent =3D dev->parent; rcdev->ops =3D &mpfs_reset_ops; + rcdev->of_node =3D dev->parent->of_node; rcdev->of_reset_n_cells =3D 1; rcdev->of_xlate =3D mpfs_reset_xlate; @@ -222,12 +281,12 @@ static const struct auxiliary_device_id mpfs_reset_id= s[] =3D { }; MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); =20 -static struct auxiliary_driver mpfs_reset_driver =3D { - .probe =3D mpfs_reset_probe, +static struct auxiliary_driver mpfs_reset_aux_driver =3D { + .probe =3D mpfs_reset_adev_probe, .id_table =3D mpfs_reset_ids, }; =20 -module_auxiliary_driver(mpfs_reset_driver); +module_auxiliary_driver(mpfs_reset_aux_driver); =20 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); MODULE_AUTHOR("Conor Dooley "); --=20 2.45.2 From nobody Thu Nov 28 10:01:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C89FC1EC005; Wed, 2 Oct 2024 10:48:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866125; cv=none; b=VMERlaQ79AKVcuOFXeXkKB96R/YVBuL1k713GMuZMPf1n4thtv59kn5rTHKwZM9Wlxa/l3zigRiVprPWggrzo+dKE6YixkvlzvEui0X8zt5DJE9zoRs0hKuD/2HEHjyvZbDEbXYBecvqBiY+3B56cgRpWr0WY4KdpdDj9DKndl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866125; c=relaxed/simple; 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a=openpgp-sha256; l=3114; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=kST0+2tXhuKzMDOPomFGGrXe4L7ZWEEe3gXv+x0OOeE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR6Wt12Ydeai+CKLbVtPx9pPuv5iTbpzIZ+P1slN1 RwRLDv/dpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAigqsZGe7tOFrA8qh5p8KJ T4m/jBYUd59NnfbRes3F4lm2FRFnC24x/E9tcxaatEbS8bqBJFPxzCTmL1c+1VizrGZfv+mjypw LV1kA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Signed-off-by: Conor Dooley Acked-by: Rob Herring (Arm) --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2a..ee4f31596d978 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll =20 clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.45.2 From nobody Thu Nov 28 10:01:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C41D01EC00B; Wed, 2 Oct 2024 10:48:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866130; cv=none; b=ax3mQ6LnabiedqSY9sROJbOlFT9NH1rl5hxNrlV1InIkK2HiB2lvcljXYLNkwCOydjAJH8Y4/bKBBDe7/GkCgHnmDqAUgCB9qDdb5S4o72SxSHlrg7/DWnm8KOJcRqCErdXhrd8LfgFn5uH4ioF/9pSvFXEzb1zszuqVzu+Hh1w= ARC-Message-Signature: i=1; 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b=pOuED2mia0rvwsEcdn+K6jDV5rSYRrIymzKfBmZefzuDHcNN9c/g7hYnpckHL06+1 Uu53eH2HRARktXDQZKsBxfeo9ixxh3AZ7MDKT5MjcPA9qM76dkT/ksYEXDZ3LPHNeU RMIqI+Cco3GPrpajsc66ySJY/CPkNn8NylOn9nz5/xNPXDh8Q8Wuk3AL5IRreQ5zmk VbUt62wHahxvlvb6zQFlXLSY9JYHc3I5bi0lEV7XFUC+ykIP+Zf7Y3dpQKgok+H8hf HlNgMH0cy+Ja+ZSKThmMXYdPMt4sm/YbkWcfh6V3AitFE29j2isXn7saSVi2qD7d6J Y5FLdDIG/dW4g== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 08/11] clk: move meson clk-regmap implementation to common code Date: Wed, 2 Oct 2024 11:48:06 +0100 Message-ID: <20241002-hula-unwashed-1c4ddbadbec2@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=20090; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Z6idHNY0klwwl1OjaLT9FKE/+kSQIdv9mwwLFhOkY88=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR5y6pncqLgv4j0/uD76UvQ6TgGViyWedg0KbLPd3 ne4Ce/pKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwESOMzEy7FY4ku6e7B+S3F70 YNYjFrMTPaqLbX4lfxJ9OPmmif3Ve4wMj+3bDAxX8S9sO3iRN1u78u+RoPbnB84Hck7kud4/t86 eEQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley I like this one better than qualcomms and wish to use it for the PolarFire SoC clock drivers. Signed-off-by: Conor Dooley Acked-by: Neil Armstrong --- drivers/clk/Kconfig | 4 ++ drivers/clk/Makefile | 1 + drivers/clk/{meson =3D> }/clk-regmap.c | 2 +- drivers/clk/meson/Kconfig | 46 +++++++++---------- drivers/clk/meson/Makefile | 1 - drivers/clk/meson/a1-peripherals.c | 2 +- drivers/clk/meson/a1-pll.c | 2 +- drivers/clk/meson/axg-aoclk.c | 2 +- drivers/clk/meson/axg-audio.c | 2 +- drivers/clk/meson/axg.c | 2 +- drivers/clk/meson/c3-peripherals.c | 2 +- drivers/clk/meson/c3-pll.c | 2 +- drivers/clk/meson/clk-cpu-dyndiv.c | 2 +- drivers/clk/meson/clk-dualdiv.c | 2 +- drivers/clk/meson/clk-mpll.c | 2 +- drivers/clk/meson/clk-phase.c | 2 +- drivers/clk/meson/clk-pll.c | 2 +- drivers/clk/meson/g12a-aoclk.c | 2 +- drivers/clk/meson/g12a.c | 2 +- drivers/clk/meson/gxbb-aoclk.c | 2 +- drivers/clk/meson/gxbb.c | 2 +- drivers/clk/meson/meson-aoclk.h | 2 +- drivers/clk/meson/meson-eeclk.c | 2 +- drivers/clk/meson/meson-eeclk.h | 2 +- drivers/clk/meson/meson8-ddr.c | 2 +- drivers/clk/meson/meson8b.c | 2 +- drivers/clk/meson/s4-peripherals.c | 2 +- drivers/clk/meson/s4-pll.c | 2 +- drivers/clk/meson/sclk-div.c | 2 +- drivers/clk/meson/vclk.h | 2 +- drivers/clk/meson/vid-pll-div.c | 2 +- .../meson =3D> include/linux/clk}/clk-regmap.h | 0 32 files changed, 53 insertions(+), 53 deletions(-) rename drivers/clk/{meson =3D> }/clk-regmap.c (99%) rename {drivers/clk/meson =3D> include/linux/clk}/clk-regmap.h (100%) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 299bc678ed1b9..85397308a74f4 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -33,6 +33,10 @@ menuconfig COMMON_CLK =20 if COMMON_CLK =20 +config COMMON_CLK_REGMAP + bool + select REGMAP + config COMMON_CLK_WM831X tristate "Clock driver for WM831x/2x PMICs" depends on MFD_WM831X diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index fb8878a5d7d93..bffdbfb932beb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_COMMON_CLK) +=3D clk-gate.o obj-$(CONFIG_CLK_GATE_KUNIT_TEST) +=3D clk-gate_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-multiplier.o obj-$(CONFIG_COMMON_CLK) +=3D clk-mux.o +obj-$(CONFIG_COMMON_CLK_REGMAP) +=3D clk-regmap.o obj-$(CONFIG_COMMON_CLK) +=3D clk-composite.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fractional-divider.o obj-$(CONFIG_CLK_FD_KUNIT_TEST) +=3D clk-fractional-divider_test.o diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/clk-regmap.c similarity index 99% rename from drivers/clk/meson/clk-regmap.c rename to drivers/clk/clk-regmap.c index 07f7e441b9161..4ec0ed8f72011 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/clk-regmap.c @@ -5,7 +5,7 @@ */ =20 #include -#include "clk-regmap.h" +#include =20 static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) { diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 78f648c9c97dc..ee4599dab7ff7 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -2,61 +2,57 @@ menu "Clock support for Amlogic platforms" depends on ARCH_MESON || COMPILE_TEST =20 -config COMMON_CLK_MESON_REGMAP - tristate - select REGMAP - config COMMON_CLK_MESON_DUALDIV tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_MPLL tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_PHASE tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_PLL tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_SCLK_DIV tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_VID_PLL_DIV tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_VCLK tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON_CLKC_UTILS tristate =20 config COMMON_CLK_MESON_AO_CLKC tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_CLKC_UTILS select RESET_CONTROLLER =20 config COMMON_CLK_MESON_EE_CLKC tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_CLKC_UTILS =20 config COMMON_CLK_MESON_CPU_DYNDIV tristate - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP =20 config COMMON_CLK_MESON8B bool "Meson8 SoC Clock controller support" depends on ARM default y - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL @@ -71,7 +67,7 @@ config COMMON_CLK_GXBB tristate "GXBB and GXL SoC clock controllers support" depends on ARM64 default y - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_VID_PLL_DIV select COMMON_CLK_MESON_MPLL @@ -87,7 +83,7 @@ config COMMON_CLK_AXG tristate "AXG SoC clock controllers support" depends on ARM64 default y - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL @@ -101,7 +97,7 @@ config COMMON_CLK_AXG config COMMON_CLK_AXG_AUDIO tristate "Meson AXG Audio Clock Controller Driver" depends on ARM64 - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_PHASE select COMMON_CLK_MESON_SCLK_DIV select COMMON_CLK_MESON_CLKC_UTILS @@ -113,7 +109,7 @@ config COMMON_CLK_AXG_AUDIO config COMMON_CLK_A1_PLL tristate "Amlogic A1 SoC PLL controller support" depends on ARM64 - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_PLL help @@ -125,7 +121,7 @@ config COMMON_CLK_A1_PERIPHERALS tristate "Amlogic A1 SoC Peripherals clock controller support" depends on ARM64 select COMMON_CLK_MESON_DUALDIV - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_CLKC_UTILS help Support for the Peripherals clock controller on Amlogic A113L based @@ -136,7 +132,7 @@ config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 default y - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_CLKC_UTILS imply COMMON_CLK_SCMI @@ -149,7 +145,7 @@ config COMMON_CLK_C3_PERIPHERALS tristate "Amlogic C3 peripherals clock controller" depends on ARM64 default y - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_CLKC_UTILS imply COMMON_CLK_SCMI @@ -163,7 +159,7 @@ config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 default y - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL @@ -184,7 +180,7 @@ config COMMON_CLK_S4_PLL select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP help Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devic= es, AKA S4. Say Y if you want the board to work, because PLLs are the paren= t of @@ -195,7 +191,7 @@ config COMMON_CLK_S4_PERIPHERALS depends on ARM64 default y select COMMON_CLK_MESON_CLKC_UTILS - select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_VID_PLL_DIV help diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1d..cd870281d82c7 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) +=3D meson-eeclk.o obj-$(CONFIG_COMMON_CLK_MESON_MPLL) +=3D clk-mpll.o obj-$(CONFIG_COMMON_CLK_MESON_PHASE) +=3D clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON_PLL) +=3D clk-pll.o -obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) +=3D clk-regmap.o obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) +=3D sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) +=3D vid-pll-div.o obj-$(CONFIG_COMMON_CLK_MESON_VCLK) +=3D vclk.o diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index 7aa6abb2eb1f2..6178e6a153394 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -12,7 +12,7 @@ #include #include "a1-peripherals.h" #include "clk-dualdiv.h" -#include "clk-regmap.h" +#include #include "meson-clkc-utils.h" =20 #include diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 8e5a42d1afbbc..48ba3981b22df 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -11,7 +11,7 @@ #include #include #include "a1-pll.h" -#include "clk-regmap.h" +#include #include "meson-clkc-utils.h" =20 #include diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index 1dabc81535a6f..ee89edf05a443 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -15,7 +15,7 @@ #include #include "meson-aoclk.h" =20 -#include "clk-regmap.h" +#include #include "clk-dualdiv.h" =20 #include diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index beda863493899..06ccf1db63f58 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -17,7 +17,7 @@ =20 #include "meson-clkc-utils.h" #include "axg-audio.h" -#include "clk-regmap.h" +#include #include "clk-phase.h" #include "sclk-div.h" =20 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 757c7a28c53de..73a0cad223c9c 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -15,7 +15,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-pll.h" #include "clk-mpll.h" #include "axg.h" diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index 7dcbf4ebee078..13c13ead6bc66 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -8,7 +8,7 @@ =20 #include #include -#include "clk-regmap.h" +#include #include "clk-dualdiv.h" #include "meson-clkc-utils.h" #include diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c index 32bd2ed9d3044..06a7322403b53 100644 --- a/drivers/clk/meson/c3-pll.c +++ b/drivers/clk/meson/c3-pll.c @@ -8,7 +8,7 @@ =20 #include #include -#include "clk-regmap.h" +#include #include "clk-pll.h" #include "meson-clkc-utils.h" #include diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu= -dyndiv.c index 6c1f58826e24a..d14bb1b5e4337 100644 --- a/drivers/clk/meson/clk-cpu-dyndiv.c +++ b/drivers/clk/meson/clk-cpu-dyndiv.c @@ -7,7 +7,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-cpu-dyndiv.h" =20 static inline struct meson_clk_cpu_dyndiv_data * diff --git a/drivers/clk/meson/clk-dualdiv.c b/drivers/clk/meson/clk-dualdi= v.c index 913bf25d3771b..8926f6fc94edf 100644 --- a/drivers/clk/meson/clk-dualdiv.c +++ b/drivers/clk/meson/clk-dualdiv.c @@ -24,7 +24,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-dualdiv.h" =20 static inline struct meson_clk_dualdiv_data * diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index f639d56f0fd3f..cdf5c3cbeda12 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -15,7 +15,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-mpll.h" =20 #define SDM_DEN 16384 diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c index c1526fbfb6c4c..f48384c190e2f 100644 --- a/drivers/clk/meson/clk-phase.c +++ b/drivers/clk/meson/clk-phase.c @@ -7,7 +7,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-phase.h" =20 #define phase_step(_width) (360 / (1 << (_width))) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index bc570a2ff3a3f..44d87c6c3dcaa 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -33,7 +33,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-pll.h" =20 static inline struct meson_clk_pll_data * diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index f0a18d8c9fc23..25e6f2597407e 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -15,7 +15,7 @@ #include #include "meson-aoclk.h" =20 -#include "clk-regmap.h" +#include #include "clk-dualdiv.h" =20 #include diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 02dda57105b10..b88b2519c9150 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -19,7 +19,7 @@ =20 #include "clk-mpll.h" #include "clk-pll.h" -#include "clk-regmap.h" +#include #include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" #include "vclk.h" diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 83b034157b353..f6facefc79041 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -8,7 +8,7 @@ #include #include "meson-aoclk.h" =20 -#include "clk-regmap.h" +#include #include "clk-dualdiv.h" =20 #include diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index f071faad1ebb7..a9c5d73ee4bfb 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -11,7 +11,7 @@ #include =20 #include "gxbb.h" -#include "clk-regmap.h" +#include #include "clk-pll.h" #include "clk-mpll.h" #include "meson-eeclk.h" diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aocl= k.h index 308be3e4814a9..099f4d5b55b10 100644 --- a/drivers/clk/meson/meson-aoclk.h +++ b/drivers/clk/meson/meson-aoclk.h @@ -16,7 +16,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "meson-clkc-utils.h" =20 struct meson_aoclk_data { diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eecl= k.c index 66f79e384fe51..bbbaf9743abd5 100644 --- a/drivers/clk/meson/meson-eeclk.c +++ b/drivers/clk/meson/meson-eeclk.c @@ -11,7 +11,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "meson-eeclk.h" =20 int meson_eeclkc_probe(struct platform_device *pdev) diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eecl= k.h index 37a48b75c6605..2def0370200a4 100644 --- a/drivers/clk/meson/meson-eeclk.h +++ b/drivers/clk/meson/meson-eeclk.h @@ -8,7 +8,7 @@ #define __MESON_CLKC_H =20 #include -#include "clk-regmap.h" +#include #include "meson-clkc-utils.h" =20 struct platform_device; diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 4b73ea244b630..22b1404ed3e1c 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -10,7 +10,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "clk-pll.h" =20 #define AM_DDR_PLL_CNTL 0x00 diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b7417ac262d33..8711c57e84b5c 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -17,7 +17,7 @@ #include =20 #include "meson8b.h" -#include "clk-regmap.h" +#include #include "meson-clkc-utils.h" #include "clk-pll.h" #include "clk-mpll.h" diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index c930cf0614a0f..e780bb0a07895 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -10,7 +10,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "vid-pll-div.h" #include "clk-dualdiv.h" #include "s4-peripherals.h" diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index b0258933fb9d2..e5e71f0a23ebd 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -12,7 +12,7 @@ =20 #include "clk-mpll.h" #include "clk-pll.h" -#include "clk-regmap.h" +#include #include "s4-pll.h" #include "meson-clkc-utils.h" #include diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c index ae03b048182f3..912b5c9b4c296 100644 --- a/drivers/clk/meson/sclk-div.c +++ b/drivers/clk/meson/sclk-div.c @@ -19,7 +19,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "sclk-div.h" =20 static inline struct meson_sclk_div_data * diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h index 20b0b181db09d..6f0370b0d3a69 100644 --- a/drivers/clk/meson/vclk.h +++ b/drivers/clk/meson/vclk.h @@ -6,7 +6,7 @@ #ifndef __VCLK_H #define __VCLK_H =20 -#include "clk-regmap.h" +#include #include "parm.h" =20 /** diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-di= v.c index 486cf68fc97a0..e3558b1a0744c 100644 --- a/drivers/clk/meson/vid-pll-div.c +++ b/drivers/clk/meson/vid-pll-div.c @@ -7,7 +7,7 @@ #include #include =20 -#include "clk-regmap.h" +#include #include "vid-pll-div.h" =20 static inline struct meson_vid_pll_div_data * diff --git a/drivers/clk/meson/clk-regmap.h b/include/linux/clk/clk-regmap.h similarity index 100% rename from drivers/clk/meson/clk-regmap.h rename to include/linux/clk/clk-regmap.h --=20 2.45.2 From nobody Thu Nov 28 10:01:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) 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linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 09/11] clk: microchip: mpfs: use regmap clock types Date: Wed, 2 Oct 2024 11:48:07 +0100 Message-ID: <20241002-monkhood-album-64c44dc9841b@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8447; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Yu86W17jKMDKSzVLM2Zg0G0yvkuZxddHUoJQp2hVgMM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR5lzj/5J63zp8HB9vM1uyYXetzY3Ddb38RUgbPxp xXLvXvhHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhIYxDD/2SZl9slOIzvdulP rpg1xUnmRs/348WTBctT/TuLQ22dtzL8r1J/cG7W3I2ZW1J8WEQP/t+66U6h5rT355/sSz803YT Fgh8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Convert the PolarFire SoC clock driver to use regmap clock types as a preparatory work for supporting the new binding for this device that will only provide the second of the two register regions, and will require the use of syscon regmap to access the "cfg" and "periph" clocks currently supported by the driver. Signed-off-by: Conor Dooley --- drivers/clk/microchip/Kconfig | 3 + drivers/clk/microchip/clk-mpfs.c | 114 ++++++++++++++++++++++--------- 2 files changed, 85 insertions(+), 32 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 0724ce65898f3..72da1e0f437d9 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -7,6 +7,9 @@ config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST default ARCH_MICROCHIP_POLARFIRE + depends on MFD_SYSCON select AUXILIARY_BUS + select COMMON_CLK_REGMAP + select REGMAP_MMIO help Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index 28ec0da88cb38..8cf963291317c 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -6,10 +6,13 @@ */ #include #include +#include #include #include +#include #include #include +#include =20 /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u @@ -30,6 +33,14 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +static const struct regmap_config clk_mpfs_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .val_format_endian =3D REGMAP_ENDIAN_LITTLE, + .max_register =3D REG_SUBBLK_CLOCK_CR, +}; + /* * This clock ID is defined here, rather than the binding headers, as it i= s an * internal clock only, and therefore has no consumers in other peripheral @@ -39,6 +50,7 @@ =20 struct mpfs_clock_data { struct device *dev; + struct regmap *regmap; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -68,14 +80,14 @@ struct mpfs_msspll_out_hw_clock { #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_o= ut_hw_clock, hw) =20 struct mpfs_cfg_hw_clock { - struct clk_divider cfg; - struct clk_init_data init; + struct clk_regmap sigh; + struct clk_regmap_div_data cfg; unsigned int id; - u32 reg_offset; }; =20 struct mpfs_periph_hw_clock { - struct clk_gate periph; + struct clk_regmap sigh; + struct clk_regmap_gate_data periph; unsigned int id; }; =20 @@ -225,10 +237,9 @@ static int mpfs_clk_register_msspll_outs(struct device= *dev, .cfg.shift =3D _shift, \ .cfg.width =3D _width, \ .cfg.table =3D _table, \ - .reg_offset =3D _offset, \ + .cfg.offset =3D _offset, \ .cfg.flags =3D _flags, \ - .cfg.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ - .cfg.lock =3D &mpfs_clk_lock, \ + .sigh.hw.init =3D CLK_HW_INIT(_name, _parent, &clk_regmap_divider_ops, 0)= , \ } =20 #define CLK_CPU_OFFSET 0u @@ -248,10 +259,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] =3D { .cfg.shift =3D 0, .cfg.width =3D 12, .cfg.table =3D mpfs_div_rtcref_table, - .reg_offset =3D REG_RTC_CLOCK_CR, + .cfg.offset =3D REG_RTC_CLOCK_CR, .cfg.flags =3D CLK_DIVIDER_ONE_BASED, - .cfg.hw.init =3D - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, = 0), + .sigh.hw.init =3D + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_regmap_divide= r_ops, 0), } }; =20 @@ -264,14 +275,16 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * for (i =3D 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw =3D &cfg_hws[i]; =20 - cfg_hw->cfg.reg =3D data->base + cfg_hw->reg_offset; - ret =3D devm_clk_hw_register(dev, &cfg_hw->cfg.hw); + cfg_hw->sigh.map =3D data->regmap; + cfg_hw->sigh.data =3D &cfg_hw->cfg; + + ret =3D devm_clk_hw_register(dev, &cfg_hw->sigh.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->id); =20 id =3D cfg_hw->id; - data->hw_data.hws[id] =3D &cfg_hw->cfg.hw; + data->hw_data.hws[id] =3D &cfg_hw->sigh.hw; } =20 return 0; @@ -283,13 +296,13 @@ static int mpfs_clk_register_cfgs(struct device *dev,= struct mpfs_cfg_hw_clock * =20 #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ .id =3D _id, \ + .periph.offset =3D REG_SUBBLK_CLOCK_CR, \ .periph.bit_idx =3D _shift, \ - .periph.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ - _flags), \ - .periph.lock =3D &mpfs_clk_lock, \ + .sigh.hw.init =3D CLK_HW_INIT_HW(_name, _parent, &clk_regmap_gate_ops, \ + _flags), \ } =20 -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].sigh.hw) =20 /* * Critical clocks: @@ -346,19 +359,61 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c for (i =3D 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw =3D &periph_hws[i]; =20 - periph_hw->periph.reg =3D data->base + REG_SUBBLK_CLOCK_CR; - ret =3D devm_clk_hw_register(dev, &periph_hw->periph.hw); + periph_hw->sigh.map =3D data->regmap; + periph_hw->sigh.data =3D &periph_hw->periph; + ret =3D devm_clk_hw_register(dev, &periph_hw->sigh.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->id); =20 id =3D periph_hws[i].id; - data->hw_data.hws[id] =3D &periph_hw->periph.hw; + data->hw_data.hws[id] =3D &periph_hw->sigh.hw; } =20 return 0; } =20 +static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data, + struct platform_device *pdev) +{ + clk_data->regmap =3D syscon_regmap_lookup_by_compatible("microchip,mpfs-m= ss-top-sysreg"); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + return 0; +} + +static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_da= ta, + struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + int ret; + + dev_warn(&pdev->dev, "falling back to old devicetree format"); + + clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->base)) + return PTR_ERR(clk_data->base); + + clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + + clk_data->regmap =3D devm_regmap_init_mmio(dev, clk_data->base, &clk_mpfs= _regmap_config); + if (IS_ERR(clk_data->regmap)) + return PTR_ERR(clk_data->regmap); + + ret =3D mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_R= ESET_CR); + if (ret) + return ret; + + return 0; +} + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -374,13 +429,12 @@ static int mpfs_clk_probe(struct platform_device *pde= v) if (!clk_data) return -ENOMEM; =20 - clk_data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(clk_data->base)) - return PTR_ERR(clk_data->base); - - clk_data->msspll_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(clk_data->msspll_base)) - return PTR_ERR(clk_data->msspll_base); + ret =3D mpfs_clk_syscon_probe(clk_data, pdev); + if (ret) { + ret =3D mpfs_clk_old_format_probe(clk_data, pdev); + if (ret) + return ret; + } =20 clk_data->hw_data.num =3D num_clks; clk_data->dev =3D dev; @@ -406,11 +460,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data= ->hw_data); - if (ret) - return ret; - - return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RE= SET_CR); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data-= >hw_data); } =20 static const struct of_device_id mpfs_clk_of_match_table[] =3D { --=20 2.45.2 From nobody Thu Nov 28 10:01:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF497200100; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U15x/gDf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0FFBCC4CEC5; Wed, 2 Oct 2024 10:48:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727866140; bh=7OviCXFHffO2bkj/xL5xz0DArD3vTiDNKyE94fzpFII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U15x/gDfugw+t7bdXCeSi8WG8lT0ArCkTgk7oKatp1fDoXs2wjF9M8h3+2yYI1FrF 2Ya2d8KeEH6N8rRmiz/JiEGQd1RzWBHSrB20F4kI9SSDuXHi2r2eb+MN6a5FIFm7GW spyLz01ZgmXAixriN4CaQUB4VEUdhJ82D/7tmiVf612cSOEnur9Cj4vEp9Hb8N3FpY pm+hsoXoy3lNsS4fkbEd4ThPqWSoCzjw92jyCl5Vby2W1PiVkVhDuRHJGc7eHdLfwR qmwSxqVsLlWr5jl8j2rq+0sIpY/yiwUIIDN1TSPwlzuOXiHQjMipdYbTyPsLkh7RW8 wSD+jn6eDeeIA== From: Conor Dooley To: linux-kernel@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Albert Ou , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 10/11] riscv: dts: microchip: fix mailbox description Date: Wed, 2 Oct 2024 11:48:08 +0100 Message-ID: <20241002-finch-sugar-9958077e8c2b@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-private-unequal-33cfa6101338@spud> References: <20241002-private-unequal-33cfa6101338@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2063; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=DOFHAjKnf7tU+evTd+s0TtMPYvUr+DWExrkuybwEW5k=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR49cK83bXR/GN0r4v+xyLctOOfQcn9l1mg7N5FZB 7ceEnvWUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgImYtDEy7E9N8BHdYnf1N/8L pucOvlfebVlXf674PkfolY1NSe+2BjD8U37rVnVGl8O8ri1oXvp2dgmu/q7jAUW7HQ6cr+5cvy2 fHwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index 9883ca3554c50..f8a45e4f00a0d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 { #reset-cells =3D <1>; }; =20 + sysreg_scb: syscon@20003000 { + compatible =3D "microchip,mpfs-sysreg-scb", "syscon"; + reg =3D <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible =3D "microchip,mpfs-ccc"; reg =3D <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ usb: usb@20201000 { status =3D "disabled"; }; =20 - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible =3D "microchip,mpfs-control-scb", "syscon", "simple-mfd"; + reg =3D <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible =3D "microchip,mpfs-mailbox"; - reg =3D <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg =3D <0x0 0x37020800 0x0 0x100>; interrupt-parent =3D <&plic>; interrupts =3D <96>; #mbox-cells =3D <1>; --=20 2.45.2 From nobody Thu Nov 28 10:01:13 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8B8D1E7669; Wed, 2 Oct 2024 10:49:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866145; cv=none; b=j/PddaUsqUmnWoMoViz0CDpfNSx1SHXOUBLhPVWTZlyr+ITJGfCn7M+nKiK+V1HCowN6dOx9rFL+g/DUG1EAQ2uB6955Z+XTDLUtkyOHBzu/ZViMiBWfsQMki3pq7cFifGWARbG5QMNA6k764liYDl1bbMoF0Hifh9JC2LNPbII= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727866145; 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a=openpgp-sha256; l=2218; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=BB4R12hb6JJv+m+wU7R6gaxBtVYrpHfMfCCdOaNVhVc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/VR7pXuTMmWI1dz5P/0rJRftzznEdb7XzW3u7THfu9 qnVD5otO0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRZ7sY/nC3+v6yfXGLZ+6S xrl5LvOFDT+JsHXWS37dPPtXKdesKB9GhrsvP9jds1yvfTTPX+HuMX/n3LNWxs83TzT3zGQWk8t 5xw8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index f8a45e4f00a0d..08aa4fe03fd30 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells =3D <1>; }; =20 - clkcfg: clkcfg@20002000 { - compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks =3D <&refclk>; - #clock-cells =3D <1>; + mss_top_sysreg: syscon@20002000 { + compatible =3D "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg =3D <0x0 0x20002000 0x0 0x1000>; #reset-cells =3D <1>; }; =20 @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC0>; + resets =3D <&mss_top_sysreg CLK_MAC0>; status =3D "disabled"; }; =20 @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address =3D [00 00 00 00 00 00]; clocks =3D <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names =3D "pclk", "hclk"; - resets =3D <&clkcfg CLK_MAC1>; + resets =3D <&mss_top_sysreg CLK_MAC1>; status =3D "disabled"; }; =20 @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks =3D <&scbclk>; status =3D "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible =3D "microchip,mpfs-clkcfg"; + reg =3D <0x0 0x3e001000 0x0 0x1000>; + clocks =3D <&refclk>; + #clock-cells =3D <1>; + }; }; }; --=20 2.45.2