From nobody Thu Nov 28 08:29:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 291531940B0; Wed, 2 Oct 2024 16:11:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885519; cv=none; b=PrlSzcUauGBQSynnbianiIKJwhjrqicw1i++IPdkLMTMD5Tq4X7qEieFB5RwMbnD92Wzak/CzbYkPGsjs1Cr89gO7v3uhtXa59lODhgOAzl93/Uk1I2qkIuRe4M40vAAJ9bTYqYM3ai0wFbWL810gj4KZzldh1xkYLPJMDJYtkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885519; c=relaxed/simple; bh=2V7RQodDQlu18TItxPVAqFSEQ7zomNY1W4Cl2ro6hcY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ujsBwvOc+eorN/i8gXE1SNBNVlmH1eXpM1ZyeThixyjhMSLYb5w1Bxh9336hdstrWb0sRYlSFVWiBp2QBg4UFGHPpUqaHb+H6QGN8eR02wAPrdAiwj20WusLE9E5cvyecQXlS0r4bHlYlSFRmFc7h/6ih4Du4oiSMGbBEpo9X8w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XrXVaB5C; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XrXVaB5C" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 870DFC4CEC2; Wed, 2 Oct 2024 16:11:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727885518; bh=2V7RQodDQlu18TItxPVAqFSEQ7zomNY1W4Cl2ro6hcY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XrXVaB5CED/nhYA5Q/3Og8em4VXoI/axEVQ0pCdADT0T6RWOvU5KyDnLLxxTar0t0 QVp/upr2xZWCUA6xy783qWnyt61/MZtyGkwGqrlAgkJNsQ0A5AYeXuldH41EZvH3fH pWTC2a+NvLEZw447rCewKckVfvseLZ3WEYuZ269QrFcJ1q2pGSEUCAGsLUK8jTrwUY nt0dIGWOdifuiveeF8chOd8HZj/HUjwXiWR0LwEMlhnOogqsTo+Gew4DM6knHcDl9t IuahGUXbfHaGe0r/uG1bPmhGHJFzE9A2IEZ5Cqose4cZ2xR7yRpV11zX0yEa4Rc3Wz +iQ3KBNCgoBBw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v1 1/5] RISC-V: add vector crypto extension validation checks Date: Wed, 2 Oct 2024 17:10:54 +0100 Message-ID: <20241002-utensil-ought-744ce828d19c@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud> References: <20241002-defeat-pavestone-73d712895f0b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10624; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Rlx86YTL8DYCeziwBL4DaUepyEPqXhOxmfx2dG/JjxY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/C/oDJle7N5w0Yp3xuWDxnPQwG37ea5t/cbdW1U24s 8Ex/Vt8RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACayio2R4UVPmJb+p+7QtKQ5 z9cqLDE/8NQrtnuiMsvSLT5rQt6wJzD8Dzq07G+B9OO8za+aLmqf0d/pN1P4c4DPEuH1L5iZzy7 fxgoA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the vector crpyto extensions. Currently riscv_isa_extension_available() will return true on systems that support the extensions but vector itself has been disabled by the kernel, adding validation callbacks will prevent such a scenario from occuring and make the behaviour of the extension detection functions more consistent with user expectations - it's not expected to have to check for vector AND the specific crypto extension. The 1.0.0 Vector crypto spec states: The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn and Zvks-- require a Zve64x base, or application ("V") base Vector Extension. All of the other Vector Crypto Extensions can be built on any embedded (Zve*) or application ("V") base Vector Extension. and this could be used as the basis for checking that the correct base for individual crypto extensions, but that's not really the kernel's job in my opinion and it is sufficient to leave that sort of precision to the dt-bindings. The kernel only needs to make sure that vector, in some form, is available. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Link: https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0 Signed-off-by: Conor Dooley --- arch/riscv/include/asm/cpufeature.h | 3 + arch/riscv/kernel/cpufeature.c | 111 ++++++++++++++++++---------- 2 files changed, 76 insertions(+), 38 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 45f9c1171a486..1de408c3deee7 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -51,6 +51,9 @@ void riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ ARRAY_SIZE(_bundled_exts), NULL) +#define __RISCV_ISA_EXT_BUNDLE_VALIDATE(_name, _bundled_exts, _validate) \ + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ + ARRAY_SIZE(_bundled_exts), _validate) =20 /* Used to declare extensions that are a superset of other extensions (Zvb= b for instance) */ #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8f20607adb406..84a2ad2581cb0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,53 @@ static int riscv_ext_zicboz_validate(const struct risc= v_isa_ext_data *data, return 0; } =20 +static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *da= ta, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data= *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + if (IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + /* + * The kernel doesn't support systems that don't implement both of + * F and D, so if any of the vector extensions that do floating point + * are to be usable, both floating point extensions need to be usable. + */ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_dat= a *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + /* + * It isn't the kernel's job to check that the binding is correct, so + * it should be enough to check that any of the vector extensions are + * enabled, which in-turn means that vector is usable in this kernel + */ + //TODO check that enough resolve rounds exist to make this work + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32X)) + return -EINVAL; + + return 0; +} + static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -308,12 +355,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), - __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, - riscv_ext_zicbom_validate), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, - riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), @@ -339,40 +384,40 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zk, riscv_zk_bundled_exts, riscv_ext_vect= or_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zkn, riscv_zkn_bundled_exts, riscv_ext_ve= ctor_crypto_validate), __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), - __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zks, riscv_zks_bundled_exts, riscv_ext_ve= ctor_crypto_validate), __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), - __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), - __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), - __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), - __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), - __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), - __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), + __RISCV_ISA_EXT_DATA_VALIDATE(zvbc, RISCV_ISA_EXT_ZVBC, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve= 32f_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vec= tor_x_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve= 64d_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve= 64f_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve= 64x_exts, riscv_ext_vector_x_validate), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), - __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), - __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), - __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), - __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), - __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), - __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), - __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), - __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), - __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), - __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), - __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), - __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkb, RISCV_ISA_EXT_ZVKB, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkg, RISCV_ISA_EXT_ZVKG, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkn, riscv_zvkn_bundled_exts, riscv_ext_= vector_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvknc, riscv_zvknc_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkned, RISCV_ISA_EXT_ZVKNED, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkng, riscv_zvkng_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvknha, RISCV_ISA_EXT_ZVKNHA, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvks, riscv_zvks_bundled_exts, riscv_ext_= vector_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksc, riscv_zvksc_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvksed, RISCV_ISA_EXT_ZVKSED, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vecto= r_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), @@ -883,16 +928,6 @@ void __init riscv_fill_hwcap(void) riscv_v_setup_vsize(); } =20 - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { - /* - * ISA string in device tree might have 'v' flag, but - * CONFIG_RISCV_ISA_V is disabled in kernel. - * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. - */ - if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; - } - memset(print_str, 0, sizeof(print_str)); for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) --=20 2.45.2 From nobody Thu Nov 28 08:29:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A11801D0E1F; Wed, 2 Oct 2024 16:12:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885524; cv=none; b=Adf1utmbmnnhrkBaA0ueqyuo25tZW/l+/kZXEOStY+Jl/2SWQ31GArn5ymdTLCzxKrIMoeEn/AYZW5OcuYhHj3FvPuDxMD3ceqfmIA4SQv7YlH6OgrciQ0WVCkpIA8eb/vLtN+Has04nDGtNR7nFRmFjdCOZq8LZYMQ5Y8aBvy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885524; c=relaxed/simple; bh=mCRekBHgNwFBX1KL6AOZHvr9N4tmriuM/RvTA6+DVm4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o0pLlZyr2dI7wLiJTXSHL0UKvBe/PQrE3k/uMjq8Ej3p1aQEd2cJpaYKBrSHA9GOkR6XrfQlkjLhYZ/3DI8+n5QYecx3DuUoIq1BPQu5U61iyG2qkwi3kwv3q/0saWDzMWGUo67lIZXphjR5k1sg3TNmuoiaKgtQc+fT4Mu0oak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L2+ayXHh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L2+ayXHh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D83E8C4CECD; Wed, 2 Oct 2024 16:12:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727885524; bh=mCRekBHgNwFBX1KL6AOZHvr9N4tmriuM/RvTA6+DVm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L2+ayXHhUHPTjpTt4zczWxCqmEwZRf0lUqAhCKLgTv1C+CV+x5ZC4iHkqVY57zvb1 56su9G7BVXOlnkE5Pja9an0r74+kM/pXmKK4WaHNQCPAz+Fmn6Vs431gBlfmRecWti 0SxdL2k/acijFAKrRPctzPMvRon4hLuik0YEn2UxLWaqQuByCFpYHCiPCTJBmHL1Y+ 4u0YDRLBgDkO9CRMryfxb5mWrt9k/DNLsRoO8D+NOiZItjO2v2CsmpaKP32RH8qBWT sjnZryNz41EOCsOl+n8cTBdDD9Q3B1Vav1iqrsnDIAK9USZJLr50hgyHBI2uEoumWq 1iV8G+kKgIHTA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v1 2/5] RISC-V: add f & d extension validation checks Date: Wed, 2 Oct 2024 17:10:55 +0100 Message-ID: <20241002-stuffed-trance-1323386dd80b@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud> References: <20241002-defeat-pavestone-73d712895f0b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2979; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=xf019LNZCscq0WBMmHr1I5lt/oOvG/GepcaYsq7GDK8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/C/rF/wSseBJ8bplFDMueWds53hmbbDvbfkr7ofC/0 6xSug+LOkpZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRyz8ZGSYKK63+uab/k2ft rYlFF9Ms/t11XNMck/63fWFOz7aWUFuG/6WhgqGFXKeWnNW4dTPpbtnONzvev91wZlZYn+2hRe5 nsvgA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the floating point extensions. The check for "d" might be slightly confusingly shorter than that of "f", despite "d" depending on "f". This is because the requirement that a hart supporting double precision must also support single precision, should be validated by dt-bindings etc, not the kernel but lack of support for single precision only is a limitation of the kernel. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 84a2ad2581cb0..b8a22ee76c2ef 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,29 @@ static int riscv_ext_zicboz_validate(const struct risc= v_isa_ext_data *data, return 0; } =20 +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { + pr_warn_once("This kernel does not support systems with F but not D\n"); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *da= ta, const unsigned long *isa_bitmap) { @@ -351,8 +374,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), - __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), - __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), @@ -912,15 +935,6 @@ void __init riscv_fill_hwcap(void) } } =20 - /* - * We don't support systems with F but without D, so mask those out - * here. - */ - if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)= ) { - pr_info("This kernel does not support systems with F but not D\n"); - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; - } - if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This cannot fail when called on the boot hart --=20 2.45.2 From nobody Thu Nov 28 08:29:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE551D1319; Wed, 2 Oct 2024 16:12:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885529; cv=none; b=t9xOGDugisfgD0nW+2blwgBL6kzQ2dZxEivpSYIM6GYd+oKTYCezwcHKz8NXUsXamX/Km4rOAQIpyMRYmskaUxG4v9ZYarfIvnMcJ4PLpwLwvp2LTQPYgrpTcTUgfF5uBksNzYI9thJpfMyI5n1y9xqjLdyGbQHJRdX26bAUa1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885529; c=relaxed/simple; bh=A0ybPXTauo3eopVMr548or5pJojT5HcHFGdg3+1LGss=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HU9lJ1IwaQul6Gmf/0EhYQSfRysRi4UIMTw/eouY1BkoCha0udHG9qJA9Kz28gprnN1+/ORoMJZdI0dZ8SR1qUHR0OvrVH6Er/mD1MNAR35Mb3d7UPQjjepYg/3AWZul4oJM1PsJkjUBscORMd8r2TacTCKHx6aHPMeaMngiKbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cgeSlCGz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cgeSlCGz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C027CC4CECD; Wed, 2 Oct 2024 16:12:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727885529; bh=A0ybPXTauo3eopVMr548or5pJojT5HcHFGdg3+1LGss=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cgeSlCGztSM2uY6msbBtrEbcKNdXBO4Qi8QZ2WOB/c0rzr/lDnjQqylxrP0Ac1ftd KFsaVKFqbqNeMen4CUQc8zXtF7S+jh+9K3zODUYj15WUlHyVbPa3dUaq851W85i7mG XbYyTB9FPI7jnrkWyAd+CTZpLb0oweQhDkBGx9mVi0oDHeR91Vq3cKtxxSJ8lNVYBE 2eqA+ba9UkdS/dq0hO9fr5MkDyaiLF09OxQ7Khvs6ptJpC+mhyUiXTjkkxlaNIY+yt o9ub8hu+QPnYXKllYSBy+G/TIRRJm2HCpAHJMX6DnzzEW8Hh4n6jNSSdRskjuYOz5U U34RzHRe4YrNw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v1 3/5] dt-bindings: riscv: d requires f Date: Wed, 2 Oct 2024 17:10:56 +0100 Message-ID: <20241002-deliverer-recite-2c5a05f50721@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud> References: <20241002-defeat-pavestone-73d712895f0b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1090; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=9IUjV4XrSlnqf+oDMep1HvXRpMwxZk7xWRthmNV0yIU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/Cya8DbpyT2Vp46G40F+7LI+IKCaqCn3+2rrLkun79 3NVux9ZdJSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiD/8w/DO1tlndwuS5gKf5 4P2Fqv657TOuPryf+6bvVubye8zSqgoM/5Nk/QruvvfMEf9qnsrseOLjD/s0ebfKjTdmB2RznXk pywgA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Per the specifications, the d extension for double-precision floating point operations depends on the f extension for single-precious floating point. Add that requirement to the bindings. This differs from the Linux implementation, where single-precious only is not supported. Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b49289..779f5cfab806e 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -564,6 +564,12 @@ properties: https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 allOf: + - if: + contains: + const: d + then: + contains: + const: f # Zcb depends on Zca - if: contains: --=20 2.45.2 From nobody Thu Nov 28 08:29:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282E51D0F40; Wed, 2 Oct 2024 16:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885534; cv=none; b=l3gxPb4/U9J8unps6tX74YGiGaLBml0F3nl9PkpNYdUDy5vgPPYnFd0ZG6Ev9TFw1IBr6uIURl6Hg+q81QSANDxQmE+bGEGGDZLdoKCpaZuBao4KXDEFMTIxusTh094KTbL3qBMVU9ueC/phi8x1+GgFxCpca2v4CV//89Bmw6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885534; c=relaxed/simple; bh=eGNgKeEbgQZhlP5/rBYHyxG3CCVZQ0AAqZnzmPdtdiM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LYRIRUfHi7zZEKoEeWxor8OfheVrAS71kXWYN6ijwzpEnNsrkEoWYB65ABbck1qrwUfSMyRu+5ziuO5hsruRvGouay7PIs7DoCCOmU0BzUXtZOX5E/WZvtyHf5M2gVXglZyUmiOi172Vxs+C/5LYkqd4bFKR2qOKAvKQv46Hu/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tnq9ps47; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tnq9ps47" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8F6DEC4CED2; Wed, 2 Oct 2024 16:12:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727885534; bh=eGNgKeEbgQZhlP5/rBYHyxG3CCVZQ0AAqZnzmPdtdiM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tnq9ps474zl9kcOUnvAVfU2YsrJMrat4YjA1CUovrMQSb+AwqFZvWnKv+JXM4pCtO j5ta39uX82oghC1IuFobvtRioh+AcU+ghBgZ8qg+YcKKJxhdRmx/jJKyu1SmPAcdrC lPL6hW8TsEIDgHHC+lZhtf9qU+89jL2ckL5RUVjfn/91pDXNeUrkNIFVya2uuDa0zo +jSniu8tZ2WZqtyTQiTP78+xJ1ASEhMcIhlBTwc6tJixqGiTlDV12gWrTQJtQJAcqt DPjg8lQ9xeYoQtIzfEhPcnl1eEpuU5CKOc6213xce5xHfkzV+SUJTiNxsWj5AtqhGm vxQeLaNWTpRZg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v1 4/5] dt-bindings: riscv: add vector sub-extension dependencies Date: Wed, 2 Oct 2024 17:10:57 +0100 Message-ID: <20241002-eagle-fresh-4b2e259e45ee@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud> References: <20241002-defeat-pavestone-73d712895f0b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2218; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=YIm6fXkkXwfBUiAT+70BG7jJ6bMEmlZ2jL6v+Po7WK8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/CyY0Zoc48mS6G21S1XxefMrtmenFKQyKSqaFz+umR bh86WvvKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwES4XzIyrP+5KeX87tPv9z/s NjrFd/HKDu1jRsszzUO/FlbGFsl9OM3IsOU2T0wIr6gn16pkD1Pe468u85z7wHPEMkZx8lmB+9+ fsAIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Section 33.18.2. Zve*: Vector Extensions for Embedded Processors in [1] says: | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve6= 4f extension depends | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the = Zve64f extension | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64= f extensions depend | upon the F extension | The Zve64d extension depends upon the D extension Apply these rules to the bindings to help prevent invalid combinations. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-rele= ase-698e64a-2024-09-09 [1] Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Cl=C3=A9ment l=C3=A9ger --- .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 779f5cfab806e..abf2579171c5b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -605,6 +605,52 @@ properties: contains: const: zca =20 + - if: + contains: + const: zve32x + then: + contains: + const: zicsr + + - if: + contains: + const: zve32f + then: + allOf: + - contains: + const: f + - contains: + const: zve32x + + - if: + contains: + const: zve64x + then: + contains: + const: zve32x + + - if: + contains: + const: zve64f + then: + allOf: + - contains: + const: f + - contains: + const: zve32f + - contains: + const: zve64x + + - if: + contains: + const: zve64d + then: + allOf: + - contains: + const: d + - contains: + const: zve64f + allOf: # Zcf extension does not exist on rv64 - if: --=20 2.45.2 From nobody Thu Nov 28 08:29:30 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4DCE1D1515; Wed, 2 Oct 2024 16:12:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885539; cv=none; b=Rg3zpCLGIPewwAFtzDrfBYVkKRFcP18dqV8IOnFe63USHI8lsmVJlPfRwMuRknZgP1ohLJ0kiEd/T+boCfLINdUXXFunw0DcWnhctUkxIvCTqRUubaFsqTOGkHVCgMiCzy8GhSmaCkmgDkPF/a/VdLKCe0VMdLoCwQmVLBtfdfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727885539; c=relaxed/simple; bh=UOs9fQ0Qb/dPq24ntgo5+/lHqCBltfzgg+ulESJu13k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uYCP2P9KKQ4n5Am3wIBizdk3tK9z1mpJI5VGrhvsSyInuXnEzEsvEb212qn0mrZFxfY9vsQv1dZ4oy1A3q9gXljyo3/B+4I5X0X6u8KhjaLqWSht5xCnyr19mq6ydRRRKaW/jP2UgcxTs8qeelLiNqWqERHkqanGR0lfri3dS/c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SD8kvVnO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SD8kvVnO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3042FC4CECD; Wed, 2 Oct 2024 16:12:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727885538; bh=UOs9fQ0Qb/dPq24ntgo5+/lHqCBltfzgg+ulESJu13k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SD8kvVnOSrKOvT28i1yXRDH8GlU0eANdP6Xef3VAzTlWfKRWouCVkzxZxV5xBs7xc 607vzEqP/iQBDEt8FftIeDWh3OtyyCaz9/Uh79IfOYB/3dt19TGsL8LtjrxdrPVlul iMYVGxg81pTvITejQsP93VmEAxwfUjhn0sNhSHgE38bAllXRcQgZzASxHmFYbE610f tdM+2C3RO040LAqjTtM+6OoCF82lrFRk6IJxnWTUVveHiGb5/TlUWQQoPb3jucKdn/ 4mxAHcr6uqy0kdO2+svFn+QfMliNTgqBgRAws1DqOk2RfLbSovwvb95TaZX6943R3Z XJMSfUvtwcOaw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC v1 5/5] dt-bindings: riscv: document vector crypto requirements Date: Wed, 2 Oct 2024 17:10:58 +0100 Message-ID: <20241002-sincerity-urgent-acdb0e8d8a66@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241002-defeat-pavestone-73d712895f0b@spud> References: <20241002-defeat-pavestone-73d712895f0b@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1973; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=0csTQ3dN/Nqy674iSwkezo4Jzd5QbE3DDkc2MwbnXzc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGl/CybsehZ2KKB10qJJ7dWVbjMfLZnbNYHLxnGp+45jl 3PubTmR1lHKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJCMcx/BVdpP3DzO/yA5ce LU/e32c2sz/TNOiz+7Qyf9LXo7+UJ21k+O+3UUv0FuMK36YJm82+5zgpB31xd1t2zuGfqXrYkle O0dwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Section 35.2. Extensions Overview of [1] says: | The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the compos= ite extensions Zvkn and | Zvks-- (sic) require a Zve64x base, or application ("V") base Vector Exte= nsion. | All of the other Vector Crypto Extensions can be built on any embedded (Z= ve*) or application ("V") base | Vector Extension Apply these rules in the binding, so that invalid combinations can be avoided. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-rele= ase-698e64a-2024-09-09 [1] Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index abf2579171c5b..02b822bbf341d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -651,6 +651,38 @@ properties: - contains: const: zve64f =20 + - if: + contains: + anyOf: + - const: zvbc + - const: zvkn + - const: zvknhb + - const: zvks + then: + contains: + anyOf: + - const: v + - const: zve64x + + - if: + contains: + anyOf: + - const: zvbb + - const: zvkb + - const: zvkg + - const: zvkned + - const: zvknha + - const: zvksed + - const: zvksh + - const: zvknc + - const: zvkng + - const: zvkt + then: + contains: + anyOf: + - const: v + - const: zve32x + allOf: # Zcf extension does not exist on rv64 - if: --=20 2.45.2