From nobody Thu Nov 28 12:42:04 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB9DC1CB334 for ; Tue, 1 Oct 2024 16:10:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799060; cv=none; b=rGLTP7ybjFZNwMebC2qMshhbctS+xOQqKBh0BsN7Wtv6ZCztk0f/G6wRBOIeUR+C6LiO+3jhyoFQv/PRWpe3abAQlwc7k7ODHtV2NezsTA3l4EOCf3kq1uEZ+WPQznENnPl34SrSbyM/Btdx30+y+QSCNtz5UKoTxCgQxx044mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799060; c=relaxed/simple; bh=020IFNVs8v20nR2gGfIY28qsRD6d12oC/VrgjCyMxCs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VAmnYe9oARmpiI7bsRlWA+ryiOYxrdgIf5Ob30Toe7LykJe99XVSF1W4891L7canofAnwwnhBbJyk2RxO6+D0HYijiSnjcOfovyKkAp9xjLp1T6RTzfgl4N3WmK3LV8/pgN2/bGInK3sErgjk8RIjzMJvCQF6KEd8+EzjWlInbI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U1dnFUCr; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U1dnFUCr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727799058; x=1759335058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=020IFNVs8v20nR2gGfIY28qsRD6d12oC/VrgjCyMxCs=; b=U1dnFUCrc+7D+osj6C1Y6nPrKVkqC2nHrQ3lgXDtE+afQmA6Jg+TgXgS HgEW6KzVUeEDkt4grKQG8DpN6Y+RKUtBid+YcVAatdsPyS1jhMmKW2C5t GJYkLtqe89CcFTHDnsIuj7dTO0BeeBe6JIpIs/m/k1/aYC2/kUI2yALS1 BgyzGqDOVW8KAIuUR0tC13O/pI3BZQMoGJPxjNyP2HZls0e3jsXTh96vq ajh6SfRu23j858PMoSCV+OKV9YdoVCDCL3InWvMNPmxQxE0BDpFtBdfPi 7SDl9JawfmP+IEpBLAXp2aY4XLUFU4BED/xxgUj3Z6vADvKBNbFTKPzM4 A==; X-CSE-ConnectionGUID: BUJsndZ6TBuu3yS5KJ1cQw== X-CSE-MsgGUID: bgSNlx8wRCqqcwKvQ1TQJw== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="37539371" X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="37539371" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 09:10:58 -0700 X-CSE-ConnectionGUID: UrsGFBloSKiKd0F25IFIiQ== X-CSE-MsgGUID: H5v3WwTlRGCf6MYULlAtoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="78585972" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:10:58 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com, Yan Hua Wu , William Xie , Ashok Raj Subject: [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation Date: Tue, 1 Oct 2024 09:10:36 -0700 Message-Id: <20241001161042.465584-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, an unconditional cache flush is performed during every microcode update. Although the original changelog did not mention a specific erratum, this measure was primarily intended to address a specific microcode bug, the load of which has already been blocked by is_blacklisted(). Therefore, this cache flush is no longer necessary. Additionally, the side effects of doing this have been overlooked. It increases CPU rendezvous time during late loading, where the cache flush takes between 1x to 3.5x longer than the actual microcode update. Remove native_wbinvd() and update the erratum name to align with the latest errata documentation: https://cdrdv2.intel.com/v1/dl/getContent/334165 # Document 334163 Version 022US Fixes: 91df9fdf5149 ("x86/microcode/intel: Writeback and invalidate caches = before updating microcode") Reported-by: Yan Hua Wu Reported-by: William Xie Signed-off-by: Chang S. Bae Tested-by: Yan Hua Wu Acked-by: Ashok Raj --- The original patch [1] was posted earlier, with a cover letter [2] providing context on the prior investigation into the cache flush. Changes in this revision include: * Added Ashok's acknowledgment tag * Corrected the subject prefix * Included the link to the errata documentation in the changelog * Refined the changelog This fix is particularly relevant to staging, as the cache flush was found to significantly increase latency during staged late loading. [1]: https://lore.kernel.org/all/20240701212012.21499-2-chang.seok.bae@inte= l.com/ [2]: https://lore.kernel.org/all/20240701212012.21499-1-chang.seok.bae@inte= l.com/ --- arch/x86/kernel/cpu/microcode/intel.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 815fa67356a2..f3d534807d91 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -319,12 +319,6 @@ static enum ucode_state __apply_microcode(struct ucode= _cpu_info *uci, return UCODE_OK; } =20 - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); =20 @@ -574,14 +568,14 @@ static bool is_blacklisted(unsigned int cpu) /* * Late loading on model 79 with microcode revision less than 0x0b000021 * and LLC size per core bigger than 2.5MB may result in a system hang. - * This behavior is documented in item BDF90, #334165 (Intel Xeon + * This behavior is documented in item BDX90, #334165 (Intel Xeon * Processor E7-8800/4800 v4 Product Family). */ if (c->x86_vfm =3D=3D INTEL_BROADWELL_X && c->x86_stepping =3D=3D 0x01 && llc_size_per_core > 2621440 && c->microcode < 0x0b000021) { - pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%= x) disabled.\n", c->microcode); + pr_err_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%= x) disabled.\n", c->microcode); pr_err_once("Please consider either early loading through initrd/built-i= n or a potential BIOS update.\n"); return true; } --=20 2.43.0 From nobody Thu Nov 28 12:42:04 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF59E1CB510 for ; Tue, 1 Oct 2024 16:10:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799061; cv=none; b=CvZkrlUVKTTveoIoy98dT9VjZ9qXgzfFS9LouOrgsPkAIakZEbpqZ5eZOuRDQBShEeI5wdKw61uTnUt1iG0vuFALO/wpxyvZExINI++9L64SAtVAfP0oQP9Vx4JKRwRwaLDRooKT7IadQFo/Yq80DwZOqlOgKC9NNbAH5bRR35k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799061; c=relaxed/simple; bh=ET7LCZjp+V8sCzKXv4bUaKBKMigRm+R+exMxJAqpbpk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=srXrYa9tGDPTqRhdGq7BAje609O3P9w535JlgQvMxr+tfSNzQCrJgdmCtgT/0t1dhghbSm2epoUb3z88nMdHv3Q3foxtEB2cV9WKrQDQf/Ux3yJj/znDroE3+/zn6Ce9vbWpaOyQbsIkoLEkuiW4MvaI6MPAe+i0vRUCH3w+9QA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kF74BxWc; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kF74BxWc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727799060; x=1759335060; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ET7LCZjp+V8sCzKXv4bUaKBKMigRm+R+exMxJAqpbpk=; b=kF74BxWcGg8jQqdfawueK18noreFEhDyR6gof9Xb2lCclsb4xE0KDHKM IpCjJ6XwH2R3QfgCcYYayhwmB390ap1zmLLjw1jAi1BvNUV/OnbAvAJnR OkUFUU5Dc/V+jNmeo+IInyCOIrKIDZI1hzx/FCi/djVyPTcmvs2HVJ7s2 2pav684QFtbTNq+rgUxuyT91ErJFg/CURrUI4CYtopeibYdC1wMr2xHCy jMTL0N1b9BMlaQ9WXXF8WoCPqq1DatMhE2/Mz+F+FII2ca0PzpscZKCd0 HUROfaqS4vNRO0I/RlRIN9YJSMUyKiH1iOUkZZMjU+iqyVKjR4sgPdBXh Q==; X-CSE-ConnectionGUID: wRNcPDZnR9qyU88/N9nbxA== X-CSE-MsgGUID: KeWzqHmDRgKRhErTZ74YeA== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="37539377" X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="37539377" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 09:10:59 -0700 X-CSE-ConnectionGUID: CxthUq3XSveLt2iQHoO5Pg== X-CSE-MsgGUID: r8cJ5EpzTQCZSNbT+o+4ww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="78585980" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:11:00 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC 2/7] x86/microcode: Introduce staging option to reduce late-loading latency Date: Tue, 1 Oct 2024 09:10:37 -0700 Message-Id: <20241001161042.465584-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As microcode patch sizes continue to grow, the latency during late-loading can spike, leading to timeouts and interruptions in running workloads. This trend of increasing patch sizes is expected to continue, so a foundational solution is needed to address the issue. To mitigate the problem, a new staging feature is introduced. This option processes most of the microcode update (excluding activation) on a non-critical path, allowing CPUs to remain operational during the majority of the update. By moving most of the work off the critical path, the latency spike can be significantly reduced. Integrate the staging process as an additional step in the late-loading flow. Introduce a new callback for staging, which is invoked after the microcode patch image is prepared but before entering the CPU rendezvous for triggering the update. Staging follows an opportunistic model: it is attempted when available. If successful, it reduces CPU rendezvous time; if not, the process falls back to the legacy loading, potentially exposing the system to higher latency. Extend struct microcode_ops to incorporate staging properties, which will be updated in the vendor code from subsequent patches. Signed-off-by: Chang S. Bae --- Whether staging should be mandatory is a policy decision that is beyond the scope of this patch at the moment. For now, the focus is on establishing a basic flow, with the intention of attracting focused reviews, while deferring the discussion on staging policy later. In terms of the flow, an alternative approach could be to integrate staging as part of microcode preparation on the vendor code side. However, this was deemed too implicit, as staging involves loading and validating the microcode image, which differs from typical microcode file handling. --- arch/x86/kernel/cpu/microcode/core.c | 12 ++++++++++-- arch/x86/kernel/cpu/microcode/internal.h | 4 +++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index b3658d11e7b6..4ddb5ba42f3f 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -676,19 +676,27 @@ static bool setup_cpus(void) =20 static int load_late_locked(void) { + bool is_safe =3D false; + if (!setup_cpus()) return -EBUSY; =20 switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { case UCODE_NEW: - return load_late_stop_cpus(false); + break; case UCODE_NEW_SAFE: - return load_late_stop_cpus(true); + is_safe =3D true; + break; case UCODE_NFOUND: return -ENOENT; default: return -EBADFD; } + + if (microcode_ops->use_staging) + microcode_ops->staging_microcode(); + + return load_late_stop_cpus(is_safe); } =20 static ssize_t reload_store(struct device *dev, diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 21776c529fa9..cb58e83e4934 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,10 +31,12 @@ struct microcode_ops { * See also the "Synchronization" section in microcode_core.c. */ enum ucode_state (*apply_microcode)(int cpu); + void (*staging_microcode)(void); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); unsigned int nmi_safe : 1, - use_nmi : 1; + use_nmi : 1, + use_staging : 1; }; =20 struct early_load_data { --=20 2.43.0 From nobody Thu Nov 28 12:42:04 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F8C11CCB29 for ; Tue, 1 Oct 2024 16:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799063; cv=none; b=Do+Iz7qA0OzrC1yhyhRvQA3Njpr4ChOjjPdAClvOqMJdVzHVjjEzEg4tvoI5wDhQ8a1/5/jk8C43Ahk64fd1EruMQfsj+PGmwXy3NHvtJaYQR+ZjSlBDQx3THlz/AGVD6lMx0MhiGj2UMSn/igfbNPjYBvumxidQ32yyB/BTc/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799063; c=relaxed/simple; bh=HjFxiO3WVk8mwE4QkGACUCunEYQwJJOVvDqryVYukaE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JDW0EF/r/Zmep8huS/L4bC3kPfLoNih/uGaerAfyviFZhYRVsrXIvDBEQzU4snpOPjqZq/+dk/PG3r1Ah4wqvmsghWy/bXhqDEP0pNWQNOomA5VOEy9PsldJU0ZqHtJ9Y1dMXqiDcFqOi4jNJnjymQyB1MHT25sCnOwi6Lh4ktc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=UmIkRLSM; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UmIkRLSM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727799061; x=1759335061; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HjFxiO3WVk8mwE4QkGACUCunEYQwJJOVvDqryVYukaE=; b=UmIkRLSMHulLc9tZBjrfzWfT/14uwMEoOyxVx5LxRmaBaJ89eauOX2Pc 5j1o5eOnwy6YF9l6waG6iyQK1Eenx4pN8znYO+wiCz5faoQ7yn1TI1bZ9 7oKHIN95CPI3OoFZV6WSvco0cgPzrx/fg+RtflxVd0BEc+99jPhd3Wm4V Y0+yV/Ub7qMBnzxZhl+3hJWn2w1h05zER3IR27cHCnRCblbOhdKvBzllh 4HjX5wxAR7gnYcvg9SLJSJfmXV+kMKQMzCoSG8ocEFlFgOGvF+JPDKCI+ YLPMSYMExeiH6ipdgzWTaRe/yJjIMV23qzB7Olp8aBJRv2p+nJHhNtW1s Q==; X-CSE-ConnectionGUID: et4nnwtlREOjDmwOGLFYrQ== X-CSE-MsgGUID: E1O1MlCdTxO1aUHarrfCxQ== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="37539383" X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="37539383" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 09:11:00 -0700 X-CSE-ConnectionGUID: 9RDTAcOxREmi2M+hA0ONYQ== X-CSE-MsgGUID: Z/PZhaeeSpSkvBQXDB5iHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="78585984" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:11:01 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC 3/7] x86/msr-index: Define MSR index and bit for the microcode staging feature Date: Tue, 1 Oct 2024 09:10:38 -0700 Message-Id: <20241001161042.465584-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The microcode staging feature involves two key MSR entities, the presence of which is indicated by bit 16 of IA32_ARCH_CAPABILITIES: * Bit 4 in IA32_MCU_ENUMERATION shows the availability of the microcode staging feature. * Staging is managed through MMIO registers, with IA32_MCU_STAGING_MBOX_ADDR MSR specifying the physical address of the first MMIO register. Define the MSR index and bit assignments, helping the upcoming staging code to make use of the hardware feature. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/msr-index.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3ae84c3b8e6d..2840a2fe340b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -164,6 +164,10 @@ * Processor MMIO stale data * vulnerabilities. */ +#define ARCH_CAP_MCU_ENUM BIT(16) /* + * Indicates the presence of microcode update + * feature enumeration and status information + */ #define ARCH_CAP_FB_CLEAR BIT(17) /* * VERW clears CPU fill buffer * even on MDS_NO CPUs. @@ -884,6 +888,11 @@ #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b =20 +#define MSR_IA32_MCU_ENUMERATION 0x0000007b +#define MCU_STAGING BIT(4) + +#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5 + /* Intel SGX Launch Enclave Public Key Hash MSRs */ #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D --=20 2.43.0 From nobody Thu Nov 28 12:42:04 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39E221CCB3B for ; Tue, 1 Oct 2024 16:11:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799063; cv=none; b=LQ2GW2yhEU6UlZbf0fJmcFSLLADFFTDjojNb4orruAwwef34rmMF8RpZ4jxW+BjQQv1GCi3V/8EblXKvKLqFder7Uz5j2fMCH+9oz5Eb7JDYCuazFv5mlfpE0vT7KXLTJyd9gVio7DM3OnAarBzWXpcuF9HlQWLMvs9rasi5GHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799063; c=relaxed/simple; bh=GEw4i2sw/lvYbQl7umLqQFJk+Qso2Qgb1x2/tZS8Tv8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eAHSWlx1LmBLKguu/yF+1o5Xelvgl8ce8irSSxLWxBjVZ6x92cGJNNyWkCdEMZ+koswX8HkO5xK7R/QWxqMSYDaz/rWZwIFsyqzStUAT2/agFUuaI191QecVRLIIJ1dD2EShwjx/pm7YlNBjK4JAWEgntg9lW3f2vxWk37YXaWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TCWUtAAp; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TCWUtAAp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727799062; x=1759335062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GEw4i2sw/lvYbQl7umLqQFJk+Qso2Qgb1x2/tZS8Tv8=; b=TCWUtAApgG2roLUkx5GMjr/GPxfzxM9+HEbCAZ7z41ES/I4lKiU7mFTg qa3XNGRCCPATN0oHm12llOapu0qnHlVlg+jzJ49dbJhAlNpX4l79BfblZ VK290nyf1/dBCFroui4ExAjeyLU6S1GMihMDa21xbxV4ATBDzIQ8ujvl8 uBCKxZ+0oyC8RZ6And5QAJfXNeZ5/iE2rqvHNATD2ud9IXQC8E+T5gcxd OE1Qu9m8AkGcnDp1AGBpvtBLD1oDwioYB/5xjJgg9zKdwa63yFiApxoC+ UbIkS9BR8VjWEdJplTI/+25HrXxWM4kSoW0Qc1mEWXD/n1aeoQO29TjKV Q==; X-CSE-ConnectionGUID: RVzhF5ziSf2IwXCsqbAXpQ== X-CSE-MsgGUID: intSRL8rSs6O7Vjn6MVQaA== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="37539389" X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="37539389" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 09:11:02 -0700 X-CSE-ConnectionGUID: gUdkz1ZNTrGyWTIOizE/9w== X-CSE-MsgGUID: 6dRYHtK8SrS3786Uaf5yFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="78585989" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:11:02 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Date: Tue, 1 Oct 2024 09:10:39 -0700 Message-Id: <20241001161042.465584-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When microcode staging is initiated, operations are carried out through an MMIO interface. Each interface is independently discoverable per CPU via the IA32_MCU_STAGING_MBOX_ADDR MSR, which points to a set of dword-sized registers. Software must first ensure the microcode image is dword-aligned, then proceed to stage the update for each exposed MMIO space as specified. Follow these two steps to arrange staging process. Identify each unique MMIO interface by iterating over the CPUs and reading the MSR for each one. While this process can be tedious, it remains simple enough and acceptable in the slow path. Suggested-by: Dave Hansen Signed-off-by: Chang S. Bae --- Note: 1. Initially, a per-package and parallel staging invocation approach was considered, but it seemed overly complex. Dave helped to identify a simpler way. 2. Ideally, the staging_work() function would be as simple as a single WRMSR execution. If this were the case, the staging flow could be completed with this patch. From this perspective, the software handling for interacting with the staging firmware has been separated from this vendor code and moved into a new file dedicated to staging logic. --- arch/x86/kernel/cpu/microcode/intel.c | 50 ++++++++++++++++++++++++ arch/x86/kernel/cpu/microcode/internal.h | 5 +++ 2 files changed, 55 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index f3d534807d91..03c4b0e7e97c 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -299,6 +299,55 @@ static __init struct microcode_intel *scan_microcode(v= oid *data, size_t size, return size ? NULL : patch; } =20 +static inline u64 staging_addr(u32 cpu) +{ + u32 lo, hi; + + rdmsr_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &lo, &hi); + return lo | ((u64)hi << 32); +} + +static bool need_staging(u64 *mmio_addrs, u64 pa) +{ + unsigned int i; + + for (i =3D 0; mmio_addrs[i] !=3D 0; i++) { + if (mmio_addrs[i] =3D=3D pa) + return false; + } + mmio_addrs[i] =3D pa; + return true; +} + +static void staging_microcode(void) +{ + u64 *mmio_addrs, mmio_pa; + unsigned int totalsize; + int cpu; + + totalsize =3D get_totalsize(&ucode_patch_late->hdr); + if (!IS_ALIGNED(totalsize, sizeof(u32))) + return; + + mmio_addrs =3D kcalloc(nr_cpu_ids, sizeof(*mmio_addrs), GFP_KERNEL); + if (WARN_ON_ONCE(!mmio_addrs)) + return; + + for_each_cpu(cpu, cpu_online_mask) { + mmio_pa =3D staging_addr(cpu); + + if (need_staging(mmio_addrs, mmio_pa) && + !staging_work(mmio_pa, ucode_patch_late, totalsize)) { + pr_err("Error: staging failed.\n"); + goto out; + } + } + + pr_info("Staging succeeded.\n"); +out: + kfree(mmio_addrs); +} + static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, u32 *cur_rev) @@ -627,6 +676,7 @@ static struct microcode_ops microcode_intel_ops =3D { .collect_cpu_info =3D collect_cpu_info, .apply_microcode =3D apply_microcode_late, .finalize_late_load =3D finalize_late_load, + .staging_microcode =3D staging_microcode, .use_nmi =3D IS_ENABLED(CONFIG_X86_64), }; =20 diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index cb58e83e4934..06c3c8db4ceb 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -120,6 +120,11 @@ void load_ucode_intel_bsp(struct early_load_data *ed); void load_ucode_intel_ap(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); +static inline bool staging_work(u64 mmio_pa, void *ucode_ptr, unsigned int= totalsize) +{ + pr_debug_once("Need to implement the Staging code.\n"); + return false; +} #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(struct early_load_data *ed) { } static inline void load_ucode_intel_ap(void) { } --=20 2.43.0 From nobody Thu Nov 28 12:42:04 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 722331CCB5C for ; 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a="37539394" X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="37539394" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 09:11:03 -0700 X-CSE-ConnectionGUID: vYPBXhLqQwOIe20TPOdLVQ== X-CSE-MsgGUID: dv483kGfQRy7xeTKUK0RVw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="78585997" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:11:03 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC 5/7] x86/microcode/intel_staging: Implement staging logic Date: Tue, 1 Oct 2024 09:10:40 -0700 Message-Id: <20241001161042.465584-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The staging firmware operates through a protocol via the MMIO interface. The protocol defines a serialized sequence that begins by clearing the hardware with an abort request. It then proceeds through iterative process of sending data, initiating transactions, waiting for processing, and reading responses. To facilitate this interaction, follow the outlined protocol. Refactor the waiting code to manage loop breaks more effectively. Data transfer involves a next level of detail to handle the mailbox format. While defining helpers, leave them empty for now. Signed-off-by: Chang S. Bae --- arch/x86/kernel/cpu/microcode/Makefile | 2 +- arch/x86/kernel/cpu/microcode/intel_staging.c | 105 ++++++++++++++++++ arch/x86/kernel/cpu/microcode/internal.h | 6 +- 3 files changed, 107 insertions(+), 6 deletions(-) create mode 100644 arch/x86/kernel/cpu/microcode/intel_staging.c diff --git a/arch/x86/kernel/cpu/microcode/Makefile b/arch/x86/kernel/cpu/m= icrocode/Makefile index 193d98b33a0a..a9f79aaffcb0 100644 --- a/arch/x86/kernel/cpu/microcode/Makefile +++ b/arch/x86/kernel/cpu/microcode/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only microcode-y :=3D core.o obj-$(CONFIG_MICROCODE) +=3D microcode.o -microcode-$(CONFIG_CPU_SUP_INTEL) +=3D intel.o +microcode-$(CONFIG_CPU_SUP_INTEL) +=3D intel.o intel_staging.o microcode-$(CONFIG_CPU_SUP_AMD) +=3D amd.o diff --git a/arch/x86/kernel/cpu/microcode/intel_staging.c b/arch/x86/kerne= l/cpu/microcode/intel_staging.c new file mode 100644 index 000000000000..9989a78f9ef2 --- /dev/null +++ b/arch/x86/kernel/cpu/microcode/intel_staging.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#define pr_fmt(fmt) "microcode: " fmt +#include +#include + +#include "internal.h" + +#define MBOX_REG_NUM 4 +#define MBOX_REG_SIZE sizeof(u32) + +#define MBOX_CONTROL_OFFSET 0x0 +#define MBOX_STATUS_OFFSET 0x4 + +#define MASK_MBOX_CTRL_ABORT BIT(0) + +#define MASK_MBOX_STATUS_ERROR BIT(2) +#define MASK_MBOX_STATUS_READY BIT(31) + +#define MBOX_XACTION_LEN PAGE_SIZE +#define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2) +#define MBOX_XACTION_TIMEOUT (10 * MSEC_PER_SEC) + +#define STAGING_OFFSET_END 0xffffffff + +static inline void abort_xaction(void __iomem *base) +{ + writel(MASK_MBOX_CTRL_ABORT, base + MBOX_CONTROL_OFFSET); +} + +static void request_xaction(void __iomem *base, u32 *chunk, unsigned int c= hunksize) +{ + pr_debug_once("Need to implement staging mailbox loading code.\n"); +} + +static enum ucode_state wait_for_xaction(void __iomem *base) +{ + u32 timeout, status; + + for (timeout =3D 0; timeout < MBOX_XACTION_TIMEOUT; timeout++) { + msleep(1); + status =3D readl(base + MBOX_STATUS_OFFSET); + if (status & MASK_MBOX_STATUS_READY) + break; + } + + status =3D readl(base + MBOX_STATUS_OFFSET); + if (status & MASK_MBOX_STATUS_ERROR) + return UCODE_ERROR; + if (!(status & MASK_MBOX_STATUS_READY)) + return UCODE_TIMEOUT; + + return UCODE_OK; +} + +static enum ucode_state read_xaction_response(void __iomem *base, unsigned= int *offset) +{ + pr_debug_once("Need to implement staging response handler.\n"); + return UCODE_ERROR; +} + +static inline unsigned int get_chunksize(unsigned int totalsize, unsigned = int offset) +{ + WARN_ON_ONCE(totalsize < offset); + return min(MBOX_XACTION_LEN, totalsize - offset); +} + +bool staging_work(u64 mmio_pa, void *ucode_ptr, unsigned int totalsize) +{ + unsigned int xaction_bytes =3D 0, offset =3D 0, chunksize; + void __iomem *mmio_base; + enum ucode_state state; + + mmio_base =3D ioremap(mmio_pa, MBOX_REG_NUM * MBOX_REG_SIZE); + if (WARN_ON_ONCE(!mmio_base)) + return false; + + abort_xaction(mmio_base); + + while (offset !=3D STAGING_OFFSET_END) { + chunksize =3D get_chunksize(totalsize, offset); + if (xaction_bytes + chunksize > MBOX_XACTION_MAX(totalsize)) { + state =3D UCODE_TIMEOUT; + break; + } + + request_xaction(mmio_base, ucode_ptr + offset, chunksize); + state =3D wait_for_xaction(mmio_base); + if (state !=3D UCODE_OK) + break; + + xaction_bytes +=3D chunksize; + state =3D read_xaction_response(mmio_base, &offset); + if (state !=3D UCODE_OK) + break; + } + + iounmap(mmio_base); + + if (state =3D=3D UCODE_OK) + return true; + + pr_err("Staging failed with %s.\n", state =3D=3D UCODE_TIMEOUT ? "timeout= " : "error"); + return false; +} diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu= /microcode/internal.h index 06c3c8db4ceb..6b0d9a4374db 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -120,11 +120,7 @@ void load_ucode_intel_bsp(struct early_load_data *ed); void load_ucode_intel_ap(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); -static inline bool staging_work(u64 mmio_pa, void *ucode_ptr, unsigned int= totalsize) -{ - pr_debug_once("Need to implement the Staging code.\n"); - return false; -} +bool staging_work(u64 mmio_pa, void *ucode_ptr, unsigned int totalsize); #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(struct early_load_data *ed) { } static inline void load_ucode_intel_ap(void) { } --=20 2.43.0 From nobody Thu Nov 28 12:42:04 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACE3B1CCEE4 for ; Tue, 1 Oct 2024 16:11:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799066; cv=none; b=Z8Uehnbnx4Sr3bIlCHTvNk9I+uQP78BmVs6Q4M848D0qi62mP4W4Tldv07BBXn2IVV0vuo2Q4Kie49CQSBKpmG3ZCJb06b7gUF6r1HdeWZpsMsVLDkbHS72hZafS+Dh6WB+W26DTv+OMPkLdLPuRjowNqxvZFUUKyx/5YAS/9/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727799066; c=relaxed/simple; bh=og3ptKplKRERSZZ6uPlQwnlGAsXnoXNYZX9O9+GAwnE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gvzutkhyak+SPSAvCP7Xmhw1M1Mc5B/5sVl5jwRUO3jkSKJXJGlfCC1Xr8DNxUteBn+vAA/4dTG3AYWC5+7dHRFIS2wWm24H0YU8onOw7z9ryQaSxLnldYYIJ+F7czWO78vO+6LS91ZZHC0qg1hv0xuzWFu2aPTv87yVBxmLgOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GloO7cRZ; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GloO7cRZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727799064; x=1759335064; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=og3ptKplKRERSZZ6uPlQwnlGAsXnoXNYZX9O9+GAwnE=; b=GloO7cRZqTHCK5G3pH8eVv1ZBrM5KGYvHku0qIe3n3QWtUwDm2UZtKDX Lg8AAALTPCD5nt+bzTyl1WHO3vn81umN/7tOGmzlCbA8UlKuJAOwI9BuT S2eBndAvCdyQp8ZhNUqoTBkadHZHC7LHb1FK+K8Agh3+LiuGHwl1IYwTm rQgnhYDqtiCLqghhcfaPstdIZOHC7EPcFSPzGr9Y9H7gvMaMpEUsHR4vD O17/OPLlaDQ676pqkPphCLDwA+/+QlsqjZgdNQFsjYypzYjso1quUpAFF s9FYvflOEhRXWD8ZIjqq5znVoekdex8lII+KHAx5F9PXJq6c4X3kAUIav w==; X-CSE-ConnectionGUID: 1XwUQQOSRtu1Hmq90P+sew== X-CSE-MsgGUID: 7L15KRYfTumW785ITbIIZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="37539404" X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="37539404" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 09:11:04 -0700 X-CSE-ConnectionGUID: XkQWciR5RY6iqv11TVqRaQ== X-CSE-MsgGUID: b74saRphQZSphBzHhulFgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="78586008" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:11:04 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC 6/7] x86/microcode/intel_staging: Support mailbox data transfer Date: Tue, 1 Oct 2024 09:10:41 -0700 Message-Id: <20241001161042.465584-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The staging architecture features a narrowed interface for data transfer. Instead of allocating MMIO space based on data chunk size, it utilizes two data registers: one for reading and one for writing, enforcing the serialization of read and write operations. Additionally, it defines a mailbox data format. To facilitate data transfer, implement helper functions in line with this specified format for reading and writing staging data. This mailbox format is a customized version and is not compatible with the existing mailbox code, so reuse is not feasible. Signed-off-by: Chang S. Bae --- arch/x86/kernel/cpu/microcode/intel_staging.c | 55 ++++++++++++++++++- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel_staging.c b/arch/x86/kerne= l/cpu/microcode/intel_staging.c index 9989a78f9ef2..d56bad30164c 100644 --- a/arch/x86/kernel/cpu/microcode/intel_staging.c +++ b/arch/x86/kernel/cpu/microcode/intel_staging.c @@ -3,6 +3,7 @@ #define pr_fmt(fmt) "microcode: " fmt #include #include +#include =20 #include "internal.h" =20 @@ -11,17 +12,44 @@ =20 #define MBOX_CONTROL_OFFSET 0x0 #define MBOX_STATUS_OFFSET 0x4 +#define MBOX_WRDATA_OFFSET 0x8 +#define MBOX_RDDATA_OFFSET 0xc =20 #define MASK_MBOX_CTRL_ABORT BIT(0) +#define MASK_MBOX_CTRL_GO BIT(31) =20 #define MASK_MBOX_STATUS_ERROR BIT(2) #define MASK_MBOX_STATUS_READY BIT(31) =20 +#define MASK_MBOX_RESP_SUCCESS BIT(0) +#define MASK_MBOX_RESP_PROGRESS BIT(1) +#define MASK_MBOX_RESP_ERROR BIT(2) + +#define MBOX_CMD_LOAD 0x3 +#define MBOX_OBJ_STAGING 0xb +#define MBOX_HDR (PCI_VENDOR_ID_INTEL | (MBOX_OBJ_STAGING << 16)) +#define MBOX_HDR_SIZE 16 + #define MBOX_XACTION_LEN PAGE_SIZE #define MBOX_XACTION_MAX(imgsz) ((imgsz) * 2) #define MBOX_XACTION_TIMEOUT (10 * MSEC_PER_SEC) =20 #define STAGING_OFFSET_END 0xffffffff +#define DWORD_SIZE(s) ((s) / sizeof(u32)) + +static inline u32 read_mbox_dword(void __iomem *base) +{ + u32 dword =3D readl(base + MBOX_RDDATA_OFFSET); + + /* Inform the read completion to the staging firmware */ + writel(0, base + MBOX_RDDATA_OFFSET); + return dword; +} + +static inline void write_mbox_dword(void __iomem *base, u32 dword) +{ + writel(dword, base + MBOX_WRDATA_OFFSET); +} =20 static inline void abort_xaction(void __iomem *base) { @@ -30,7 +58,18 @@ static inline void abort_xaction(void __iomem *base) =20 static void request_xaction(void __iomem *base, u32 *chunk, unsigned int c= hunksize) { - pr_debug_once("Need to implement staging mailbox loading code.\n"); + unsigned int i, dwsize =3D DWORD_SIZE(chunksize); + + write_mbox_dword(base, MBOX_HDR); + write_mbox_dword(base, dwsize + DWORD_SIZE(MBOX_HDR_SIZE)); + + write_mbox_dword(base, MBOX_CMD_LOAD); + write_mbox_dword(base, 0); + + for (i =3D 0; i < dwsize; i++) + write_mbox_dword(base, chunk[i]); + + writel(MASK_MBOX_CTRL_GO, base + MBOX_CONTROL_OFFSET); } =20 static enum ucode_state wait_for_xaction(void __iomem *base) @@ -55,8 +94,18 @@ static enum ucode_state wait_for_xaction(void __iomem *b= ase) =20 static enum ucode_state read_xaction_response(void __iomem *base, unsigned= int *offset) { - pr_debug_once("Need to implement staging response handler.\n"); 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d="scan'208";a="78586022" Received: from cbae1-mobl.amr.corp.intel.com (HELO cbae1-mobl.intel.com) ([10.124.136.21]) by orviesa003.jf.intel.com with ESMTP; 01 Oct 2024 09:11:06 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, chang.seok.bae@intel.com Subject: [PATCH RFC 7/7] x86/microcode/intel: Enable staging when available Date: Tue, 1 Oct 2024 09:10:42 -0700 Message-Id: <20241001161042.465584-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001161042.465584-1-chang.seok.bae@intel.com> References: <20241001161042.465584-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the staging code being ready, check the relevant MSRs and set the feature chicken bit to allow staging to be invoked from the core microcode update process. Signed-off-by: Chang S. Bae --- arch/x86/kernel/cpu/microcode/intel.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 03c4b0e7e97c..8f2476fbe8f2 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -688,6 +688,18 @@ static __init void calc_llc_size_per_core(struct cpuin= fo_x86 *c) llc_size_per_core =3D (unsigned int)llc_size; } =20 +static __init bool staging_available(void) +{ + u64 val; + + val =3D x86_read_arch_cap_msr(); + if (!(val & ARCH_CAP_MCU_ENUM)) + return false; + + rdmsrl(MSR_IA32_MCU_ENUMERATION, val); + return !!(val & MCU_STAGING); +} + struct microcode_ops * __init init_intel_microcode(void) { struct cpuinfo_x86 *c =3D &boot_cpu_data; @@ -698,6 +710,11 @@ struct microcode_ops * __init init_intel_microcode(voi= d) return NULL; } =20 + if (staging_available()) { + pr_info("Staging is available.\n"); + microcode_intel_ops.use_staging =3D true; + } + calc_llc_size_per_core(c); =20 return µcode_intel_ops; --=20 2.43.0