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charset="utf-8" From: Lad Prabhakar Use enum values (`RZG2L_CRU_IP_SINK` and `RZG2L_CRU_IP_SOURCE`) instead of hardcoded array indices. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index ac8ebae4ed07..9f0ea1de50da 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -217,8 +217,8 @@ int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *= cru) ip->subdev.entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; ip->subdev.entity.ops =3D &rzg2l_cru_ip_entity_ops; =20 - ip->pads[0].flags =3D MEDIA_PAD_FL_SINK; - ip->pads[1].flags =3D MEDIA_PAD_FL_SOURCE; + ip->pads[RZG2L_CRU_IP_SINK].flags =3D MEDIA_PAD_FL_SINK; + ip->pads[RZG2L_CRU_IP_SOURCE].flags =3D MEDIA_PAD_FL_SOURCE; =20 ret =3D media_entity_pads_init(&ip->subdev.entity, 2, ip->pads); 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charset="utf-8" From: Lad Prabhakar Mark the sink and source pad with the MEDIA_PAD_FL_MUST_CONNECT flag to ensure pipeline validation fails if it is not connected. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line and commit message - Added MUST_CONNECT flag for source pad - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c | 2 +- drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-core.c index 19e0ba9596c9..69cd45b26951 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c @@ -209,7 +209,7 @@ static int rzg2l_cru_media_init(struct rzg2l_cru_dev *c= ru) const struct of_device_id *match; int ret; =20 - cru->pad.flags =3D MEDIA_PAD_FL_SINK; + cru->pad.flags =3D MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; ret =3D media_entity_pads_init(&cru->vdev.entity, 1, &cru->pad); if (ret) return ret; diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 9f0ea1de50da..700d8b704689 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -217,8 +217,10 @@ int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev = *cru) ip->subdev.entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 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Tue, 01 Oct 2024 07:09:39 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Laurent Pinchart , Sakari Ailus , Mauro Carvalho Chehab , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 03/17] media: rzg2l-cru: csi2: Mark sink and source pad with MUST_CONNECT flag Date: Tue, 1 Oct 2024 15:09:05 +0100 Message-ID: <20241001140919.206139-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241001140919.206139-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241001140919.206139-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Mark the sink and source pad with the MEDIA_PAD_FL_MUST_CONNECT flag to ensure pipeline validation fails if it is not connected. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line and commit message - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index c7fdee347ac8..2f4c87ede8bf 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -795,13 +795,15 @@ static int rzg2l_csi2_probe(struct platform_device *p= dev) csi2->subdev.entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; csi2->subdev.entity.ops =3D &rzg2l_csi2_entity_ops; =20 - csi2->pads[RZG2L_CSI2_SINK].flags =3D MEDIA_PAD_FL_SINK; + csi2->pads[RZG2L_CSI2_SINK].flags =3D MEDIA_PAD_FL_SINK | + MEDIA_PAD_FL_MUST_CONNECT; /* * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual * channels should be implemented by streams API which is under * development lets hardcode to VC0 for now. */ - csi2->pads[RZG2L_CSI2_SOURCE].flags =3D MEDIA_PAD_FL_SOURCE; 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charset="utf-8" From: Lad Prabhakar The media_entity_pads_init() function was previously hardcoded to use a magic number for the number of pads. Replace the magic number with the ARRAY_SIZE() macro to determine the number of pads dynamically. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line and commit message - Used ARRAY_SIZE() instead of NR_OF_RZG2L_CSI2_PAD - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index 2f4c87ede8bf..abacf53b944c 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -804,7 +804,8 @@ static int rzg2l_csi2_probe(struct platform_device *pde= v) */ csi2->pads[RZG2L_CSI2_SOURCE].flags =3D MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT; - ret =3D media_entity_pads_init(&csi2->subdev.entity, 2, csi2->pads); + ret =3D media_entity_pads_init(&csi2->subdev.entity, ARRAY_SIZE(csi2->pad= s), + csi2->pads); if (ret) goto error_pm; =20 --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17BF31C7B9B; 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charset="utf-8" From: Lad Prabhakar The RZ/G2L CRU requires information about which VCx to process data from, among the four available VCs. To obtain this information, the .get_frame_desc() routine is implemented. This routine, in turn, calls .get_frame_desc() on the remote sensor connected to the CSI2 bridge. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line v1->v2 - Collected RB tag --- .../platform/renesas/rzg2l-cru/rzg2l-csi2.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index abacf53b944c..3fd0be6a3b65 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -582,6 +582,25 @@ static int rzg2l_csi2_enum_frame_size(struct v4l2_subd= ev *sd, return 0; } =20 +static int rzg2l_csi2_get_frame_desc(struct v4l2_subdev *sd, unsigned int = pad, + struct v4l2_mbus_frame_desc *fd) +{ + struct rzg2l_csi2 *csi2 =3D sd_to_csi2(sd); + struct media_pad *remote_pad; + + if (!csi2->remote_source) + return -ENODEV; + + remote_pad =3D media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]); + if (IS_ERR(remote_pad)) { + dev_err(csi2->dev, "can't get source pad of %s (%ld)\n", + csi2->remote_source->name, PTR_ERR(remote_pad)); + return PTR_ERR(remote_pad); + } + return v4l2_subdev_call(csi2->remote_source, pad, get_frame_desc, + remote_pad->index, fd); +} + static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops =3D { .s_stream =3D rzg2l_csi2_s_stream, .pre_streamon =3D rzg2l_csi2_pre_streamon, @@ -593,6 +612,7 @@ static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_= ops =3D { .enum_frame_size =3D rzg2l_csi2_enum_frame_size, .set_fmt =3D rzg2l_csi2_set_format, .get_fmt =3D v4l2_subdev_get_fmt, + .get_frame_desc =3D rzg2l_csi2_get_frame_desc, }; =20 static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops =3D { --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C7A11C8FC9; Tue, 1 Oct 2024 14:09:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; 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charset="utf-8" From: Lad Prabhakar The RZ/G2L CRU needs to configure the ICnMC.VCSEL bits to specify which virtual channel should be processed from the four available VCs. To retrieve this information from the connected subdevice, the .get_frame_desc() function is called. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line v1->v2 - Collected RB tag --- .../platform/renesas/rzg2l-cru/rzg2l-cru.h | 5 +++ .../platform/renesas/rzg2l-cru/rzg2l-ip.c | 5 --- .../platform/renesas/rzg2l-cru/rzg2l-video.c | 34 +++++++++++++++++++ 3 files changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h b/drivers= /media/platform/renesas/rzg2l-cru/rzg2l-cru.h index 174760239548..8fbd45c43763 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h @@ -31,6 +31,11 @@ #define RZG2L_CRU_MIN_INPUT_HEIGHT 240 #define RZG2L_CRU_MAX_INPUT_HEIGHT 4095 =20 +enum rzg2l_csi2_pads { + RZG2L_CRU_IP_SINK =3D 0, + RZG2L_CRU_IP_SOURCE, +}; + /** * enum rzg2l_cru_dma_state - DMA states * @RZG2L_CRU_DMA_STOPPED: No operation in progress diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 700d8b704689..aee7d4ba70b0 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -18,11 +18,6 @@ static const struct rzg2l_cru_ip_format rzg2l_cru_ip_for= mats[] =3D { { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, .datatype =3D 0x1e, .bpp =3D 16 }, }; =20 -enum rzg2l_csi2_pads { - RZG2L_CRU_IP_SINK =3D 0, - RZG2L_CRU_IP_SOURCE, -}; - static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned= int code) { unsigned int i; diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index bbf4674f888d..7cd33eb1939c 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -433,12 +433,46 @@ void rzg2l_cru_stop_image_processing(struct rzg2l_cru= _dev *cru) spin_unlock_irqrestore(&cru->qlock, flags); } =20 +static int rzg2l_cru_get_virtual_channel(struct rzg2l_cru_dev *cru) +{ + struct v4l2_mbus_frame_desc fd =3D { }; + struct media_pad *remote_pad; + int ret; + + remote_pad =3D media_pad_remote_pad_unique(&cru->ip.pads[RZG2L_CRU_IP_SIN= K]); + ret =3D v4l2_subdev_call(cru->ip.remote, pad, get_frame_desc, remote_pad-= >index, &fd); + if (ret < 0 && ret !=3D -ENOIOCTLCMD) { + dev_err(cru->dev, "get_frame_desc failed on IP remote subdev\n"); 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charset="utf-8" From: Lad Prabhakar Remove the CSI virtual channel number from `struct rzg2l_cru_csi`. Instead, pass the CSI virtual channel number as an argument to `rzg2l_cru_csi2_setup()`. Suggested-by: Laurent Pinchart Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Collected RB tag v1->v2 - New patch --- .../media/platform/renesas/rzg2l-cru/rzg2l-core.c | 1 - .../media/platform/renesas/rzg2l-cru/rzg2l-cru.h | 1 - .../media/platform/renesas/rzg2l-cru/rzg2l-video.c | 14 ++++++++------ 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-core.c index 69cd45b26951..b21a66e2ce5c 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c @@ -72,7 +72,6 @@ static int rzg2l_cru_group_notify_complete(struct v4l2_as= ync_notifier *notifier) source->name, sink->name); return ret; } - cru->csi.channel =3D 0; cru->ip.remote =3D cru->csi.subdev; =20 /* Create media device link between CRU IP <-> CRU OUTPUT */ diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h b/drivers= /media/platform/renesas/rzg2l-cru/rzg2l-cru.h index 8fbd45c43763..4fe24bdde5b2 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h @@ -53,7 +53,6 @@ enum rzg2l_cru_dma_state { struct rzg2l_cru_csi { struct v4l2_async_connection *asd; struct v4l2_subdev *subdev; - u32 channel; }; =20 struct rzg2l_cru_ip { diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index 7cd33eb1939c..9ab7ef33c9da 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -301,7 +301,7 @@ static void rzg2l_cru_initialize_axi(struct rzg2l_cru_d= ev *cru) } =20 static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, bool *input_is= _yuv, - struct v4l2_mbus_framefmt *ip_sd_fmt) + struct v4l2_mbus_framefmt *ip_sd_fmt, u8 csi_vc) { u32 icnmc; =20 @@ -319,19 +319,20 @@ static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev= *cru, bool *input_is_yuv, icnmc |=3D (rzg2l_cru_read(cru, ICnMC) & ~ICnMC_INF_MASK); =20 /* Set virtual channel CSI2 */ - icnmc |=3D ICnMC_VCSEL(cru->csi.channel); + icnmc |=3D ICnMC_VCSEL(csi_vc); =20 rzg2l_cru_write(cru, ICnMC, icnmc); } =20 static int rzg2l_cru_initialize_image_conv(struct rzg2l_cru_dev *cru, - struct v4l2_mbus_framefmt *ip_sd_fmt) + struct v4l2_mbus_framefmt *ip_sd_fmt, + u8 csi_vc) { bool output_is_yuv =3D false; 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charset="utf-8" From: Lad Prabhakar The INF field in the ICnMC register accepts data type codes as specified in the MIPI CSI-2 v2.1 specification. This patch introduces the `ICnMC_INF()` macro to use the MIPI CSI-2 data types, which are available in the `media/mipi-csi2.h` header. Suggested-by: Laurent Pinchart Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index 9ab7ef33c9da..de88c0fab961 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -15,6 +15,7 @@ #include #include =20 +#include #include #include =20 @@ -77,8 +78,7 @@ /* CRU Image Processing Main Control Register */ #define ICnMC 0x208 #define ICnMC_CSCTHR BIT(5) -#define ICnMC_INF_YUV8_422 (0x1e << 16) -#define ICnMC_INF_USER (0x30 << 16) +#define ICnMC_INF(x) ((x) << 16) #define ICnMC_VCSEL(x) ((x) << 22) #define ICnMC_INF_MASK GENMASK(21, 16) =20 @@ -307,12 +307,12 @@ static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev= *cru, bool *input_is_yuv, =20 switch (ip_sd_fmt->code) { case MEDIA_BUS_FMT_UYVY8_1X16: - icnmc =3D ICnMC_INF_YUV8_422; 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charset="utf-8" From: Lad Prabhakar Simplified the `rzg2l_cru_ip_format` struct by removing the unused `datatype` and `bpp` fields from the structure in `rzg2l-ip.c`. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index aee7d4ba70b0..7b006a0bfaae 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -10,12 +10,10 @@ =20 struct rzg2l_cru_ip_format { u32 code; - unsigned int datatype; - unsigned int bpp; }; =20 static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] =3D { - { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, .datatype =3D 0x1e, .bpp =3D 16 }, + { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, }, }; =20 static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned= int code) --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB4F31C9DDA; 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charset="utf-8" From: Lad Prabhakar Refactor the handling of supported formats in the RZ/G2L CRU driver by moving the `rzg2l_cru_ip_format` struct to the common header to allow reuse across multiple files and adding pixelformat and bpp members to it. This change centralizes format handling, making it easier to manage and extend. - Moved the `rzg2l_cru_ip_format` struct to `rzg2l-cru.h` for better accessibility. - Added format, datatype and bpp members to `rzg2l_cru_ip_format` struct - Dropped rzg2l_cru_formats - Introduced helper functions `rzg2l_cru_ip_code_to_fmt()`, `rzg2l_cru_ip_format_to_fmt()`, and `rzg2l_cru_ip_index_to_fmt()` to streamline format lookups. - Refactored the `rzg2l_cru_csi2_setup` and format alignment functions to utilize the new helpers. Suggested-by: Laurent Pinchart Signed-off-by: Lad Prabhakar --- v2->v3 - Updated subject line and commit message - Implemented rzg2l_cru_ip_format_to_fmt() and rzg2l_cru_ip_index_to_fmt() - Dropped checking fmt in rzg2l_cru_initialize_image_conv() v1->v2 - New patch --- .../platform/renesas/rzg2l-cru/rzg2l-cru.h | 20 +++++- .../platform/renesas/rzg2l-cru/rzg2l-ip.c | 35 ++++++++-- .../platform/renesas/rzg2l-cru/rzg2l-video.c | 67 ++++++------------- 3 files changed, 68 insertions(+), 54 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h b/drivers= /media/platform/renesas/rzg2l-cru/rzg2l-cru.h index 4fe24bdde5b2..39296a59b3da 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h @@ -62,6 +62,20 @@ struct rzg2l_cru_ip { struct v4l2_subdev *remote; }; =20 +/** + * struct rzg2l_cru_ip_format - CRU IP format + * @code: Media bus code + * @format: 4CC format identifier (V4L2_PIX_FMT_*) + * @datatype: MIPI CSI2 data type + * @bpp: bytes per pixel + */ +struct rzg2l_cru_ip_format { + u32 code; + u32 format; + u32 datatype; + u8 bpp; +}; + /** * struct rzg2l_cru_dev - Renesas CRU device structure * @dev: (OF) device @@ -144,10 +158,12 @@ int rzg2l_cru_video_register(struct rzg2l_cru_dev *cr= u); void rzg2l_cru_video_unregister(struct rzg2l_cru_dev *cru); irqreturn_t rzg2l_cru_irq(int irq, void *data); =20 -const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format); - int rzg2l_cru_ip_subdev_register(struct rzg2l_cru_dev *cru); void rzg2l_cru_ip_subdev_unregister(struct rzg2l_cru_dev *cru); struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *= cru); =20 +const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int co= de); +const struct rzg2l_cru_ip_format *rzg2l_cru_ip_format_to_fmt(u32 format); +const struct rzg2l_cru_ip_format *rzg2l_cru_ip_index_to_fmt(u32 index); + #endif diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 7b006a0bfaae..12aac9d6cb4b 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -6,17 +6,21 @@ */ =20 #include -#include "rzg2l-cru.h" =20 -struct rzg2l_cru_ip_format { - u32 code; -}; +#include + +#include "rzg2l-cru.h" =20 static const struct rzg2l_cru_ip_format rzg2l_cru_ip_formats[] =3D { - { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, }, + { + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .format =3D V4L2_PIX_FMT_UYVY, + .datatype =3D MIPI_CSI2_DT_YUV422_8B, + .bpp =3D 2, + }, }; =20 -static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned= int code) +const struct rzg2l_cru_ip_format *rzg2l_cru_ip_code_to_fmt(unsigned int co= de) { unsigned int i; =20 @@ -27,6 +31,25 @@ static const struct rzg2l_cru_ip_format *rzg2l_cru_ip_co= de_to_fmt(unsigned int c return NULL; } =20 +const struct rzg2l_cru_ip_format *rzg2l_cru_ip_format_to_fmt(u32 format) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(rzg2l_cru_ip_formats); i++) + if (rzg2l_cru_ip_formats[i].format =3D=3D format) + return &rzg2l_cru_ip_formats[i]; + + return NULL; +} + +const struct rzg2l_cru_ip_format *rzg2l_cru_ip_index_to_fmt(u32 index) +{ + if (index >=3D ARRAY_SIZE(rzg2l_cru_ip_formats)) + return NULL; + + return &rzg2l_cru_ip_formats[index]; +} + struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *= cru) { struct v4l2_subdev_state *state; diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index de88c0fab961..ceb9012c9d70 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -300,21 +300,10 @@ static void rzg2l_cru_initialize_axi(struct rzg2l_cru= _dev *cru) rzg2l_cru_write(cru, AMnAXIATTR, amnaxiattr); } =20 -static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, bool *input_is= _yuv, - struct v4l2_mbus_framefmt *ip_sd_fmt, u8 csi_vc) +static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, u8 csi_vc, + u32 csi2_datatype) { - u32 icnmc; - - switch (ip_sd_fmt->code) { - case MEDIA_BUS_FMT_UYVY8_1X16: - icnmc =3D ICnMC_INF(MIPI_CSI2_DT_YUV422_8B); - *input_is_yuv =3D true; - break; - default: - *input_is_yuv =3D false; - icnmc =3D ICnMC_INF(MIPI_CSI2_DT_USER_DEFINED(0)); - break; - } + u32 icnmc =3D ICnMC_INF(csi2_datatype); =20 icnmc |=3D (rzg2l_cru_read(cru, ICnMC) & ~ICnMC_INF_MASK); =20 @@ -328,17 +317,20 @@ static int rzg2l_cru_initialize_image_conv(struct rzg= 2l_cru_dev *cru, struct v4l2_mbus_framefmt *ip_sd_fmt, u8 csi_vc) { - bool output_is_yuv =3D false; - bool input_is_yuv =3D false; + const struct v4l2_format_info *src_finfo, *dst_finfo; + const struct rzg2l_cru_ip_format *cru_ip_fmt; u32 icndmr; =20 - rzg2l_cru_csi2_setup(cru, &input_is_yuv, ip_sd_fmt, csi_vc); + cru_ip_fmt =3D rzg2l_cru_ip_code_to_fmt(ip_sd_fmt->code); + rzg2l_cru_csi2_setup(cru, csi_vc, cru_ip_fmt->datatype); + + src_finfo =3D v4l2_format_info(cru_ip_fmt->format); + dst_finfo =3D v4l2_format_info(cru->format.pixelformat); =20 /* Output format */ switch (cru->format.pixelformat) { case V4L2_PIX_FMT_UYVY: icndmr =3D ICnDMR_YCMODE_UYVY; - output_is_yuv =3D true; break; default: dev_err(cru->dev, "Invalid pixelformat (0x%x)\n", @@ -347,7 +339,7 @@ static int rzg2l_cru_initialize_image_conv(struct rzg2l= _cru_dev *cru, } =20 /* If input and output use same colorspace, do bypass mode */ - if (output_is_yuv =3D=3D input_is_yuv) + if (v4l2_is_format_yuv(src_finfo) && v4l2_is_format_yuv(dst_finfo)) rzg2l_cru_write(cru, ICnMC, rzg2l_cru_read(cru, ICnMC) | ICnMC_CSCTHR); else @@ -810,35 +802,15 @@ int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru) /* -----------------------------------------------------------------------= ------ * V4L2 stuff */ - -static const struct v4l2_format_info rzg2l_cru_formats[] =3D { - { - .format =3D V4L2_PIX_FMT_UYVY, - .bpp[0] =3D 2, - }, -}; - -const struct v4l2_format_info *rzg2l_cru_format_from_pixel(u32 format) -{ - unsigned int i; - - for (i =3D 0; i < ARRAY_SIZE(rzg2l_cru_formats); i++) - if (rzg2l_cru_formats[i].format =3D=3D format) - return rzg2l_cru_formats + i; - - return NULL; -} - static u32 rzg2l_cru_format_bytesperline(struct v4l2_pix_format *pix) { - const struct v4l2_format_info *fmt; - - fmt =3D rzg2l_cru_format_from_pixel(pix->pixelformat); + const struct rzg2l_cru_ip_format *fmt; =20 + fmt =3D rzg2l_cru_ip_format_to_fmt(pix->pixelformat); if (WARN_ON(!fmt)) - return -EINVAL; + return 0; =20 - return pix->width * fmt->bpp[0]; + return pix->width * fmt->bpp; } =20 static u32 rzg2l_cru_format_sizeimage(struct v4l2_pix_format *pix) @@ -849,7 +821,7 @@ static u32 rzg2l_cru_format_sizeimage(struct v4l2_pix_f= ormat *pix) static void rzg2l_cru_format_align(struct rzg2l_cru_dev *cru, struct v4l2_pix_format *pix) { - if (!rzg2l_cru_format_from_pixel(pix->pixelformat)) + if (!rzg2l_cru_ip_format_to_fmt(pix->pixelformat)) pix->pixelformat =3D RZG2L_CRU_DEFAULT_FORMAT; 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charset="utf-8" From: Lad Prabhakar Use the `rzg2l_cru_ip_formats` array in `rzg2l_cru_ip_enum_frame_size()` to validate the format code. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line and commit message - Dropped fse->index check - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 12aac9d6cb4b..6ce077ab42e2 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -165,7 +165,7 @@ static int rzg2l_cru_ip_enum_frame_size(struct v4l2_sub= dev *sd, if (fse->index !=3D 0) return -EINVAL; =20 - if (fse->code !=3D MEDIA_BUS_FMT_UYVY8_1X16) + if (!rzg2l_cru_ip_code_to_fmt(fse->code)) return -EINVAL; =20 fse->min_width =3D RZG2L_CRU_MIN_INPUT_WIDTH; --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19CC91CB30A; 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charset="utf-8" From: Lad Prabhakar Remove the unused `datatype` field from the `rzg2l_csi2_format` struct and update the `rzg2l_csi2_formats[]` array to reflect the updated structure. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index 3fd0be6a3b65..7b76d495cfe4 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -183,12 +183,11 @@ static const struct rzg2l_csi2_timings rzg2l_csi2_glo= bal_timings[] =3D { =20 struct rzg2l_csi2_format { u32 code; - unsigned int datatype; unsigned int bpp; }; =20 static const struct rzg2l_csi2_format rzg2l_csi2_formats[] =3D { - { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, .datatype =3D 0x1e, .bpp =3D 16 }, + { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, .bpp =3D 16 }, }; =20 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd) --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8D791CB300; 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charset="utf-8" From: Lad Prabhakar Implement the `.link_validate()` callback for the video node and move the format checking into this function. This change allows the removal of `rzg2l_cru_mc_validate_format()`. Suggested-by: Laurent Pinchart Signed-off-by: Lad Prabhakar --- v2->v3 - New patch --- .../platform/renesas/rzg2l-cru/rzg2l-video.c | 99 ++++++++++--------- 1 file changed, 55 insertions(+), 44 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index ceb9012c9d70..c6c82b9b130a 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -189,46 +189,6 @@ static void rzg2l_cru_buffer_queue(struct vb2_buffer *= vb) spin_unlock_irqrestore(&cru->qlock, flags); } =20 -static int rzg2l_cru_mc_validate_format(struct rzg2l_cru_dev *cru, - struct v4l2_subdev *sd, - struct media_pad *pad) -{ - struct v4l2_subdev_format fmt =3D { - .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, - }; - - fmt.pad =3D pad->index; - if (v4l2_subdev_call_state_active(sd, pad, get_fmt, &fmt)) - return -EPIPE; - - switch (fmt.format.code) { - case MEDIA_BUS_FMT_UYVY8_1X16: - break; - default: - return -EPIPE; - } - - switch (fmt.format.field) { - case V4L2_FIELD_TOP: - case V4L2_FIELD_BOTTOM: - case V4L2_FIELD_NONE: - case V4L2_FIELD_INTERLACED_TB: - case V4L2_FIELD_INTERLACED_BT: - case V4L2_FIELD_INTERLACED: - case V4L2_FIELD_SEQ_TB: - case V4L2_FIELD_SEQ_BT: - break; - default: - return -EPIPE; - } - - if (fmt.format.width !=3D cru->format.width || - fmt.format.height !=3D cru->format.height) - return -EPIPE; - - return 0; -} - static void rzg2l_cru_set_slot_addr(struct rzg2l_cru_dev *cru, int slot, dma_addr_t addr) { @@ -531,10 +491,6 @@ static int rzg2l_cru_set_stream(struct rzg2l_cru_dev *= cru, int on) return stream_off_ret; } =20 - ret =3D rzg2l_cru_mc_validate_format(cru, sd, pad); - if (ret) - return ret; - pipe =3D media_entity_pipeline(&sd->entity) ? : &cru->vdev.pipe; ret =3D video_device_pipeline_start(&cru->vdev, pipe); if (ret) @@ -995,6 +951,60 @@ static const struct v4l2_file_operations rzg2l_cru_fop= s =3D { .read =3D vb2_fop_read, }; =20 +/* -----------------------------------------------------------------------= ------ + * Media entity operations + */ + +static int rzg2l_cru_video_link_validate(struct media_link *link) +{ + struct v4l2_subdev_format fmt =3D { + .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, + }; + struct v4l2_subdev *subdev; + struct media_entity *entity; + struct rzg2l_cru_dev *cru; + struct media_pad *remote; + int ret; + + entity =3D link->sink->entity; + remote =3D link->source; + + subdev =3D media_entity_to_v4l2_subdev(remote->entity); + fmt.pad =3D remote->index; + ret =3D v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); + if (ret < 0) + return ret =3D=3D -ENOIOCTLCMD ? -EINVAL : ret; + + if (!rzg2l_cru_ip_code_to_fmt(fmt.format.code)) + return -EPIPE; + + switch (fmt.format.field) { + case V4L2_FIELD_TOP: + case V4L2_FIELD_BOTTOM: + case V4L2_FIELD_NONE: + case V4L2_FIELD_INTERLACED_TB: + case V4L2_FIELD_INTERLACED_BT: + case V4L2_FIELD_INTERLACED: + case V4L2_FIELD_SEQ_TB: + case V4L2_FIELD_SEQ_BT: + break; + default: + return -EPIPE; + } + + cru =3D container_of(media_entity_to_video_device(entity), + struct rzg2l_cru_dev, vdev); + if (fmt.format.width !=3D cru->format.width || + fmt.format.height !=3D cru->format.height) + return -EPIPE; + + return 0; +} + +static const struct media_entity_operations rzg2l_cru_video_media_ops =3D { + .link_validate =3D rzg2l_cru_video_link_validate, +}; + static void rzg2l_cru_v4l2_init(struct rzg2l_cru_dev *cru) { struct video_device *vdev =3D &cru->vdev; @@ -1006,6 +1016,7 @@ static void rzg2l_cru_v4l2_init(struct rzg2l_cru_dev = *cru) vdev->lock =3D &cru->lock; vdev->device_caps =3D V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; vdev->device_caps |=3D V4L2_CAP_IO_MC; + vdev->entity.ops =3D &rzg2l_cru_video_media_ops; vdev->fops =3D &rzg2l_cru_fops; vdev->ioctl_ops =3D &rzg2l_cru_ioctl_ops; =20 --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F1091CB316; Tue, 1 Oct 2024 14:09:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727791796; cv=none; b=oaquWCzY4p/fx5ValALO17gbQrNeehSn/C2SNj+5wzGAb4fxM2t2kBHvaShyQejdEP7lgnNmBaaEBJpZBf/eQGTMj/beM9kQ4W7TLzKz+ZZV+KeJRuFurM8JG6GG0Kel80M1I4NvW5nPcpLB5BRZdIX3DdMeVEg5WgRg8c2gs3s= ARC-Message-Signature: i=1; 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Tue, 01 Oct 2024 07:09:52 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Laurent Pinchart , Sakari Ailus , Mauro Carvalho Chehab , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 14/17] media: rzg2l-cru: csi2: Use rzg2l_csi2_formats array in enum_frame_size Date: Tue, 1 Oct 2024 15:09:16 +0100 Message-ID: <20241001140919.206139-15-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241001140919.206139-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241001140919.206139-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Make use of `rzg2l_csi2_formats` array in rzg2l_csi2_enum_frame_size() to validate if the `fse->code` is supported. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Dropped fse->index check - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index 7b76d495cfe4..e21142d3b67d 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -573,6 +573,9 @@ static int rzg2l_csi2_enum_frame_size(struct v4l2_subde= v *sd, if (fse->index !=3D 0) return -EINVAL; =20 + if (!rzg2l_csi2_code_to_fmt(fse->code)) + return -EINVAL; + fse->min_width =3D RZG2L_CSI2_MIN_WIDTH; fse->min_height =3D RZG2L_CSI2_MIN_HEIGHT; fse->max_width =3D RZG2L_CSI2_MAX_WIDTH; --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B8EA1CB510; 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charset="utf-8" From: Lad Prabhakar Refactor the ICnDMR register configuration in `rzg2l_cru_initialize_image_conv()` by adding a new member `icndmr` in the `rzg2l_cru_ip_format` structure. Suggested-by: Laurent Pinchart Signed-off-by: Lad Prabhakar --- v2->v3 - Updated subject line and commit message - Re-used rzg2l_cru_ip_format_to_fmt() to fetch icndmr details - Collected RB tag v1->v2 - New patch --- drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h | 4 ++++ drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 1 + drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c | 10 ++++------ 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h b/drivers= /media/platform/renesas/rzg2l-cru/rzg2l-cru.h index 39296a59b3da..51206373b7fe 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h @@ -31,6 +31,8 @@ #define RZG2L_CRU_MIN_INPUT_HEIGHT 240 #define RZG2L_CRU_MAX_INPUT_HEIGHT 4095 =20 +#define ICnDMR_YCMODE_UYVY (1 << 4) + enum rzg2l_csi2_pads { RZG2L_CRU_IP_SINK =3D 0, RZG2L_CRU_IP_SOURCE, @@ -68,12 +70,14 @@ struct rzg2l_cru_ip { * @format: 4CC format identifier (V4L2_PIX_FMT_*) * @datatype: MIPI CSI2 data type * @bpp: bytes per pixel + * @icndmr: ICnDMR register value */ struct rzg2l_cru_ip_format { u32 code; u32 format; u32 datatype; u8 bpp; + u32 icndmr; }; =20 /** diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index 6ce077ab42e2..f14ac949cc64 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -17,6 +17,7 @@ static const struct rzg2l_cru_ip_format rzg2l_cru_ip_form= ats[] =3D { .format =3D V4L2_PIX_FMT_UYVY, .datatype =3D MIPI_CSI2_DT_YUV422_8B, .bpp =3D 2, + .icndmr =3D ICnDMR_YCMODE_UYVY, }, }; =20 diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index c6c82b9b130a..c3d10b001b7c 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -88,7 +88,6 @@ =20 /* CRU Data Output Mode Register */ #define ICnDMR 0x26c -#define ICnDMR_YCMODE_UYVY (1 << 4) =20 #define RZG2L_TIMEOUT_MS 100 #define RZG2L_RETRIES 10 @@ -278,6 +277,7 @@ static int rzg2l_cru_initialize_image_conv(struct rzg2l= _cru_dev *cru, u8 csi_vc) { const struct v4l2_format_info *src_finfo, *dst_finfo; + const struct rzg2l_cru_ip_format *cru_video_fmt; const struct rzg2l_cru_ip_format *cru_ip_fmt; u32 icndmr; =20 @@ -288,15 +288,13 @@ static int rzg2l_cru_initialize_image_conv(struct rzg= 2l_cru_dev *cru, dst_finfo =3D v4l2_format_info(cru->format.pixelformat); =20 /* Output format */ - switch (cru->format.pixelformat) { - case V4L2_PIX_FMT_UYVY: - icndmr =3D ICnDMR_YCMODE_UYVY; - break; - default: + cru_video_fmt =3D rzg2l_cru_ip_format_to_fmt(cru->format.pixelformat); + if (!cru_video_fmt) { dev_err(cru->dev, "Invalid pixelformat (0x%x)\n", cru->format.pixelformat); return -EINVAL; } + icndmr =3D cru_video_fmt->icndmr; =20 /* If input and output use same colorspace, do bypass mode */ if (v4l2_is_format_yuv(src_finfo) && v4l2_is_format_yuv(dst_finfo)) --=20 2.43.0 From nobody Thu Nov 28 12:35:12 2024 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F84F1C6F66; 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charset="utf-8" From: Lad Prabhakar Add support to capture 8bit Bayer formats. Signed-off-by: Lad Prabhakar Reviewed-by: Laurent Pinchart --- v2->v3 - Updated subject line - Collected RB tag v1->v2 - Used the simplified version of format handling --- .../platform/renesas/rzg2l-cru/rzg2l-csi2.c | 4 +++ .../platform/renesas/rzg2l-cru/rzg2l-ip.c | 28 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/driver= s/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c index e21142d3b67d..84230926875a 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c @@ -188,6 +188,10 @@ struct rzg2l_csi2_format { =20 static const struct rzg2l_csi2_format rzg2l_csi2_formats[] =3D { { .code =3D MEDIA_BUS_FMT_UYVY8_1X16, .bpp =3D 16 }, + { .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, .bpp =3D 8, }, + { .code =3D MEDIA_BUS_FMT_SGBRG8_1X8, .bpp =3D 8, }, + { .code =3D MEDIA_BUS_FMT_SGRBG8_1X8, .bpp =3D 8, }, + { .code =3D MEDIA_BUS_FMT_SRGGB8_1X8, .bpp =3D 8, }, }; =20 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/= media/platform/renesas/rzg2l-cru/rzg2l-ip.c index f14ac949cc64..7e3f725eeece 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c @@ -19,6 +19,34 @@ static const struct rzg2l_cru_ip_format rzg2l_cru_ip_for= mats[] =3D { .bpp =3D 2, .icndmr =3D ICnDMR_YCMODE_UYVY, }, + { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .format =3D V4L2_PIX_FMT_SBGGR8, + .datatype =3D MIPI_CSI2_DT_RAW8, + .bpp =3D 1, + .icndmr =3D 0, + }, + { + .code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .format =3D V4L2_PIX_FMT_SGBRG8, + .datatype =3D MIPI_CSI2_DT_RAW8, + .bpp =3D 1, + .icndmr =3D 0, + }, + { + .code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .format =3D V4L2_PIX_FMT_SGRBG8, + .datatype =3D MIPI_CSI2_DT_RAW8, + .bpp =3D 1, + .icndmr =3D 0, + }, + { + .code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .format =3D V4L2_PIX_FMT_SRGGB8, + .datatype =3D MIPI_CSI2_DT_RAW8, + .bpp =3D 1, + .icndmr =3D 0, + }, }; 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charset="utf-8" From: Lad Prabhakar Move the RZ/G2L CRU register definitions from `rzg2l-video.c` to a dedicated header file, `rzg2l-cru-regs.h`. Separating these definitions into their own file improves the readability of the code. Suggested-by: Laurent Pinchart Signed-off-by: Lad Prabhakar --- v2->v3 - New patch --- .../renesas/rzg2l-cru/rzg2l-cru-regs.h | 79 +++++++++++++++++++ .../platform/renesas/rzg2l-cru/rzg2l-video.c | 69 +--------------- 2 files changed, 80 insertions(+), 68 deletions(-) create mode 100644 drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs= .h diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h b/dr= ivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h new file mode 100644 index 000000000000..458f7452e5d3 --- /dev/null +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru-regs.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __RZG2L_CRU_REGS_H__ +#define __RZG2L_CRU_REGS_H__ + +/* HW CRU Registers Definition */ + +/* CRU Control Register */ +#define CRUnCTRL 0x0 +#define CRUnCTRL_VINSEL(x) ((x) << 0) + +/* CRU Interrupt Enable Register */ +#define CRUnIE 0x4 +#define CRUnIE_EFE BIT(17) + +/* CRU Interrupt Status Register */ +#define CRUnINTS 0x8 +#define CRUnINTS_SFS BIT(16) + +/* CRU Reset Register */ +#define CRUnRST 0xc +#define CRUnRST_VRESETN BIT(0) + +/* Memory Bank Base Address (Lower) Register for CRU Image Data */ +#define AMnMBxADDRL(x) (0x100 + ((x) * 8)) + +/* Memory Bank Base Address (Higher) Register for CRU Image Data */ +#define AMnMBxADDRH(x) (0x104 + ((x) * 8)) + +/* Memory Bank Enable Register for CRU Image Data */ +#define AMnMBVALID 0x148 +#define AMnMBVALID_MBVALID(x) GENMASK(x, 0) + +/* Memory Bank Status Register for CRU Image Data */ +#define AMnMBS 0x14c +#define AMnMBS_MBSTS 0x7 + +/* AXI Master Transfer Setting Register for CRU Image Data */ +#define AMnAXIATTR 0x158 +#define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0) +#define AMnAXIATTR_AXILEN (0xf) + +/* AXI Master FIFO Pointer Register for CRU Image Data */ +#define AMnFIFOPNTR 0x168 +#define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0) +#define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16) + +/* AXI Master Transfer Stop Register for CRU Image Data */ +#define AMnAXISTP 0x174 +#define AMnAXISTP_AXI_STOP BIT(0) + +/* AXI Master Transfer Stop Status Register for CRU Image Data */ +#define AMnAXISTPACK 0x178 +#define AMnAXISTPACK_AXI_STOP_ACK BIT(0) + +/* CRU Image Processing Enable Register */ +#define ICnEN 0x200 +#define ICnEN_ICEN BIT(0) + +/* CRU Image Processing Main Control Register */ +#define ICnMC 0x208 +#define ICnMC_CSCTHR BIT(5) +#define ICnMC_INF(x) ((x) << 16) +#define ICnMC_VCSEL(x) ((x) << 22) +#define ICnMC_INF_MASK GENMASK(21, 16) + +/* CRU Module Status Register */ +#define ICnMS 0x254 +#define ICnMS_IA BIT(2) + +/* CRU Data Output Mode Register */ +#define ICnDMR 0x26c + +#endif /* __RZG2L_CRU_REGS_H__ */ diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drive= rs/media/platform/renesas/rzg2l-cru/rzg2l-video.c index c3d10b001b7c..d7c82c7b9044 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -20,74 +20,7 @@ #include =20 #include "rzg2l-cru.h" - -/* HW CRU Registers Definition */ - -/* CRU Control Register */ -#define CRUnCTRL 0x0 -#define CRUnCTRL_VINSEL(x) ((x) << 0) - -/* CRU Interrupt Enable Register */ -#define CRUnIE 0x4 -#define CRUnIE_EFE BIT(17) - -/* CRU Interrupt Status Register */ -#define CRUnINTS 0x8 -#define CRUnINTS_SFS BIT(16) - -/* CRU Reset Register */ -#define CRUnRST 0xc -#define CRUnRST_VRESETN BIT(0) - -/* Memory Bank Base Address (Lower) Register for CRU Image Data */ -#define AMnMBxADDRL(x) (0x100 + ((x) * 8)) - -/* Memory Bank Base Address (Higher) Register for CRU Image Data */ -#define AMnMBxADDRH(x) (0x104 + ((x) * 8)) - -/* Memory Bank Enable Register for CRU Image Data */ -#define AMnMBVALID 0x148 -#define AMnMBVALID_MBVALID(x) GENMASK(x, 0) - -/* Memory Bank Status Register for CRU Image Data */ -#define AMnMBS 0x14c -#define AMnMBS_MBSTS 0x7 - -/* AXI Master Transfer Setting Register for CRU Image Data */ -#define AMnAXIATTR 0x158 -#define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0) -#define AMnAXIATTR_AXILEN (0xf) - -/* AXI Master FIFO Pointer Register for CRU Image Data */ -#define AMnFIFOPNTR 0x168 -#define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0) -#define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16) - -/* AXI Master Transfer Stop Register for CRU Image Data */ -#define AMnAXISTP 0x174 -#define AMnAXISTP_AXI_STOP BIT(0) - -/* AXI Master Transfer Stop Status Register for CRU Image Data */ -#define AMnAXISTPACK 0x178 -#define AMnAXISTPACK_AXI_STOP_ACK BIT(0) - -/* CRU Image Processing Enable Register */ -#define ICnEN 0x200 -#define ICnEN_ICEN BIT(0) - -/* CRU Image Processing Main Control Register */ -#define ICnMC 0x208 -#define ICnMC_CSCTHR BIT(5) -#define ICnMC_INF(x) ((x) << 16) -#define ICnMC_VCSEL(x) ((x) << 22) -#define ICnMC_INF_MASK GENMASK(21, 16) - -/* CRU Module Status Register */ -#define ICnMS 0x254 -#define ICnMS_IA BIT(2) - -/* CRU Data Output Mode Register */ -#define ICnDMR 0x26c +#include "rzg2l-cru-regs.h" =20 #define RZG2L_TIMEOUT_MS 100 #define RZG2L_RETRIES 10 --=20 2.43.0