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charset="utf-8" Add support for LAN8670/1/2 Rev.C1 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 2 +- drivers/net/phy/microchip_t1s.c | 66 ++++++++++++++++++++++++++++++++- 2 files changed, 66 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f18defab70cf..04f605606a8a 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -292,7 +292,7 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0/B1 + Currently supports the LAN8670/1/2 Rev.B1/C1 and LAN8650/1 Rev.B0/B1 Internal PHYs. =20 config MICROCHIP_PHY diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index a874ac87ce10..003aecaf35b2 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -3,7 +3,7 @@ * Driver for Microchip 10BASE-T1S PHYs * * Support: Microchip Phys: - * lan8670/1/2 Rev.B1 + * lan8670/1/2 Rev.B1/C1 * lan8650/1 Rev.B0/B1 Internal PHYs */ =20 @@ -12,6 +12,7 @@ #include =20 #define PHY_ID_LAN867X_REVB1 0x0007C162 +#define PHY_ID_LAN867X_REVC1 0x0007C164 /* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation= */ #define PHY_ID_LAN865X_REVB 0x0007C1B3 =20 @@ -290,6 +291,58 @@ static int lan867x_check_reset_complete(struct phy_dev= ice *phydev) return 0; } =20 +static int lan867x_revc1_config_init(struct phy_device *phydev) +{ + s8 offsets[2]; + int ret; + + ret =3D lan867x_check_reset_complete(phydev); + if (ret) + return ret; + + ret =3D lan865x_generate_cfg_offsets(phydev, offsets); + if (ret) + return ret; + + /* LAN867x Rev.C1 configuration settings are equal to the first 9 + * configuration settings and all the sqi fixup settings from LAN865x + * Rev.B0/B1. So the same fixup registers and values from LAN865x + * Rev.B0/B1 are used for LAN867x Rev.C1 to avoid duplication. + * Refer the below links for the comparison. + * https://www.microchip.com/en-us/application-notes/an1760 + * Revision F (DS60001760G - June 2024) + * https://www.microchip.com/en-us/application-notes/an1699 + * Revision E (DS60001699F - June 2024) + */ + for (int i =3D 0; i < 9; i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb_fixup_registers[i], + lan865x_revb_fixup_values[i]); + if (ret) + return ret; + + if (i =3D=3D 1) { + ret =3D lan865x_setup_cfgparam(phydev, offsets); + if (ret) + return ret; + } + } + + ret =3D lan865x_setup_sqi_cfgparam(phydev, offsets); + if (ret) + return ret; + + for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb_sqi_fixup_regs[i], + lan865x_revb_sqi_fixup_values[i]); + if (ret) + return ret; + } + + return 0; +} + static int lan867x_revb1_config_init(struct phy_device *phydev) { int err; @@ -370,6 +423,16 @@ static struct phy_driver microchip_t1s_driver[] =3D { .set_plca_cfg =3D genphy_c45_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1), + .name =3D "LAN867X Rev.C1", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .config_init =3D lan867x_revc1_config_init, + .read_status =3D lan86xx_read_status, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB), .name =3D "LAN865X Rev.B0/B1 Internal Phy", @@ -388,6 +451,7 @@ module_phy_driver(microchip_t1s_driver); =20 static struct mdio_device_id __maybe_unused tbl[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) }, { } }; --=20 2.34.1