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Add one more nested power-domain layer to pass the check. Acked-by: Rob Herring (Arm) Signed-off-by: Fei Shao --- (no changes since v1) .../devicetree/bindings/power/mediatek,power-controller.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index 8985e2df8a56..a7df4041b745 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -54,6 +54,10 @@ patternProperties: patternProperties: "^power-domain@[0-9a-f]+$": $ref: "#/$defs/power-domain-node" + patternProperties: + "^power-domain@[0-9a-f]+$": + $ref: "#/$defs/power-domain-node" + unevaluatedProperties: false unevaluatedProperties: false unevaluatedProperties: false unevaluatedProperties: false --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 12:47:27 2024 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6594B1C2DA4 for ; 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Tue, 01 Oct 2024 04:31:23 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:e044:f156:126b:d5c6]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b264b63d9sm7810646b3a.52.2024.10.01.04.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 04:31:23 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Krzysztof Kozlowski , Bjorn Helgaas , Conor Dooley , Jianjun Wang , Krzysztof Kozlowski , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Lorenzo Bianconi , Lorenzo Pieralisi , Manivannan Sadhasivam , Matthias Brugger , Rob Herring , Ryder Lee , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org Subject: [PATCH v2 2/8] dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only Date: Tue, 1 Oct 2024 19:27:20 +0800 Message-ID: <20241001113052.3124869-3-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241001113052.3124869-1-fshao@chromium.org> References: <20241001113052.3124869-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MediaTek PCIe gen3 bindings, "clocks" accepts a range of 1-6 clocks across all SoCs. But in practice, each SoC requires a particular number of clocks as defined in "clock-names", and the length of "clocks" and "clock-names" can be inconsistent with current bindings. For example: - MT8188, MT8192 and MT8195 all require 6 clocks, while the bindings accept 4-6 clocks. - MT7986 requires 4 clocks, while the bindings accept 4-6 clocks. Update minItems and maxItems properties for individual SoCs as needed to only accept the correct number of clocks. Fixes: c6abd0eadec6 ("dt-bindings: PCI: mediatek-gen3: Add support for Airo= ha EN7581") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Fei Shao --- (no changes since v1) .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 898c1be2d6a4..f05aab2b1add 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -149,7 +149,7 @@ allOf: then: properties: clocks: - minItems: 4 + minItems: 6 =20 clock-names: items: @@ -178,7 +178,7 @@ allOf: then: properties: clocks: - minItems: 4 + minItems: 6 =20 clock-names: items: @@ -207,6 +207,7 @@ allOf: properties: clocks: minItems: 4 + maxItems: 4 =20 clock-names: items: --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 12:47:27 2024 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ACAE1C32F5 for ; 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charset="utf-8" On MediaTek platforms with Multimedia MMU (M4U), a multimedia hardware can be assigned with a local arbiter (LARB) which has a maximum of 32 ports for MediaTek's IOMMU infrastructure. That means there can be at most 32 items in the iommus property in theory. Instead of relaxing the max item count every time a newly introduced device tree hits the limit, bump the number to 32 as an one-time effort. On the other hand, all existing and foreseeable JPEG decoder nodes at this point have at least 2 IOMMUs, so set minItems to 2 accordingly. Signed-off-by: Fei Shao Acked-by: Krzysztof Kozlowski --- It's not in the upstream tree yet, but the upcoming MT8188 DT will have 6 IOMMUs in its JPEG decoder. This patch is to pave the way for that. Changes in v2: New patch. .../devicetree/bindings/media/mediatek-jpeg-decoder.yaml | 3 ++- .../devicetree/bindings/media/mediatek-jpeg-encoder.yaml | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.= yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml index cfabf360f278..a4aacd3eb189 100644 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml @@ -44,7 +44,8 @@ properties: maxItems: 1 =20 iommus: - maxItems: 2 + minItems: 2 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, s= ee Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for deta= ils. diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.= yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml index 83c020a673d6..5b15f8977f67 100644 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml @@ -39,7 +39,7 @@ properties: =20 iommus: minItems: 2 - maxItems: 4 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, s= ee Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for deta= ils. --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 12:47:27 2024 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A65E81C3F01 for ; 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charset="utf-8" Revise the description of MediaTek video decoder to improve wording, fix typos, simplify diagram, and extend the pipeline architecture used in newer MediaTek SoCs (MT8186 and MT8188). Signed-off-by: Fei Shao Acked-by: Krzysztof Kozlowski --- Feedback are welcome. I've tried my best to organize the existing information with some educated guesses, but there might be inaccuracies or gaps still. Please let me know if you have anything to add so we can make this more comprehensive. Thanks! Changes in v2: New patch. .../media/mediatek,vcodec-subdev-decoder.yaml | 100 +++++++++++------- 1 file changed, 59 insertions(+), 41 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index a500a585c692..52a96a5aec96 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -5,52 +5,70 @@ $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.ya= ml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek Video Decode Accelerator With Multi Hardware +title: MediaTek Video Decode Accelerator With Multi Hardware =20 maintainers: - Yunfei Dong =20 description: | - Mediatek Video Decode is the video decode hardware present in Mediatek - SoCs which supports high resolution decoding functionalities. Required - parent and child device node. - - About the Decoder Hardware Block Diagram, please check below: - - +------------------------------------------------+--------------------= -----------------+ - | | = | - | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> co= re HW -> output | - | || || | = || | - +------------||-------------||-------------------+--------------------= -||--------------+ - || lat || | core = workqueue - -------------||-------------||-------------------|--------------------= -||--------------- - ||<------------||----------------HW index----------------= >|| - \/ \/ = \/ - +----------------------------------------------------------= ---+ - | enable/disable = | - | clk power irq iommu = | - | (lat/lat soc/core0/core1) = | - +----------------------------------------------------------= ---+ - - As above, there are parent and child devices, child mean each hardware. = The child device - controls the information of each hardware independent which include clk/= power/irq. - - There are two workqueues in parent device: lat workqueue and core workqu= eue. They are used - to lat and core hardware decoder. Lat workqueue need to get input bitstr= eam and lat buffer, - then enable lat to decode, writing the result to lat buffer, dislabe har= dware when lat decode - done. Core workqueue need to get lat buffer and output buffer, then enab= le core to decode, - writing the result to output buffer, disable hardware when core decode d= one. These two - hardwares will decode each frame cyclically. - - For the smi common may not the same for each hardware, can't combine all= hardware in one node, - or leading to iommu fault when access dram data. - - Lat soc is a hardware which is related with some larb(local arbiter) por= ts. For mt8195 - platform, there are some ports like RDMA, UFO in lat soc larb, need to e= nable its power and - clock when lat start to work, don't have interrupt. - - mt8195: lat soc HW + lat HW + core HW - mt8192: lat HW + core HW + MediaTek Video Decode Accelerator is the video decoding hardware present= in + MediaTek SoCs that supports high-resolution decoding functionalities. + It consists of parent and child nodes. + + The decoder hardware block diagram is shown below: + + +------------------------------------------------+--------------------= ----------+ + | | = | + | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> outpu= t buffer | + | || || | || = | + +--------------||-----------||-------------------+-------||-----------= ----------+ + LAT Workqueue | Core Workqueue = + ---------------||-----------||-------------------|-------||-----------= ----------- + ||<----------||---------HW index--------->|| = + \/ \/ \/ + +-------------------------------------------------------------+ + | enable/disable | + | clk power irq iommu | + | (lat/lat-soc/core0/core1) | + +-------------------------------------------------------------+ + + The child nodes represent the individual hardware blocks within the deco= ding + pipeline, such as LAT-SoC, LAT and Core. + Each child node is responsible for managing the dedicated resources of t= he + hardware, such as clocks, power domains, interrupts and IOMMUs. + + The parent node is a central point of control for the child nodes. + It identifies the specific video decoding pipeline architecture used by = the + SoC, manages the shared resources like workqueues and platform data, and + handles V4L2 API calls on behalf of the underlying hardware. + + The parent utilizes two workqueues to manage the decoding process. + 1. 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charset="utf-8" Add the missing dma-ranges property to the soc node, similar to how it was done for MT8195 and MT8192. This allows the entire 16GB of iova range to be used and enables multimedia processing usages, like vcodec and MIPI camera. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index cd27966d2e3c..69390da9cfe0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -878,6 +878,7 @@ soc { #address-cells =3D <2>; #size-cells =3D <2>; compatible =3D "simple-bus"; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x4 0x0>; ranges; =20 gic: interrupt-controller@c000000 { --=20 2.46.1.824.gd892dcdcdd-goog From nobody Thu Nov 28 12:47:27 2024 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 332C71C3F30 for ; Tue, 1 Oct 2024 11:31:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The MediaTek mmsys is more than just a clock controller; it's a system controller. In addition to clock controls, it provides display pipeline routing controls and other miscellaneous control registers. On the MT8188 and MT8195 SoCs, the mmsys blocks utilize the same mmsys driver but have been aliased to "vdosys" and "vppsys", likely to better represent their actual functionality. Update the vppsys node names and compatibles in MT8188 DT to reflect that and fix dtbs_check errors against mediatek/mt8188-evb.dtb. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Fei Shao --- (no changes since v1) arch/arm64/boot/dts/mediatek/mt8188.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 69390da9cfe0..790315c1bdb3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1779,8 +1779,8 @@ mfgcfg: clock-controller@13fbf000 { #clock-cells =3D <1>; }; =20 - vppsys0: clock-controller@14000000 { - compatible =3D "mediatek,mt8188-vppsys0"; + vppsys0: syscon@14000000 { + compatible =3D "mediatek,mt8188-vppsys0", "syscon"; reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; }; @@ -1797,8 +1797,8 @@ wpesys_vpp0: clock-controller@14e02000 { #clock-cells =3D <1>; }; =20 - vppsys1: clock-controller@14f00000 { - compatible =3D "mediatek,mt8188-vppsys1"; + vppsys1: syscon@14f00000 { + compatible =3D "mediatek,mt8188-vppsys1", "syscon"; reg =3D <0 0x14f00000 0 0x1000>; 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Tue, 01 Oct 2024 04:31:38 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:e044:f156:126b:d5c6]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b264b63d9sm7810646b3a.52.2024.10.01.04.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 04:31:37 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 7/8] arm64: dts: mediatek: mt8188: Move vdec1 power domain under vdec0 Date: Tue, 1 Oct 2024 19:27:25 +0800 Message-ID: <20241001113052.3124869-8-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241001113052.3124869-1-fshao@chromium.org> References: <20241001113052.3124869-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MT8188 video decoder pipeline has two hardware IP blocks: LAT and Core, which are powered by vdec0 and vdec1 power domains, respectively. The hardware design includes a dependency between the vdec0 and vdec1 power domains to ensure that Core is powered down before LAT. Without correctly describing this dependency in DT, the system will fail to suspend. As a comparable reference, MT8192 also uses the LAT + Core decoding pipeline, and it has the correct power domain dependency defined in DT. Update vdec1 as a sub-domain of vdec0 in MT8188 DT to reflect the hardware design. Also, use more specific clock names for both power domains. Signed-off-by: Fei Shao --- Changes in v2: Revise commit message. arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index 790315c1bdb3..ca50ed20fca0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1062,20 +1062,22 @@ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { #power-domain-cells =3D <0>; }; =20 - power-domain@MT8188_POWER_DOMAIN_VDEC1 { - reg =3D ; - clocks =3D <&vdecsys CLK_VDEC2_LARB1>; - clock-names =3D "ss-vdec"; - mediatek,infracfg =3D <&infracfg_ao>; - #power-domain-cells =3D <0>; - }; - power-domain@MT8188_POWER_DOMAIN_VDEC0 { reg =3D ; clocks =3D <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; - clock-names =3D "ss-vdec"; + clock-names =3D "ss-vdec1-soc-l1"; mediatek,infracfg =3D <&infracfg_ao>; - #power-domain-cells =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; 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charset="utf-8" Move the #address-cells and #size-cells properties from the board dts to SoC dtsi to be reused by other boards and avoid duplicated lines. Signed-off-by: Fei Shao --- Changes in v2: New patch. arch/arm64/boot/dts/mediatek/mt8188-evb.dts | 2 -- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8188-evb.dts index 68a82b49f7a3..f89835ac36f3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts @@ -140,8 +140,6 @@ &mt6359_vrf12_ldo_reg { &nor_flash { pinctrl-names =3D "default"; pinctrl-0 =3D <&nor_pins_default>; - #address-cells =3D <1>; - #size-cells =3D <0>; status =3D "okay"; =20 flash@0 { diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi index ca50ed20fca0..e2c6ed816507 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1618,6 +1618,8 @@ nor_flash: spi@1132c000 { clock-names =3D "spi", "sf", "axi"; assigned-clocks =3D <&topckgen CLK_TOP_SPINOR>; interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; status =3D "disabled"; }; =20 --=20 2.46.1.824.gd892dcdcdd-goog