From nobody Thu Nov 28 13:49:15 2024 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C42262B9B0; Tue, 1 Oct 2024 09:34:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727775293; cv=none; b=lBQ+BzAsJgMh9T0frFEfNcvjamIEpANUl6r94AXXwyanwIvsmrx3S9Yz+x/sA0WDrQvivJSJMBWPPs8j3pFFmUY1XCG4vvp3tsdb7w5eaOemQwVcBpvwo8JAakCGUKiRyyI96dAOTQlMi3IpQyGbkNC+WBPWRmCf9yVObc3uaJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727775293; c=relaxed/simple; bh=nPAhLL4dCEvf+6KLCH+xxbdHbJQ75yK2bzAeNuHjg7Y=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=troM/FB8Gb0VN/psMummBbZweO24ykpBoEu2B7GqDMU7KEXgd57xdpvNAGuOo5LMtF8mniVOmBgiIirJZ9AhV4MIbqIMTQ/jmfeOl82I/R3hVaC+0DNz2V71FpAJ3l7/IRHcDGA4fPtXD46Arw3AfT2Yhp736p4xF93uYunoHiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=BulZI2t7; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BulZI2t7" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 4919YWS1016155; Tue, 1 Oct 2024 04:34:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727775272; bh=FtgklXq5IUBxZsv7K/tdb7i/ncVceTgGqh8VSnQk5x4=; h=From:To:CC:Subject:Date; b=BulZI2t7hXg+ac0Ep74w8KV8figqkyD5VrQI2FLJKt0e5465grdBYVgRyNJdEDZFK PVJV9JeGtU2OUDza6MTGD9WyoOvKh1/G6XE2hzBJdnR/4aMwOkh6uvdVA5DCoF3OtA XhDGtWMA9DBwjBkDVgL/PQlzP77Yco1S2RYXVmqc= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 4919YWoX008355 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 1 Oct 2024 04:34:32 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 1 Oct 2024 04:34:31 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 1 Oct 2024 04:34:31 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.81]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4919YRTt000755; Tue, 1 Oct 2024 04:34:28 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH v2] arm64: dts: ti: k3-j7200-evm: Add overlay for PCIE1 Endpoint Mode Date: Tue, 1 Oct 2024 15:04:26 +0530 Message-ID: <20241001093426.3401765-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add overlay to enable the PCIE1 instance of PCIe on J7200-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli --- Hello, This patch is based on linux-next tagged next-20241001. v1: https://lore.kernel.org/r/20240304094559.76406-1-s-vadapalli@ti.com/ Changes since v1: - Rebased patch on next-20241001. Logs validating overlay with J784S4-EVM as Root-Complex and J7200-EVM as Endpoint: https://gist.github.com/Siddharth-Vadapalli-at-TI/38364f5fc47b670fff4ef65dc= f60b9fc Regards, Siddharth. arch/arm64/boot/dts/ti/Makefile | 5 ++ .../boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 53 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index bcd392c3206e..3ced231d273e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am654-pcie-usb3.dtbo # Boards with J7200 SoC k3-j7200-evm-dtbs :=3D k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-po= rt-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j7200-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j7200-evm-pcie1-ep.dtbo =20 # Boards with J721e SoC k3-j721e-evm-dtbs :=3D k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-po= rt-eth-exp.dtbo @@ -188,6 +189,8 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs :=3D k3-am6= 8-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am69-sk-csi2-dual-imx219-dtbs :=3D k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo +k3-j7200-evm-pcie1-ep-dtbs :=3D k3-j7200-common-proc-board.dtb \ + k3-j7200-evm-pcie1-ep.dtbo k3-j721e-common-proc-board-infotainment-dtbs :=3D k3-j721e-common-proc-boa= rd.dtb \ k3-j721e-common-proc-board-infotainment.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ @@ -221,6 +224,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ + k3-j7200-evm-pcie1-ep.dtbo \ k3-j721e-common-proc-board-infotainment.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ @@ -243,6 +247,7 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-am68-sk-base-board +=3D -@ DTC_FLAGS_k3-am69-sk +=3D -@ +DTC_FLAGS_k3-j7200-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721e-sk +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64= /boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso new file mode 100644 index 000000000000..3cc315a0e084 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with t= he + * J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXC= PXEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 240 6>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + }; +}; --=20 2.40.1