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charset="utf-8" Since there are no registers controlling the hardware parameters IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be declared in the device tree. snps,bus-capacitance-pf indicates the bus capacitance in picofarads (pF). It affects the high and low pulse width of SCL line in high speed mode. The legal values for this property are 100 and 400 only, and default value is 100. This property corresponds to IC_CAP_LOADING. snps,clk-freq-optimized indicates whether the hardware input clock frequency is reduced by reducing the internal latency. This property corresponds to IC_CLK_FREQ_OPTIMIZATION. The driver can calculate hs_hcnt and hs_lcnt appropriate for the hardware based on these two properties. Signed-off-by: Michael Wu --- .../bindings/i2c/snps,designware-i2c.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml= b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 60035a787e5c..c373f3acd34b 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -97,6 +97,21 @@ properties: - const: tx - const: rx =20 + snps,bus-capacitance-pf: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + This property indicates the bus capacitance in picofarads (pF). + This value is used to compute the tHIGH and tLOW periods for high sp= eed + mode. + default: 100 + + snps,clk-freq-optimized: + description: > + This property indicates whether the hardware input clock frequency is + reduced by reducing the internal latency. This value is used to comp= ute + the tHIGH and tLOW periods for high speed mode. + type: boolean + unevaluatedProperties: false =20 required: @@ -146,4 +161,13 @@ examples: interrupts =3D <8>; clocks =3D <&ahb_clk>; }; + - | + i2c@c5000000 { + compatible =3D "snps,designware-i2c"; + reg =3D <0xc5000000 0x1000>; + interrupts =3D <37 1>; + clock-frequency =3D <400000>; + snps,bus-capacitance-pf =3D <400>; + snps,clk-freq-optimized; + }; ... --=20 2.43.0 From nobody Thu Nov 28 12:54:42 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2136.outbound.protection.outlook.com [40.107.223.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7416219D891; Tue, 1 Oct 2024 08:30:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.136 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727771446; 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However, the set of these fixed values only applies to the combination of hardware parameters IC_CAP_LOADING =3D 400pF and IC_CLK_FREQ_OPTIMIZATION =3D 1. Outside of this combination, if these fixed tHIGH =3D 160 and tLOW =3D 120 are still used, the calculated hs_hcnt and hs_lcnt may not be small enough, making it impossible for the SCL frequency to reach 3.4 MHz. Section 3.15.4.5 in DesignWare DW_apb_i2b Databook v2.03 says that when IC_CLK_FREQ_OPTIMIZATION =3D 0, MIN_SCL_HIGHtime =3D 60 ns for 3.4 Mbps, bus loading =3D 100pF =3D 120 ns for 3.4 Mbps, bus loading =3D 400pF MIN_SCL_LOWtime =3D 160 ns for 3.4 Mbps, bus loading =3D 100pF =3D 320 ns for 3.4 Mbps, bus loading =3D 400pF and section 3.15.4.6 says that when IC_CLK_FREQ_OPTIMIZATION =3D 1, MIN_SCL_HIGHtime =3D 60 ns for 3.4 Mbps, bus loading =3D 100pF =3D 160 ns for 3.4 Mbps, bus loading =3D 400pF MIN_SCL_LOWtime =3D 120 ns for 3.4 Mbps, bus loading =3D 100pF =3D 320 ns for 3.4 Mbps, bus loading =3D 400pF In order to calculate more accurate hs_hcnt amd hs_lcnt, two hardware parameters IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION must be considered together. Signed-off-by: Michael Wu --- drivers/i2c/busses/i2c-designware-common.c | 5 +++++ drivers/i2c/busses/i2c-designware-core.h | 5 +++++ drivers/i2c/busses/i2c-designware-master.c | 23 ++++++++++++++++++++-- 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 080204182bb5..9599be1de775 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -380,6 +380,11 @@ int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *d= ev) =20 i2c_parse_fw_timings(device, t, false); =20 + if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus= _capacitance_pf)) + dev->bus_capacitance_pf =3D 100; + + dev->clk_freq_optimized =3D device_property_read_bool(device, "snps,clk-f= req-optimized"); + i2c_dw_adjust_bus_speed(dev); =20 if (is_of_node(fwnode)) diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index 1ac2afd03a0a..44c97bf15843 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -240,6 +240,9 @@ struct reset_control; * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE * @rinfo: I=C2=B2C GPIO recovery information + * @bus_capacitance_pf: bus capacitance in picofarads + * @clk_freq_optimized: indicate whether hardware input clock frequency is + * reduced by reducing the internal latency * * HCNT and LCNT parameters can be used if the platform knows more accurate * values than the one computed based only on the input clock frequency. @@ -297,6 +300,8 @@ struct dw_i2c_dev { int (*set_sda_hold_time)(struct dw_i2c_dev *dev); int mode; struct i2c_bus_recovery_info rinfo; + u32 bus_capacitance_pf; + bool clk_freq_optimized; }; =20 #define ACCESS_INTR_MASK BIT(0) diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busse= s/i2c-designware-master.c index e46f1b22c360..3dbc94db94a4 100644 --- a/drivers/i2c/busses/i2c-designware-master.c +++ b/drivers/i2c/busses/i2c-designware-master.c @@ -154,12 +154,31 @@ static int i2c_dw_set_timings_master(struct dw_i2c_de= v *dev) dev->hs_hcnt =3D 0; dev->hs_lcnt =3D 0; } else if (!dev->hs_hcnt || !dev->hs_lcnt) { + u32 t_high, t_low; + + /* + * The legal values stated in the databook for bus + * capacitance are only 100pF and 400pF. + * If dev->bus_capacitance_pf is greater than or equals + * to 400, t_high and t_low are assumed to be + * appropriate values for 400pF, otherwise 100pF. + */ + if (dev->bus_capacitance_pf >=3D 400) { + /* assume bus capacitance is 400pF */ + t_high =3D dev->clk_freq_optimized ? 160 : 120; + t_low =3D 320; + } else { + /* assume bus capacitance is 100pF */ + t_high =3D 60; + t_low =3D dev->clk_freq_optimized ? 120 : 160; + } + ic_clk =3D i2c_dw_clk_rate(dev); dev->hs_hcnt =3D i2c_dw_scl_hcnt(dev, DW_IC_HS_SCL_HCNT, ic_clk, - 160, /* tHIGH =3D 160 ns */ + t_high, sda_falling_time, 0, /* DW default */ 0); /* No offset */ @@ -167,7 +186,7 @@ static int i2c_dw_set_timings_master(struct dw_i2c_dev = *dev) i2c_dw_scl_lcnt(dev, DW_IC_HS_SCL_LCNT, ic_clk, - 320, /* tLOW =3D 320 ns */ + t_low, scl_falling_time, 0); /* No offset */ } --=20 2.43.0