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charset="utf-8" The am625 is capable of running at 1.4 GHz when VDD_CORE is increased from 0.75V to 0.85V. Here we add a 1.4 GHz node to the a53_opp_table and increase the VDD_CORE voltage accordingly. Signed-off-by: Garrett Giordano Reviewed-by: Wadim Egorov --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index 43488cc8bcb1..236b94c0248c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -173,6 +173,13 @@ AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ }; }; =20 +&a53_opp_table { + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + }; +}; + &cpsw3g { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>; @@ -226,8 +233,8 @@ pmic@30 { regulators { vdd_core: buck1 { regulator-name =3D "VDD_CORE"; - regulator-min-microvolt =3D <750000>; - regulator-max-microvolt =3D <750000>; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; regulator-boot-on; regulator-always-on; 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b=gJP3dpasUa4h3Vh1eY2mw7IZ9ZjeJ7U31PCVaFxE7BXzdB+YE+7MwarLIbCH+vxM7JEpRGkNc1+LcCu+1Jho6VFjhfRXefoeVjmEBwm1tpail89hpO9iXZozhI9EYpn8k04JvMkYF/fike3+VL0EN33tK4HmsjIU1/jW+s4rq24= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=phytec.com; Received: from SJ2PR22MB4354.namprd22.prod.outlook.com (2603:10b6:a03:537::8) by LV8PR22MB5551.namprd22.prod.outlook.com (2603:10b6:408:232::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.28; Tue, 1 Oct 2024 07:19:50 +0000 Received: from SJ2PR22MB4354.namprd22.prod.outlook.com ([fe80::789c:e41e:1367:383d]) by SJ2PR22MB4354.namprd22.prod.outlook.com ([fe80::789c:e41e:1367:383d%5]) with mapi id 15.20.8005.024; Tue, 1 Oct 2024 07:19:50 +0000 From: Garrett Giordano To: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh@kernel.org, krzk+dt@kernel.org, w.egorov@phytec.de Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@lists.phytec.de Subject: [PATCH v2 2/2] Revert "arm64: dts: ti: am62-phyboard-lyra: Add overlay to increase cpu frequency to 1.4 GHz" Date: Tue, 1 Oct 2024 00:19:16 -0700 Message-Id: <20241001071916.1362213-3-ggiordano@phytec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001071916.1362213-1-ggiordano@phytec.com> References: <20241001071916.1362213-1-ggiordano@phytec.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: CH2PR05CA0069.namprd05.prod.outlook.com (2603:10b6:610:38::46) To SJ2PR22MB4354.namprd22.prod.outlook.com (2603:10b6:a03:537::8) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR22MB4354:EE_|LV8PR22MB5551:EE_ X-MS-Office365-Filtering-Correlation-Id: df5065fc-b02d-4cf7-6ac1-08dce1e96fc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|7416014|52116014|1800799024|38350700014; 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charset="utf-8" We now configure the a53_opp_table to include a 1.4 GHz node and set our VDD_CORE to 0.85v in the k3-am62-phycore-som.dtsi. This change is to match our PMIC which is now set to output 0.85v by default. This reverts commit 7a5775a3da906dab059b8de60a2b88f6016cb4b8. Signed-off-by: Garrett Giordano --- Changes in v2: - Use git revert to revert the change arch/arm64/boot/dts/ti/Makefile | 3 --- .../k3-am625-phyboard-lyra-1-4-ghz-opp.dtso | 20 ------------------- 2 files changed, 23 deletions(-) delete mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-o= pp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index e20b27ddf901..44052354503a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -22,7 +22,6 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-verdin-wifi-yavia.dtb -dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk-nand.dtbo @@ -124,8 +123,6 @@ k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beag= leplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo k3-am625-beagleplay-csi2-tevi-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtbo -k3-am625-phyboard-lyra-1-4-ghz-opp.dtbs :=3D k3-am625-phyboard-lyra-rdk.dt= b \ - k3-am625-phyboard-lyra-1-4-ghz-opp.dtbo k3-am625-phyboard-lyra-disable-eth-phy-dtbs :=3D k3-am625-phyboard-lyra-rd= k.dtb \ k3-am6xx-phycore-disable-eth-phy.dtbo k3-am625-phyboard-lyra-disable-rtc-dtbs :=3D k3-am625-phyboard-lyra-rdk.dt= b \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso= b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso deleted file mode 100644 index 6ec6d57ec49c..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-1-4-ghz-opp.dtso +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Copyright (C) 2024 PHYTEC America LLC - * Author: Nathan Morrisson - */ - -/dts-v1/; -/plugin/; - -&vdd_core { - regulator-min-microvolt =3D <850000>; - regulator-max-microvolt =3D <850000>; -}; - -&a53_opp_table { - opp-1400000000 { - opp-hz =3D /bits/ 64 <1400000000>; - opp-supported-hw =3D <0x01 0x0004>; - }; -}; -- 2.25.1