From nobody Thu Nov 28 16:43:57 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACECC1B1D6B; Tue, 1 Oct 2024 04:39:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727757582; cv=none; b=Xx0GMmjxycsXlTYGQ/kUByNuqJf0vuRjsMe3hRiqAGI/vZqaio2C1zfK0ITzfpN1FTuNa5p6YBeN2MwCTLPeGM4j0HeGPdfNqnV4D49MctaMY7txHp726YuwDU95McJBMqhWvXqTAmICuAtW84Lgi3wgaAhuM455/1vOpEZ27ow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727757582; c=relaxed/simple; bh=qRlFYk4dROIAZ51SrQ+l7xbvXRsYyx2thqhkXohUYrI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q145NkuqV1HbDt+E2+3Ar79aCaFJb2hDo3WRh+IBG3MPpFUtPMm8wAIHIpii4p/fd81hVs2zYEoLfT8XvELmOOGRD+p5RdSNQtprQnL65pKxIYNuZezUwtcumd17nQ/QIneHs4gkbpVT5UhrTt2BWjUd4+UaWZEFioeOJ5L9iro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=hL9qMI7X; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="hL9qMI7X" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0A9D523D6A; Tue, 1 Oct 2024 06:39:39 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id XM4t5ca97D9N; Tue, 1 Oct 2024 06:39:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727757578; bh=qRlFYk4dROIAZ51SrQ+l7xbvXRsYyx2thqhkXohUYrI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hL9qMI7XWchMhs1+8uYVqMVSg699F4yDlTU6/3vuzX0dDJ19Hatnpd3yjIuyZnjBt 4YcH2Le5bk26lvbLqhWl0g85Np2rU1WxpGg9O103SJLn3i+MOowRVYkDMV5pLYmmSb gW7lGAYiUxaqBLt0yGludSzeFe0lpdyYCmOWaaJyeiutI3nS7/+cek+Q7LxqQvRFPO myiJxiZLZZomiWRz7WZP9IUxfV1YZ1Bg0uj3fhCdJYca6ZKkUtrIjq8MMR2nWH86vu k0XSj8xCaygNj+DiNnUTNu/5Ldar3YBDJPPpGeiMneBGr5VZjZvJfTEwCrWdQRCbhc 6SVq7M+0Y1ozg== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 7/8] arm64: dts: rockchip: Add clock generators for RK3528 SoC Date: Tue, 1 Oct 2024 04:38:37 +0000 Message-ID: <20241001043838.31963-1-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt node for RK3528 clock and reset unit. Clock "phy_50m_out" is generated by internal Ethernet phy, a fixed clock node is added as a placeholder to avoid orphans. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index e58faa985aa4..c0552ff7cd31 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -6,6 +6,7 @@ =20 #include #include +#include =20 / { compatible =3D "rockchip,rk3528"; @@ -95,6 +96,13 @@ xin24m: clock-xin24m { #clock-cells =3D <0>; }; =20 + phy50m_clk: clock-phy50m { + compatible =3D "fixed-clock"; + clock-frequency =3D <50000000>; + clock-output-names =3D "phy_50m_out"; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; ranges =3D <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; @@ -114,6 +122,47 @@ gic: interrupt-controller@fed01000 { #interrupt-cells =3D <3>; }; =20 + cru: clock-controller@ff4a0000 { + compatible =3D "rockchip,rk3528-cru"; + reg =3D <0x0 0xff4a0000 0x0 0x30000>; + assigned-clocks =3D + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>; + assigned-clock-rates =3D + <32768>, <1188000000>, + <1000000000>, <996000000>, + <408000000>, <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + uart0: serial@ff9f0000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xff9f0000 0x0 0x100>; --=20 2.46.0