From nobody Thu Nov 28 15:34:18 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E743E1B652D; Tue, 1 Oct 2024 04:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756755; cv=none; b=W0ZyAq+4SxFvzugAtrsJja+psptAmkfBWK8olQQhMGVMSkOtUqZCm0EHHQqQigqJ9z9POuX1VYJTkQM0XBr9JL6W4bCqs0q2/3uPesOuYY0zH/gLQWbKrlFRJv9m3bbFLcnqI5q6VPgyhxHkV0LPySKVHLjJMAk67ACpCLvAXNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756755; c=relaxed/simple; bh=zX7e8iV9phckFaC5bqESpnimFOhE4jLq8O6rmpwV3M0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LTcmK0gP4J71tVfYhJZdmS8rchYdeDXUyhWkauuf/XjQ4ftKPQVTxfQGS/3yiXmpkZHd2Ks+/pv+otJ9PqLBHWsJ6CAHFU9g09ynfBdbGAkWvsAQrOjme/aQeacBNPQ28TFMOPqnf+5WcmHFEt6O4Ny/LKOOuTSsTAS/fdRIHAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ipbCdSh1; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ipbCdSh1" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 665D223CB2; Tue, 1 Oct 2024 06:25:52 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 8us6GjPoTX2f; Tue, 1 Oct 2024 06:25:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756751; bh=zX7e8iV9phckFaC5bqESpnimFOhE4jLq8O6rmpwV3M0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ipbCdSh1gEKqLJpQwYh+By6BVU2tbxf5TD4lgl1Cqv/xWBEzTkjfMu9KkvYuLC94N dB05M9uiHIl0PSnHTN8C7yDuTEt2fO2ENymo2Ndc/i70oxqlgSmlsg2eQ3FORjQaFC cOT1Q3+XHKJF7sJW/jbCE4GJm6H2FGGC8B7qVHozgSTyAvfoIzfePavE0yTFl8SyP9 g26Dt1mmbI+oqe0NfDD8/+gTbgJrBdjP9gL3aaCZpavgFd/TdhZ8kSuqH8IYuGEuw/ b+CIAVzqC5E6C1mJAMZ3V82arLd/o4IjJ5vC2wNVTmqzqYW602A7svSnXE68evrHBI P1nEFHV0kGJEQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 5/8] clk: rockchip: Add clock type GATE_NO_SET_RATE Date: Tue, 1 Oct 2024 04:23:59 +0000 Message-ID: <20241001042401.31903-7-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This clock type is similar to GATE, but doesn't allow rate setting, which presents on RK3528 platform. Signed-off-by: Yao Zi --- drivers/clk/rockchip/clk.c | 8 ++++++++ drivers/clk/rockchip/clk.h | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 73d2cbdc716b..7d233770e68b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -521,6 +521,14 @@ void rockchip_clk_register_branches(struct rockchip_cl= k_provider *ctx, case branch_gate: flags |=3D CLK_SET_RATE_PARENT; =20 + clk =3D clk_register_gate(NULL, list->name, + list->parent_names[0], flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); + break; + case branch_gate_no_set_rate: + flags &=3D ~CLK_SET_RATE_PARENT; + clk =3D clk_register_gate(NULL, list->name, list->parent_names[0], flags, ctx->reg_base + list->gate_offset, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 1efc5c3a1e77..360d16402fe5 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -519,6 +519,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_gate_no_set_rate, branch_mmc, branch_inverter, branch_factor, @@ -844,6 +845,19 @@ struct rockchip_clk_branch { .gate_flags =3D gf, \ } =20 +#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \ + { \ + .id =3D _id, \ + .branch_type =3D branch_gate_no_set_rate, \ + .name =3D cname, \ + .parent_names =3D (const char *[]){ pname }, \ + .num_parents =3D 1, \ + .flags =3D f, \ + .gate_offset =3D o, \ + .gate_shift =3D b, \ + .gate_flags =3D gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id =3D _id, \ --=20 2.46.0