From nobody Thu Nov 28 15:39:39 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 783421B5EC5; Tue, 1 Oct 2024 04:25:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756751; cv=none; b=LiggwVt9Djvap4dvQOXtk67fj2Yvj+tSaiVoegc2WdXKozGM0JCATqhv1hpsjh9Fil01qe6AC3sipNs6/b2HUqYokNCKzgTQ6492leEUCPI6okkRaDm+4in9/vkdORSoBG/3bsTKE8MAEx99xhwR2t5XqD242i4X4+DwhdGUoQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756751; c=relaxed/simple; bh=g3/xsaggoBD8STCM4ioqMxyKkwu2ClnVteNZa156RfA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fOlVYpmeMcO6jKIdWqTL0mqBHkb6OKsK1tUjkXBtn9yKkIwWKp241RDkAwDpmexmq0mv/vOq2EYr/2+cZdiZcOWR2XIyecJ+fG7x6WcBbbeQ9Udq8rjLWXBHaN5PULIA1DAiRBOeAvXpnHK7XtYQ3hOYmVE+i+srnXikqsQUJG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=KTHaUHi1; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="KTHaUHi1" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0867823CB2; Tue, 1 Oct 2024 06:25:49 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id EQi-h7-SyM0d; Tue, 1 Oct 2024 06:25:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756748; bh=g3/xsaggoBD8STCM4ioqMxyKkwu2ClnVteNZa156RfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KTHaUHi1CaAPViTnRp4BcBT/sKGPTXc54XXajNENC0cMFzf3fe7XB/TMz/nIZoKxZ 9bO5sZ2xuKZ1kWtbp4uh3dc2gRCYDnphjrfbS2pSvXeCdbMHfabSCq7QTNuKjMpstA SmC9SJc0iUh8JppZXanppafF9RaIyIIjucv1O0qoKMBXIrJWQGuQAxWNJI4TDvjWDt AmPgfbu4ki53n0Vyl8EEK9yHx1nuJtifBZCM5TnnVIUYxzlnOVMmDVcmtHmenP1Uyv zzZ6SY2jaZl1H1q171JJRHoexOR34HzXWjATQhMuWnFRhNAav6t1Pf7JE0m08zFCZw glskzc2BSudwQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 4/8] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE Date: Tue, 1 Oct 2024 04:23:58 +0000 Message-ID: <20241001042401.31903-6-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE, which should operate in normal mode only. Add corresponding definition and handle it in code. Signed-off-by: Yao Zi --- drivers/clk/rockchip/clk-pll.c | 10 ++++++---- drivers/clk/rockchip/clk.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 606ce5458f54..46be1c67301a 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rock= chip_clk_pll *pll, rockchip_rk3036_pll_get_params(pll, &cur); cur.rate =3D 0; =20 - cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); - if (cur_parent =3D=3D PLL_MODE_NORM) { - pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); - rate_change_remuxed =3D 1; + if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { + cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent =3D=3D PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed =3D 1; + } } =20 /* update pll values */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..1efc5c3a1e77 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -391,6 +391,7 @@ struct rockchip_pll_rate_table { * Flags: * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the * rate_table parameters and ajust them if necessary. + * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only */ struct rockchip_pll_clock { unsigned int id; @@ -408,6 +409,7 @@ struct rockchip_pll_clock { }; =20 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) =20 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \ --=20 2.46.0