From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2205F1B5326; Tue, 1 Oct 2024 04:25:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756743; cv=none; b=XMstfMDds0AHQ+LOIyDdCNKn+TglRsD9CeOFywtNSQ7OSSnsSSNfElYKyhSaX52R5v1noI7jvLBMZcjGLiO5RbInjEGM4hN571IKSpLasVgsOp/kIPDuc82CTIoWl8HnQG/Iy5qeqB57GHmakdINtF/nzIj2KfmAinZyoZPOquc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756743; c=relaxed/simple; bh=HWD6B2FwS6vV97o62BmUuy3CASxt4hNCIMzcSVrNeBA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tC7TApQX875CoFoHoAqf9vyWpif5hfyl/X+eVxM16PiRT7FTn2H9zxitnxgcmMyUUGrgXgx3hMvaIqqL6+FEMescUCRxFPbUYF5DKm+f+tDs2GTDCJon3Jh8j6ffYig0wV8l5YqFjX6YK07AjbAlcryadefbcVD0y6pxb3DRkqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Symtdxai; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Symtdxai" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 5A13C23D82; Tue, 1 Oct 2024 06:25:39 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id mmpSJTWIq1dL; Tue, 1 Oct 2024 06:25:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756738; bh=HWD6B2FwS6vV97o62BmUuy3CASxt4hNCIMzcSVrNeBA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Symtdxaic0ugR+2AokFbZtqu3vJ1Fp8EnPtfGIJDBIu5nJIeHQZzcCeLpDoTnzaMl ORZkczOoFh9LR2nsMe6tMfNOW3h3UVuRKMcO+m8b5IjqQmN0HVok3Ei41yyrWIGwEt twnU5GCQuiN1ZF1ahyBfupYQb3e2oDcGAxxjJrqDKWNddE3iYFwcpH0u0NBTseQ5I+ 1k2c2oQdvF6qsVvIVIi89yJ3l9UlqHYu8u5ec6Vt7KtOP0UjjGs6pVIHzsZwY7amMJ NLjuV8dxWQ90lT2qs3+y12+gxTYaksPxWWODsslIt/VX/gZTsgLZWFvh2lQ0mGWJS9 1wcj8alxpZ+Ig== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 1/8] dt-bindings: clock: Add clock ID definition for Rockchip RK3528 Date: Tue, 1 Oct 2024 04:23:55 +0000 Message-ID: <20241001042401.31903-3-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are two types of clocks in RK3528 SoC, CRU-managed and SCMI-managed. They are assigned independent clock IDs. Signed-off-by: Yao Zi --- .../dt-bindings/clock/rockchip,rk3528-cru.h | 453 ++++++++++++++++++ 1 file changed, 453 insertions(+) create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-b= indings/clock/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..c90b25f57973 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi + * Author: Joseph Chen + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 1 +#define PLL_CPLL 2 +#define PLL_GPLL 3 +#define PLL_PPLL 4 +#define PLL_DPLL 5 +#define ARMCLK 6 +#define XIN_OSC0_HALF 8 +#define CLK_MATRIX_50M_SRC 9 +#define CLK_MATRIX_100M_SRC 10 +#define CLK_MATRIX_150M_SRC 11 +#define CLK_MATRIX_200M_SRC 12 +#define CLK_MATRIX_250M_SRC 13 +#define CLK_MATRIX_300M_SRC 14 +#define CLK_MATRIX_339M_SRC 15 +#define CLK_MATRIX_400M_SRC 16 +#define CLK_MATRIX_500M_SRC 17 +#define CLK_MATRIX_600M_SRC 18 +#define CLK_UART0_SRC 19 +#define CLK_UART0_FRAC 20 +#define SCLK_UART0 21 +#define CLK_UART1_SRC 22 +#define CLK_UART1_FRAC 23 +#define SCLK_UART1 24 +#define CLK_UART2_SRC 25 +#define CLK_UART2_FRAC 26 +#define SCLK_UART2 27 +#define CLK_UART3_SRC 28 +#define CLK_UART3_FRAC 29 +#define SCLK_UART3 30 +#define CLK_UART4_SRC 31 +#define CLK_UART4_FRAC 32 +#define SCLK_UART4 33 +#define CLK_UART5_SRC 34 +#define CLK_UART5_FRAC 35 +#define SCLK_UART5 36 +#define CLK_UART6_SRC 37 +#define CLK_UART6_FRAC 38 +#define SCLK_UART6 39 +#define CLK_UART7_SRC 40 +#define CLK_UART7_FRAC 41 +#define SCLK_UART7 42 +#define CLK_I2S0_2CH_SRC 43 +#define CLK_I2S0_2CH_FRAC 44 +#define MCLK_I2S0_2CH_SAI_SRC 45 +#define CLK_I2S3_8CH_SRC 46 +#define CLK_I2S3_8CH_FRAC 47 +#define MCLK_I2S3_8CH_SAI_SRC 48 +#define CLK_I2S1_8CH_SRC 49 +#define CLK_I2S1_8CH_FRAC 50 +#define MCLK_I2S1_8CH_SAI_SRC 51 +#define CLK_I2S2_2CH_SRC 52 +#define CLK_I2S2_2CH_FRAC 53 +#define MCLK_I2S2_2CH_SAI_SRC 54 +#define CLK_SPDIF_SRC 55 +#define CLK_SPDIF_FRAC 56 +#define MCLK_SPDIF_SRC 57 +#define DCLK_VOP_SRC0 58 +#define DCLK_VOP_SRC1 59 +#define CLK_HSM 60 +#define CLK_CORE_SRC_ACS 63 +#define CLK_CORE_SRC_PVTMUX 65 +#define CLK_CORE_SRC 66 +#define CLK_CORE 67 +#define ACLK_M_CORE_BIU 68 +#define CLK_CORE_PVTPLL_SRC 69 +#define PCLK_DBG 70 +#define SWCLKTCK 71 +#define CLK_SCANHS_CORE 72 +#define CLK_SCANHS_ACLKM_CORE 73 +#define CLK_SCANHS_PCLK_DBG 74 +#define CLK_SCANHS_PCLK_CPU_BIU 76 +#define PCLK_CPU_ROOT 77 +#define PCLK_CORE_GRF 78 +#define PCLK_DAPLITE_BIU 79 +#define PCLK_CPU_BIU 80 +#define CLK_REF_PVTPLL_CORE 81 +#define ACLK_BUS_VOPGL_ROOT 85 +#define ACLK_BUS_VOPGL_BIU 86 +#define ACLK_BUS_H_ROOT 87 +#define ACLK_BUS_H_BIU 88 +#define ACLK_BUS_ROOT 89 +#define HCLK_BUS_ROOT 90 +#define PCLK_BUS_ROOT 91 +#define ACLK_BUS_M_ROOT 92 +#define ACLK_SYSMEM_BIU 93 +#define CLK_TIMER_ROOT 95 +#define ACLK_BUS_BIU 96 +#define HCLK_BUS_BIU 97 +#define PCLK_BUS_BIU 98 +#define PCLK_DFT2APB 99 +#define PCLK_BUS_GRF 100 +#define ACLK_BUS_M_BIU 101 +#define ACLK_GIC 102 +#define ACLK_SPINLOCK 103 +#define ACLK_DMAC 104 +#define PCLK_TIMER 105 +#define CLK_TIMER0 106 +#define CLK_TIMER1 107 +#define CLK_TIMER2 108 +#define CLK_TIMER3 109 +#define CLK_TIMER4 110 +#define CLK_TIMER5 111 +#define PCLK_JDBCK_DAP 112 +#define CLK_JDBCK_DAP 113 +#define PCLK_WDT_NS 114 +#define TCLK_WDT_NS 115 +#define HCLK_TRNG_NS 116 +#define PCLK_UART0 117 +#define PCLK_DMA2DDR 123 +#define ACLK_DMA2DDR 124 +#define PCLK_PWM0 126 +#define CLK_PWM0 127 +#define CLK_CAPTURE_PWM0 128 +#define PCLK_PWM1 129 +#define CLK_PWM1 130 +#define CLK_CAPTURE_PWM1 131 +#define PCLK_SCR 134 +#define ACLK_DCF 135 +#define PCLK_INTMUX 138 +#define CLK_PPLL_I 141 +#define CLK_PPLL_MUX 142 +#define CLK_PPLL_100M_MATRIX 143 +#define CLK_PPLL_50M_MATRIX 144 +#define CLK_REF_PCIE_INNER_PHY 145 +#define CLK_REF_PCIE_100M_PHY 146 +#define ACLK_VPU_L_ROOT 147 +#define CLK_GMAC1_VPU_25M 148 +#define CLK_PPLL_125M_MATRIX 149 +#define ACLK_VPU_ROOT 150 +#define HCLK_VPU_ROOT 151 +#define PCLK_VPU_ROOT 152 +#define ACLK_VPU_BIU 153 +#define HCLK_VPU_BIU 154 +#define PCLK_VPU_BIU 155 +#define ACLK_VPU 156 +#define HCLK_VPU 157 +#define PCLK_CRU_PCIE 158 +#define PCLK_VPU_GRF 159 +#define HCLK_SFC 160 +#define SCLK_SFC 161 +#define CCLK_SRC_EMMC 163 +#define HCLK_EMMC 164 +#define ACLK_EMMC 165 +#define BCLK_EMMC 166 +#define TCLK_EMMC 167 +#define PCLK_GPIO1 168 +#define DBCLK_GPIO1 169 +#define ACLK_VPU_L_BIU 172 +#define PCLK_VPU_IOC 173 +#define HCLK_SAI_I2S0 174 +#define MCLK_SAI_I2S0 175 +#define HCLK_SAI_I2S2 176 +#define MCLK_SAI_I2S2 177 +#define PCLK_ACODEC 178 +#define MCLK_ACODEC_TX 179 +#define PCLK_GPIO3 186 +#define DBCLK_GPIO3 187 +#define PCLK_SPI1 189 +#define CLK_SPI1 190 +#define SCLK_IN_SPI1 191 +#define PCLK_UART2 192 +#define PCLK_UART5 194 +#define PCLK_UART6 196 +#define PCLK_UART7 198 +#define PCLK_I2C3 200 +#define CLK_I2C3 201 +#define PCLK_I2C5 202 +#define CLK_I2C5 203 +#define PCLK_I2C6 204 +#define CLK_I2C6 205 +#define ACLK_MAC_VPU 206 +#define PCLK_MAC_VPU 207 +#define CLK_GMAC1_RMII_VPU 209 +#define CLK_GMAC1_SRC_VPU 210 +#define PCLK_PCIE 215 +#define CLK_PCIE_AUX 216 +#define ACLK_PCIE 217 +#define HCLK_PCIE_SLV 218 +#define HCLK_PCIE_DBI 219 +#define PCLK_PCIE_PHY 220 +#define PCLK_PIPE_GRF 221 +#define CLK_PIPE_USB3OTG_COMBO 230 +#define CLK_UTMI_USB3OTG 232 +#define CLK_PCIE_PIPE_PHY 235 +#define CCLK_SRC_SDIO0 240 +#define HCLK_SDIO0 241 +#define CCLK_SRC_SDIO1 244 +#define HCLK_SDIO1 245 +#define CLK_TS_0 246 +#define CLK_TS_1 247 +#define PCLK_CAN2 250 +#define CLK_CAN2 251 +#define PCLK_CAN3 252 +#define CLK_CAN3 253 +#define PCLK_SARADC 256 +#define CLK_SARADC 257 +#define PCLK_TSADC 258 +#define CLK_TSADC 259 +#define CLK_TSADC_TSEN 260 +#define ACLK_USB3OTG 261 +#define CLK_REF_USB3OTG 262 +#define CLK_SUSPEND_USB3OTG 263 +#define ACLK_GPU_ROOT 269 +#define PCLK_GPU_ROOT 270 +#define ACLK_GPU_BIU 271 +#define PCLK_GPU_BIU 272 +#define ACLK_GPU 273 +#define CLK_GPU_PVTPLL_SRC 274 +#define ACLK_GPU_MALI 275 +#define HCLK_RKVENC_ROOT 281 +#define ACLK_RKVENC_ROOT 282 +#define PCLK_RKVENC_ROOT 283 +#define HCLK_RKVENC_BIU 284 +#define ACLK_RKVENC_BIU 285 +#define PCLK_RKVENC_BIU 286 +#define HCLK_RKVENC 287 +#define ACLK_RKVENC 288 +#define CLK_CORE_RKVENC 289 +#define HCLK_SAI_I2S1 290 +#define MCLK_SAI_I2S1 291 +#define PCLK_I2C1 292 +#define CLK_I2C1 293 +#define PCLK_I2C0 294 +#define CLK_I2C0 295 +#define CLK_UART_JTAG 296 +#define PCLK_SPI0 297 +#define CLK_SPI0 298 +#define SCLK_IN_SPI0 299 +#define PCLK_GPIO4 300 +#define DBCLK_GPIO4 301 +#define PCLK_RKVENC_IOC 302 +#define HCLK_SPDIF 308 +#define MCLK_SPDIF 309 +#define HCLK_PDM 310 +#define MCLK_PDM 311 +#define PCLK_UART1 315 +#define PCLK_UART3 317 +#define PCLK_RKVENC_GRF 319 +#define PCLK_CAN0 320 +#define CLK_CAN0 321 +#define PCLK_CAN1 322 +#define CLK_CAN1 323 +#define ACLK_VO_ROOT 324 +#define HCLK_VO_ROOT 325 +#define PCLK_VO_ROOT 326 +#define ACLK_VO_BIU 327 +#define HCLK_VO_BIU 328 +#define PCLK_VO_BIU 329 +#define HCLK_RGA2E 330 +#define ACLK_RGA2E 331 +#define CLK_CORE_RGA2E 332 +#define HCLK_VDPP 333 +#define ACLK_VDPP 334 +#define CLK_CORE_VDPP 335 +#define PCLK_VO_GRF 336 +#define PCLK_CRU 337 +#define ACLK_VOP_ROOT 338 +#define ACLK_VOP_BIU 339 +#define HCLK_VOP 340 +#define DCLK_VOP0 341 +#define DCLK_VOP1 342 +#define ACLK_VOP 343 +#define PCLK_HDMI 344 +#define CLK_SFR_HDMI 345 +#define CLK_CEC_HDMI 346 +#define CLK_SPDIF_HDMI 347 +#define CLK_HDMIPHY_TMDSSRC 348 +#define CLK_HDMIPHY_PREP 349 +#define PCLK_HDMIPHY 352 +#define HCLK_HDCP_KEY 354 +#define ACLK_HDCP 355 +#define HCLK_HDCP 356 +#define PCLK_HDCP 357 +#define HCLK_CVBS 358 +#define DCLK_CVBS 359 +#define DCLK_4X_CVBS 360 +#define ACLK_JPEG_DECODER 361 +#define HCLK_JPEG_DECODER 362 +#define ACLK_VO_L_ROOT 375 +#define ACLK_VO_L_BIU 376 +#define ACLK_MAC_VO 377 +#define PCLK_MAC_VO 378 +#define CLK_GMAC0_SRC 379 +#define CLK_GMAC0_RMII_50M 380 +#define CLK_GMAC0_TX 381 +#define CLK_GMAC0_RX 382 +#define ACLK_JPEG_ROOT 385 +#define ACLK_JPEG_BIU 386 +#define HCLK_SAI_I2S3 387 +#define MCLK_SAI_I2S3 388 +#define CLK_MACPHY 398 +#define PCLK_VCDCPHY 399 +#define PCLK_GPIO2 404 +#define DBCLK_GPIO2 405 +#define PCLK_VO_IOC 406 +#define CCLK_SRC_SDMMC0 407 +#define HCLK_SDMMC0 408 +#define PCLK_OTPC_NS 411 +#define CLK_SBPI_OTPC_NS 412 +#define CLK_USER_OTPC_NS 413 +#define CLK_HDMIHDP0 415 +#define HCLK_USBHOST 416 +#define HCLK_USBHOST_ARB 417 +#define CLK_USBHOST_OHCI 418 +#define CLK_USBHOST_UTMI 419 +#define PCLK_UART4 420 +#define PCLK_I2C4 422 +#define CLK_I2C4 423 +#define PCLK_I2C7 424 +#define CLK_I2C7 425 +#define PCLK_USBPHY 426 +#define CLK_REF_USBPHY 427 +#define HCLK_RKVDEC_ROOT 433 +#define ACLK_RKVDEC_ROOT_NDFT 434 +#define PCLK_DDRPHY_CRU 435 +#define HCLK_RKVDEC_BIU 436 +#define ACLK_RKVDEC_BIU 437 +#define ACLK_RKVDEC 439 +#define HCLK_RKVDEC 440 +#define CLK_HEVC_CA_RKVDEC 441 +#define ACLK_RKVDEC_PVTMUX_ROOT 442 +#define CLK_RKVDEC_PVTPLL_SRC 443 +#define PCLK_DDR_ROOT 449 +#define PCLK_DDR_BIU 450 +#define PCLK_DDRC 451 +#define PCLK_DDRMON 452 +#define CLK_TIMER_DDRMON 453 +#define PCLK_MSCH_BIU 454 +#define PCLK_DDR_GRF 455 +#define PCLK_DDR_HWLP 456 +#define PCLK_DDRPHY 457 +#define CLK_MSCH_BIU 463 +#define ACLK_DDR_UPCTL 464 +#define CLK_DDR_UPCTL 465 +#define CLK_DDRMON 466 +#define ACLK_DDR_SCRAMBLE 467 +#define ACLK_SPLIT 468 +#define CLK_DDRC_SRC 470 +#define CLK_DDR_PHY 471 +#define PCLK_OTPC_S 472 +#define CLK_SBPI_OTPC_S 473 +#define CLK_USER_OTPC_S 474 +#define PCLK_KEYREADER 475 +#define PCLK_BUS_SGRF 476 +#define PCLK_STIMER 477 +#define CLK_STIMER0 478 +#define CLK_STIMER1 479 +#define PCLK_WDT_S 480 +#define TCLK_WDT_S 481 +#define HCLK_TRNG_S 482 +#define HCLK_BOOTROM 486 +#define PCLK_DCF 487 +#define ACLK_SYSMEM 488 +#define HCLK_TSP 489 +#define ACLK_TSP 490 +#define CLK_CORE_TSP 491 +#define CLK_OTPC_ARB 492 +#define PCLK_OTP_MASK 493 +#define CLK_PMC_OTP 494 +#define PCLK_PMU_ROOT 495 +#define HCLK_PMU_ROOT 496 +#define PCLK_I2C2 497 +#define CLK_I2C2 498 +#define HCLK_PMU_BIU 500 +#define PCLK_PMU_BIU 501 +#define FCLK_MCU 502 +#define RTC_CLK_MCU 504 +#define PCLK_OSCCHK 505 +#define CLK_PMU_MCU_JTAG 506 +#define PCLK_PMU 508 +#define PCLK_GPIO0 509 +#define DBCLK_GPIO0 510 +#define XIN_OSC0_DIV 511 +#define CLK_DEEPSLOW 512 +#define CLK_DDR_FAIL_SAFE 513 +#define PCLK_PMU_HP_TIMER 514 +#define CLK_PMU_HP_TIMER 515 +#define CLK_PMU_32K_HP_TIMER 516 +#define PCLK_PMU_IOC 517 +#define PCLK_PMU_CRU 518 +#define PCLK_PMU_GRF 519 +#define PCLK_PMU_WDT 520 +#define TCLK_PMU_WDT 521 +#define PCLK_PMU_MAILBOX 522 +#define PCLK_SCRKEYGEN 524 +#define CLK_SCRKEYGEN 525 +#define CLK_PVTM_OSCCHK 526 +#define CLK_REFOUT 530 +#define CLK_PVTM_PMU 532 +#define PCLK_PVTM_PMU 533 +#define PCLK_PMU_SGRF 534 +#define HCLK_PMU_SRAM 535 +#define CLK_UART0 536 +#define CLK_UART1 537 +#define CLK_UART2 538 +#define CLK_UART3 539 +#define CLK_UART4 540 +#define CLK_UART5 541 +#define CLK_UART6 542 +#define CLK_UART7 543 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 544 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 545 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 546 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 547 +#define MCLK_SDPDIF_SRC_PRE 548 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H --=20 2.46.0 From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org 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layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id TGsxb-HfGSLC; Tue, 1 Oct 2024 06:25:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756741; bh=qINmKLYPVDbFQb7u+E4PtU9YtutM9VRX2dikTr6h06I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=YJskmHWTCpm9UzqOx11Uhw+08ZHtmlPthbGoGVmFhvh2lbEpHBnuPsH8ZcgwKpMAs /fkOn/WCqdAC5PEVjszVqfc2GoZNk8EOvilh5q+r+ti3+b7HgJ0z1TxYKVXEDxpmb1 S3jWapPWsLm8olGTyub+Syh9aVpj3fZSQdghXfp/cExAl78QIDjErFWwMiOHn4av18 L01wooxivajWvhSB/Dlh7+NEmTZHTxr0SIwfDMW+T2vGJRAIMHtQEmrQKErblMiqYY r61HoI+MK/xF6dQWT+COLg/RKMXgmuJxm7A2wuqJ/pZ16VwqCCT/yx1/0X8/AO3Qj8 8ng9iD5XVPrng== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 2/8] dt-bindings: reset: Add reset ID definition for Rockchip RK3528 Date: Tue, 1 Oct 2024 04:23:56 +0000 Message-ID: <20241001042401.31903-4-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similar to previous Rockchip generations, reset IDs for RK3528 SoC are register offsets. Signed-off-by: Yao Zi --- .../dt-bindings/reset/rockchip,rk3528-cru.h | 292 ++++++++++++++++++ 1 file changed, 292 insertions(+) create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-b= indings/reset/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..1f8c0d38bb88 --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi + * Author: Joseph Chen + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H + +// CRU_SOFTRST_CON03 (Offset: 0xA0C) +#define SRST_CORE0_PO 0x00000030 +#define SRST_CORE1_PO 0x00000031 +#define SRST_CORE2_PO 0x00000032 +#define SRST_CORE3_PO 0x00000033 +#define SRST_CORE0 0x00000034 +#define SRST_CORE1 0x00000035 +#define SRST_CORE2 0x00000036 +#define SRST_CORE3 0x00000037 +#define SRST_NL2 0x00000038 +#define SRST_CORE_BIU 0x00000039 +#define SRST_CORE_CRYPTO 0x0000003A + +// CRU_SOFTRST_CON05 (Offset: 0xA14) +#define SRST_P_DBG 0x0000005D +#define SRST_POT_DBG 0x0000005E +#define SRST_NT_DBG 0x0000005F + +// CRU_SOFTRST_CON06 (Offset: 0xA18) +#define SRST_P_CORE_GRF 0x00000062 +#define SRST_P_DAPLITE_BIU 0x00000063 +#define SRST_P_CPU_BIU 0x00000064 +#define SRST_REF_PVTPLL_CORE 0x00000067 + +// CRU_SOFTRST_CON08 (Offset: 0xA20) +#define SRST_A_BUS_VOPGL_BIU 0x00000081 +#define SRST_A_BUS_H_BIU 0x00000083 +#define SRST_A_SYSMEM_BIU 0x00000088 +#define SRST_A_BUS_BIU 0x0000008A +#define SRST_H_BUS_BIU 0x0000008B +#define SRST_P_BUS_BIU 0x0000008C +#define SRST_P_DFT2APB 0x0000008D +#define SRST_P_BUS_GRF 0x0000008F + +// CRU_SOFTRST_CON09 (Offset: 0xA24) +#define SRST_A_BUS_M_BIU 0x00000090 +#define SRST_A_GIC 0x00000091 +#define SRST_A_SPINLOCK 0x00000092 +#define SRST_A_DMAC 0x00000094 +#define SRST_P_TIMER 0x00000095 +#define SRST_TIMER0 0x00000096 +#define SRST_TIMER1 0x00000097 +#define SRST_TIMER2 0x00000098 +#define SRST_TIMER3 0x00000099 +#define SRST_TIMER4 0x0000009A +#define SRST_TIMER5 0x0000009B +#define SRST_P_JDBCK_DAP 0x0000009C +#define SRST_JDBCK_DAP 0x0000009D +#define SRST_P_WDT_NS 0x0000009F + +// CRU_SOFTRST_CON10 (Offset: 0xA28) +#define SRST_T_WDT_NS 0x000000A0 +#define SRST_H_TRNG_NS 0x000000A3 +#define SRST_P_UART0 0x000000A7 +#define SRST_S_UART0 0x000000A8 +#define SRST_PKA_CRYPTO 0x000000AA +#define SRST_A_CRYPTO 0x000000AB +#define SRST_H_CRYPTO 0x000000AC +#define SRST_P_DMA2DDR 0x000000AD +#define SRST_A_DMA2DDR 0x000000AE + +// CRU_SOFTRST_CON11 (Offset: 0xA2C) +#define SRST_P_PWM0 0x000000B4 +#define SRST_PWM0 0x000000B5 +#define SRST_P_PWM1 0x000000B7 +#define SRST_PWM1 0x000000B8 +#define SRST_P_SCR 0x000000BA +#define SRST_A_DCF 0x000000BB +#define SRST_P_INTMUX 0x000000BC + +// CRU_SOFTRST_CON25 (Offset: 0xA64) +#define SRST_A_VPU_BIU 0x00000196 +#define SRST_H_VPU_BIU 0x00000197 +#define SRST_P_VPU_BIU 0x00000198 +#define SRST_A_VPU 0x00000199 +#define SRST_H_VPU 0x0000019A +#define SRST_P_CRU_PCIE 0x0000019B +#define SRST_P_VPU_GRF 0x0000019C +#define SRST_H_SFC 0x0000019D +#define SRST_S_SFC 0x0000019E +#define SRST_C_EMMC 0x0000019F + +// CRU_SOFTRST_CON26 (Offset: 0xA68) +#define SRST_H_EMMC 0x000001A0 +#define SRST_A_EMMC 0x000001A1 +#define SRST_B_EMMC 0x000001A2 +#define SRST_T_EMMC 0x000001A3 +#define SRST_P_GPIO1 0x000001A4 +#define SRST_DB_GPIO1 0x000001A5 +#define SRST_A_VPU_L_BIU 0x000001A6 +#define SRST_P_VPU_IOC 0x000001A8 +#define SRST_H_SAI_I2S0 0x000001A9 +#define SRST_M_SAI_I2S0 0x000001AA +#define SRST_H_SAI_I2S2 0x000001AB +#define SRST_M_SAI_I2S2 0x000001AC +#define SRST_P_ACODEC 0x000001AD + +// CRU_SOFTRST_CON27 (Offset: 0xA6C) +#define SRST_P_GPIO3 0x000001B0 +#define SRST_DB_GPIO3 0x000001B1 +#define SRST_P_SPI1 0x000001B4 +#define SRST_SPI1 0x000001B5 +#define SRST_P_UART2 0x000001B7 +#define SRST_S_UART2 0x000001B8 +#define SRST_P_UART5 0x000001B9 +#define SRST_S_UART5 0x000001BA +#define SRST_P_UART6 0x000001BB +#define SRST_S_UART6 0x000001BC +#define SRST_P_UART7 0x000001BD +#define SRST_S_UART7 0x000001BE +#define SRST_P_I2C3 0x000001BF + +// CRU_SOFTRST_CON28 (Offset: 0xA70) +#define SRST_I2C3 0x000001C0 +#define SRST_P_I2C5 0x000001C1 +#define SRST_I2C5 0x000001C2 +#define SRST_P_I2C6 0x000001C3 +#define SRST_I2C6 0x000001C4 +#define SRST_A_MAC 0x000001C5 + +// CRU_SOFTRST_CON30 (Offset: 0xA78) +#define SRST_P_PCIE 0x000001E1 +#define SRST_PCIE_PIPE_PHY 0x000001E2 +#define SRST_PCIE_POWER_UP 0x000001E3 +#define SRST_P_PCIE_PHY 0x000001E6 +#define SRST_P_PIPE_GRF 0x000001E7 + +// CRU_SOFTRST_CON32 (Offset: 0xA80) +#define SRST_H_SDIO0 0x00000202 +#define SRST_H_SDIO1 0x00000204 +#define SRST_TS_0 0x00000205 +#define SRST_TS_1 0x00000206 +#define SRST_P_CAN2 0x00000207 +#define SRST_CAN2 0x00000208 +#define SRST_P_CAN3 0x00000209 +#define SRST_CAN3 0x0000020A +#define SRST_P_SARADC 0x0000020B +#define SRST_SARADC 0x0000020C +#define SRST_SARADC_PHY 0x0000020D +#define SRST_P_TSADC 0x0000020E +#define SRST_TSADC 0x0000020F + +// CRU_SOFTRST_CON33 (Offset: 0xA84) +#define SRST_A_USB3OTG 0x00000211 + +// CRU_SOFTRST_CON34 (Offset: 0xA88) +#define SRST_A_GPU_BIU 0x00000223 +#define SRST_P_GPU_BIU 0x00000225 +#define SRST_A_GPU 0x00000228 +#define SRST_REF_PVTPLL_GPU 0x00000229 + +// CRU_SOFTRST_CON36 (Offset: 0xA90) +#define SRST_H_RKVENC_BIU 0x00000243 +#define SRST_A_RKVENC_BIU 0x00000244 +#define SRST_P_RKVENC_BIU 0x00000245 +#define SRST_H_RKVENC 0x00000246 +#define SRST_A_RKVENC 0x00000247 +#define SRST_CORE_RKVENC 0x00000248 +#define SRST_H_SAI_I2S1 0x00000249 +#define SRST_M_SAI_I2S1 0x0000024A +#define SRST_P_I2C1 0x0000024B +#define SRST_I2C1 0x0000024C +#define SRST_P_I2C0 0x0000024D +#define SRST_I2C0 0x0000024E + +// CRU_SOFTRST_CON37 (Offset: 0xA94) +#define SRST_P_SPI0 0x00000252 +#define SRST_SPI0 0x00000253 +#define SRST_P_GPIO4 0x00000258 +#define SRST_DB_GPIO4 0x00000259 +#define SRST_P_RKVENC_IOC 0x0000025A +#define SRST_H_SPDIF 0x0000025E +#define SRST_M_SPDIF 0x0000025F + +// CRU_SOFTRST_CON38 (Offset: 0xA98) +#define SRST_H_PDM 0x00000260 +#define SRST_M_PDM 0x00000261 +#define SRST_P_UART1 0x00000262 +#define SRST_S_UART1 0x00000263 +#define SRST_P_UART3 0x00000264 +#define SRST_S_UART3 0x00000265 +#define SRST_P_RKVENC_GRF 0x00000266 +#define SRST_P_CAN0 0x00000267 +#define SRST_CAN0 0x00000268 +#define SRST_P_CAN1 0x00000269 +#define SRST_CAN1 0x0000026A + +// CRU_SOFTRST_CON39 (Offset: 0xA9C) +#define SRST_A_VO_BIU 0x00000273 +#define SRST_H_VO_BIU 0x00000274 +#define SRST_P_VO_BIU 0x00000275 +#define SRST_H_RGA2E 0x00000277 +#define SRST_A_RGA2E 0x00000278 +#define SRST_CORE_RGA2E 0x00000279 +#define SRST_H_VDPP 0x0000027A +#define SRST_A_VDPP 0x0000027B +#define SRST_CORE_VDPP 0x0000027C +#define SRST_P_VO_GRF 0x0000027D +#define SRST_P_CRU 0x0000027F + +// CRU_SOFTRST_CON40 (Offset: 0xAA0) +#define SRST_A_VOP_BIU 0x00000281 +#define SRST_H_VOP 0x00000282 +#define SRST_D_VOP0 0x00000283 +#define SRST_D_VOP1 0x00000284 +#define SRST_A_VOP 0x00000285 +#define SRST_P_HDMI 0x00000286 +#define SRST_HDMI 0x00000287 +#define SRST_P_HDMIPHY 0x0000028E +#define SRST_H_HDCP_KEY 0x0000028F + +// CRU_SOFTRST_CON41 (Offset: 0xAA4) +#define SRST_A_HDCP 0x00000290 +#define SRST_H_HDCP 0x00000291 +#define SRST_P_HDCP 0x00000292 +#define SRST_H_CVBS 0x00000293 +#define SRST_D_CVBS_VOP 0x00000294 +#define SRST_D_4X_CVBS_VOP 0x00000295 +#define SRST_A_JPEG_DECODER 0x00000296 +#define SRST_H_JPEG_DECODER 0x00000297 +#define SRST_A_VO_L_BIU 0x00000299 +#define SRST_A_MAC_VO 0x0000029A + +// CRU_SOFTRST_CON42 (Offset: 0xAA8) +#define SRST_A_JPEG_BIU 0x000002A0 +#define SRST_H_SAI_I2S3 0x000002A1 +#define SRST_M_SAI_I2S3 0x000002A2 +#define SRST_MACPHY 0x000002A3 +#define SRST_P_VCDCPHY 0x000002A4 +#define SRST_P_GPIO2 0x000002A5 +#define SRST_DB_GPIO2 0x000002A6 +#define SRST_P_VO_IOC 0x000002A7 +#define SRST_H_SDMMC0 0x000002A9 +#define SRST_P_OTPC_NS 0x000002AB +#define SRST_SBPI_OTPC_NS 0x000002AC +#define SRST_USER_OTPC_NS 0x000002AD + +// CRU_SOFTRST_CON43 (Offset: 0xAAC) +#define SRST_HDMIHDP0 0x000002B2 +#define SRST_H_USBHOST 0x000002B3 +#define SRST_H_USBHOST_ARB 0x000002B4 +#define SRST_HOST_UTMI 0x000002B6 +#define SRST_P_UART4 0x000002B7 +#define SRST_S_UART4 0x000002B8 +#define SRST_P_I2C4 0x000002B9 +#define SRST_I2C4 0x000002BA +#define SRST_P_I2C7 0x000002BB +#define SRST_I2C7 0x000002BC +#define SRST_P_USBPHY 0x000002BD +#define SRST_USBPHY_POR 0x000002BE +#define SRST_USBPHY_OTG 0x000002BF + +// CRU_SOFTRST_CON44 (Offset: 0xAB0) +#define SRST_USBPHY_HOST 0x000002C0 +#define SRST_P_DDRPHY_CRU 0x000002C4 +#define SRST_H_RKVDEC_BIU 0x000002C6 +#define SRST_A_RKVDEC_BIU 0x000002C7 +#define SRST_A_RKVDEC 0x000002C8 +#define SRST_H_RKVDEC 0x000002C9 +#define SRST_HEVC_CA_RKVDEC 0x000002CB +#define SRST_REF_PVTPLL_RKVDEC 0x000002CC + +// CRU_SOFTRST_CON45 (Offset: 0xAB4) +#define SRST_P_DDR_BIU 0x000002D1 +#define SRST_P_DDRC 0x000002D2 +#define SRST_P_DDRMON 0x000002D3 +#define SRST_TIMER_DDRMON 0x000002D4 +#define SRST_P_MSCH_BIU 0x000002D5 +#define SRST_P_DDR_GRF 0x000002D6 +#define SRST_P_DDR_HWLP 0x000002D8 +#define SRST_P_DDRPHY 0x000002D9 +#define SRST_MSCH_BIU 0x000002DA +#define SRST_A_DDR_UPCTL 0x000002DB +#define SRST_DDR_UPCTL 0x000002DC +#define SRST_DDRMON 0x000002DD +#define SRST_A_DDR_SCRAMBLE 0x000002DE +#define SRST_A_SPLIT 0x000002DF + +// CRU_SOFTRST_CON46 (Offset: 0xAB8) +#define SRST_DDR_PHY 0x000002E0 + +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H --=20 2.46.0 From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 474731B5839; Tue, 1 Oct 2024 04:25:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756749; cv=none; b=BMZXfpnIlQ6UfkW5EtspMAGsMGneOIatEy6KMPAJp8l+p/f8fz6mMUsfb1g5qIO1y/uiSKNizuBhoX6VvQqx67rgheU3DI7a4Z3aoWBsWOLDecBK3L1F+TbREg8hividJSJbFIf39YdoKEhkyvaH+ytmEQLFkP22IW2h3LpOnPs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756749; c=relaxed/simple; bh=5MrQbBokfZMOsLxeFgXKXqngGLTWAVulicUDVAiD3dc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 1GZLnuBHkKf2; Tue, 1 Oct 2024 06:25:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756745; bh=5MrQbBokfZMOsLxeFgXKXqngGLTWAVulicUDVAiD3dc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ZLb3Hg5JpYgyHICNo8PHo4FdgSJ1G15e47gYb5CK8D2WLjhQ5T/fw6PIa1TmdV9SM 8eq+uFmPbLAqquCYQoXg+fLbNlKvgQcuUcW2DTiDRvvsDDKJy0Gj/Ei9O/G7r8eikk QcV0pCNdKtAN8Qfc7yJf6LPleddthpbxyOotK/QQx3yFtKKSpygBMYGK3+LrZXnfXY ItcZlTAkQ04tyU1JYY+2F4u7fJS6wCzJwpfHdmUr5rzpxbGZY58g8pExdOR1yQoLk6 VOOKD62hErQXD6SEwCznQCFi1hnBMIaSV5gnNjF0pTa5LoCdOazF1MmfU+sxZAt3v7 xcB56LadeQYQQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 3/8] dt-bindings: clock: Add rockchip,rk3528-cru Date: Tue, 1 Oct 2024 04:23:57 +0000 Message-ID: <20241001042401.31903-5-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Rockchip RK3528 clock and reset unit. Signed-off-by: Yao Zi --- .../bindings/clock/rockchip,rk3528-cru.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3528= -cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.ya= ml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 000000000000..ae51dfde5bb9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi + +description: | + The RK3528 clock controller generates the clock and also implements a re= set + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to speci= fy + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + enum: + - rockchip,rk3528-cru + + reg: + maxItems: 1 + + assigned-clocks: true + + assigned-clock-rates: true + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: phy_50m_out + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff4a0000 { + compatible =3D "rockchip,rk3528-cru"; + reg =3D <0xff4a0000 0x30000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.46.0 From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 783421B5EC5; Tue, 1 Oct 2024 04:25:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756751; cv=none; b=LiggwVt9Djvap4dvQOXtk67fj2Yvj+tSaiVoegc2WdXKozGM0JCATqhv1hpsjh9Fil01qe6AC3sipNs6/b2HUqYokNCKzgTQ6492leEUCPI6okkRaDm+4in9/vkdORSoBG/3bsTKE8MAEx99xhwR2t5XqD242i4X4+DwhdGUoQA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756751; c=relaxed/simple; bh=g3/xsaggoBD8STCM4ioqMxyKkwu2ClnVteNZa156RfA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fOlVYpmeMcO6jKIdWqTL0mqBHkb6OKsK1tUjkXBtn9yKkIwWKp241RDkAwDpmexmq0mv/vOq2EYr/2+cZdiZcOWR2XIyecJ+fG7x6WcBbbeQ9Udq8rjLWXBHaN5PULIA1DAiRBOeAvXpnHK7XtYQ3hOYmVE+i+srnXikqsQUJG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=KTHaUHi1; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="KTHaUHi1" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 0867823CB2; Tue, 1 Oct 2024 06:25:49 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id EQi-h7-SyM0d; Tue, 1 Oct 2024 06:25:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756748; bh=g3/xsaggoBD8STCM4ioqMxyKkwu2ClnVteNZa156RfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KTHaUHi1CaAPViTnRp4BcBT/sKGPTXc54XXajNENC0cMFzf3fe7XB/TMz/nIZoKxZ 9bO5sZ2xuKZ1kWtbp4uh3dc2gRCYDnphjrfbS2pSvXeCdbMHfabSCq7QTNuKjMpstA SmC9SJc0iUh8JppZXanppafF9RaIyIIjucv1O0qoKMBXIrJWQGuQAxWNJI4TDvjWDt AmPgfbu4ki53n0Vyl8EEK9yHx1nuJtifBZCM5TnnVIUYxzlnOVMmDVcmtHmenP1Uyv zzZ6SY2jaZl1H1q171JJRHoexOR34HzXWjATQhMuWnFRhNAav6t1Pf7JE0m08zFCZw glskzc2BSudwQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 4/8] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE Date: Tue, 1 Oct 2024 04:23:58 +0000 Message-ID: <20241001042401.31903-6-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE, which should operate in normal mode only. Add corresponding definition and handle it in code. Signed-off-by: Yao Zi --- drivers/clk/rockchip/clk-pll.c | 10 ++++++---- drivers/clk/rockchip/clk.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 606ce5458f54..46be1c67301a 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rock= chip_clk_pll *pll, rockchip_rk3036_pll_get_params(pll, &cur); cur.rate =3D 0; =20 - cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); - if (cur_parent =3D=3D PLL_MODE_NORM) { - pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); - rate_change_remuxed =3D 1; + if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { + cur_parent =3D pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent =3D=3D PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed =3D 1; + } } =20 /* update pll values */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..1efc5c3a1e77 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -391,6 +391,7 @@ struct rockchip_pll_rate_table { * Flags: * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the * rate_table parameters and ajust them if necessary. + * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only */ struct rockchip_pll_clock { unsigned int id; @@ -408,6 +409,7 @@ struct rockchip_pll_clock { }; =20 #define ROCKCHIP_PLL_SYNC_RATE BIT(0) +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) =20 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \ --=20 2.46.0 From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E743E1B652D; Tue, 1 Oct 2024 04:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727756755; cv=none; b=W0ZyAq+4SxFvzugAtrsJja+psptAmkfBWK8olQQhMGVMSkOtUqZCm0EHHQqQigqJ9z9POuX1VYJTkQM0XBr9JL6W4bCqs0q2/3uPesOuYY0zH/gLQWbKrlFRJv9m3bbFLcnqI5q6VPgyhxHkV0LPySKVHLjJMAk67ACpCLvAXNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 1 Oct 2024 06:25:52 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 8us6GjPoTX2f; Tue, 1 Oct 2024 06:25:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727756751; bh=zX7e8iV9phckFaC5bqESpnimFOhE4jLq8O6rmpwV3M0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ipbCdSh1gEKqLJpQwYh+By6BVU2tbxf5TD4lgl1Cqv/xWBEzTkjfMu9KkvYuLC94N dB05M9uiHIl0PSnHTN8C7yDuTEt2fO2ENymo2Ndc/i70oxqlgSmlsg2eQ3FORjQaFC cOT1Q3+XHKJF7sJW/jbCE4GJm6H2FGGC8B7qVHozgSTyAvfoIzfePavE0yTFl8SyP9 g26Dt1mmbI+oqe0NfDD8/+gTbgJrBdjP9gL3aaCZpavgFd/TdhZ8kSuqH8IYuGEuw/ b+CIAVzqC5E6C1mJAMZ3V82arLd/o4IjJ5vC2wNVTmqzqYW602A7svSnXE68evrHBI P1nEFHV0kGJEQ== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 5/8] clk: rockchip: Add clock type GATE_NO_SET_RATE Date: Tue, 1 Oct 2024 04:23:59 +0000 Message-ID: <20241001042401.31903-7-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This clock type is similar to GATE, but doesn't allow rate setting, which presents on RK3528 platform. Signed-off-by: Yao Zi --- drivers/clk/rockchip/clk.c | 8 ++++++++ drivers/clk/rockchip/clk.h | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 73d2cbdc716b..7d233770e68b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -521,6 +521,14 @@ void rockchip_clk_register_branches(struct rockchip_cl= k_provider *ctx, case branch_gate: flags |=3D CLK_SET_RATE_PARENT; =20 + clk =3D clk_register_gate(NULL, list->name, + list->parent_names[0], flags, + ctx->reg_base + list->gate_offset, + list->gate_shift, list->gate_flags, &ctx->lock); + break; + case branch_gate_no_set_rate: + flags &=3D ~CLK_SET_RATE_PARENT; + clk =3D clk_register_gate(NULL, list->name, list->parent_names[0], flags, ctx->reg_base + list->gate_offset, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 1efc5c3a1e77..360d16402fe5 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -519,6 +519,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_gate_no_set_rate, branch_mmc, branch_inverter, branch_factor, @@ -844,6 +845,19 @@ struct rockchip_clk_branch { .gate_flags =3D gf, \ } =20 +#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf) \ + { \ + .id =3D _id, \ + .branch_type =3D branch_gate_no_set_rate, \ + .name =3D cname, \ + .parent_names =3D (const char *[]){ pname }, \ + .num_parents =3D 1, \ + .flags =3D f, \ + .gate_offset =3D o, \ + .gate_shift =3D b, \ + .gate_flags =3D gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id =3D _id, \ --=20 2.46.0 From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80BB21B5818; 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charset="utf-8" Add clock tree definition for RK3528. Similar to previous Rockchip SoCs, clock controller shares MMIO region with reset controller and they are probed together. Signed-off-by: Yao Zi --- drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3528.c | 1194 +++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 20 + 4 files changed, 1222 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rk3528.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 9aad86925cd2..9f1853b88ebb 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -93,6 +93,13 @@ config CLK_RK3399 help Build the driver for RK3399 Clock Driver. =20 +config CLK_RK3528 + bool "Rockchip RK3528 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3528 Clock Controller. + config CLK_RK3568 bool "Rockchip RK3568 clock controller support" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 36894f6a7022..1caf5a50806f 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -27,5 +27,6 @@ obj-$(CONFIG_CLK_RK3308) +=3D clk-rk3308.o obj-$(CONFIG_CLK_RK3328) +=3D clk-rk3328.o obj-$(CONFIG_CLK_RK3368) +=3D clk-rk3368.o obj-$(CONFIG_CLK_RK3399) +=3D clk-rk3399.o +obj-$(CONFIG_CLK_RK3528) +=3D clk-rk3528.o obj-$(CONFIG_CLK_RK3568) +=3D clk-rk3568.o obj-$(CONFIG_CLK_RK3588) +=3D clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-r= k3528.c new file mode 100644 index 000000000000..8c4b9cfa1f84 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3528.c @@ -0,0 +1,1194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi + * Author: Joseph Chen + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define RK3528_GRF_SOC_STATUS0 0x1a0 + +enum rk3528_plls { + apll, cpll, gpll, ppll, dpll, +}; + +static struct rockchip_pll_rate_table rk3528_pll_rates[] =3D { + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ + RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ + RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ + RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), + { /* sentinel */ }, +}; + +#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 +#define RK3528_DIV_PCLK_DBG_MASK 0x1f +#define RK3528_DIV_PCLK_DBG_SHIFT 1 + +#define RK3528_CLKSEL39(_aclk_m_core) \ +{ \ + .reg =3D RK3528_CLKSEL_CON(39), \ + .val =3D HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \ + RK3528_DIV_ACLK_M_CORE_SHIFT), \ +} + +#define RK3528_CLKSEL40(_pclk_dbg) \ +{ \ + .reg =3D RK3528_CLKSEL_CON(40), \ + .val =3D HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \ + RK3528_DIV_PCLK_DBG_SHIFT), \ +} + +#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \ +{ \ + .prate =3D _prate, \ + .divs =3D { \ + RK3528_CLKSEL39(_aclk_m_core), \ + RK3528_CLKSEL40(_pclk_dbg), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = =3D { + RK3528_CPUCLK_RATE(1896000000, 1, 13), + RK3528_CPUCLK_RATE(1800000000, 1, 12), + RK3528_CPUCLK_RATE(1704000000, 1, 11), + RK3528_CPUCLK_RATE(1608000000, 1, 11), + RK3528_CPUCLK_RATE(1512000000, 1, 11), + RK3528_CPUCLK_RATE(1416000000, 1, 9), + RK3528_CPUCLK_RATE(1296000000, 1, 8), + RK3528_CPUCLK_RATE(1200000000, 1, 8), + RK3528_CPUCLK_RATE(1188000000, 1, 8), + RK3528_CPUCLK_RATE(1092000000, 1, 7), + RK3528_CPUCLK_RATE(1008000000, 1, 6), + RK3528_CPUCLK_RATE(1000000000, 1, 6), + RK3528_CPUCLK_RATE(996000000, 1, 6), + RK3528_CPUCLK_RATE(960000000, 1, 6), + RK3528_CPUCLK_RATE(912000000, 1, 6), + RK3528_CPUCLK_RATE(816000000, 1, 5), + RK3528_CPUCLK_RATE(600000000, 1, 3), + RK3528_CPUCLK_RATE(594000000, 1, 3), + RK3528_CPUCLK_RATE(408000000, 1, 2), + RK3528_CPUCLK_RATE(312000000, 1, 2), + RK3528_CPUCLK_RATE(216000000, 1, 1), + RK3528_CPUCLK_RATE(96000000, 1, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data =3D { + .core_reg[0] =3D RK3528_CLKSEL_CON(39), + .div_core_shift[0] =3D 5, + .div_core_mask[0] =3D 0x1f, + .num_cores =3D 1, + .mux_core_alt =3D 1, + .mux_core_main =3D 0, + .mux_core_shift =3D 10, + .mux_core_mask =3D 0x1, +}; + +PNAME(mux_pll_p) =3D { "xin24m" }; +PNAME(mux_armclk) =3D { "apll", "gpll" }; +PNAME(mux_24m_32k_p) =3D { "xin24m", "clk_32k" }; +PNAME(mux_gpll_cpll_p) =3D { "gpll", "cpll" }; +PNAME(mux_gpll_cpll_xin24m_p) =3D { "gpll", "cpll", "xin24m" }; +PNAME(mux_100m_50m_24m_p) =3D { "clk_100m_src", "clk_50m_src= ", + "xin24m" }; +PNAME(mux_150m_100m_24m_p) =3D { "clk_150m_src", "clk_100m_sr= c", + "xin24m" }; +PNAME(mux_200m_100m_24m_p) =3D { "clk_200m_src", "clk_100m_sr= c", + "xin24m" }; +PNAME(mux_200m_100m_50m_24m_p) =3D { "clk_200m_src", "clk_100m_sr= c", + "clk_50m_src", "xin24m" }; +PNAME(mux_300m_200m_100m_24m_p) =3D { "clk_300m_src", "clk_200m_sr= c", + "clk_100m_src", "xin24m" }; +PNAME(mux_339m_200m_100m_24m_p) =3D { "clk_339m_src", "clk_200m_sr= c", + "clk_100m_src", "xin24m" }; +PNAME(mux_500m_200m_100m_24m_p) =3D { "clk_500m_src", "clk_200m_sr= c", + "clk_100m_src", "xin24m" }; +PNAME(mux_500m_300m_100m_24m_p) =3D { "clk_500m_src", "clk_300m_sr= c", + "clk_100m_src", "xin24m" }; +PNAME(mux_600m_300m_200m_24m_p) =3D { "clk_600m_src", "clk_300m_sr= c", + "clk_200m_src", "xin24m" }; +PNAME(aclk_gpu_p) =3D { "aclk_gpu_root", + "clk_gpu_pvtpll_src" }; +PNAME(aclk_rkvdec_pvtmux_root_p) =3D { "aclk_rkvdec_root", + "clk_rkvdec_pvtpll_src" }; +PNAME(clk_i2c2_p) =3D { "clk_200m_src", "clk_100m_sr= c", + "xin24m", "clk_32k" }; +PNAME(clk_ref_pcie_inner_phy_p) =3D { "clk_ppll_100m_src", "xin24m= " }; +PNAME(dclk_vop0_p) =3D { "dclk_vop_src0", + "clk_hdmiphy_pixel_io" }; +PNAME(mclk_i2s0_2ch_sai_src_p) =3D { "clk_i2s0_2ch_src", + "clk_i2s0_2ch_frac", "xin12m" }; +PNAME(mclk_i2s1_8ch_sai_src_p) =3D { "clk_i2s1_8ch_src", + "clk_i2s1_8ch_frac", "xin12m" }; +PNAME(mclk_i2s2_2ch_sai_src_p) =3D { "clk_i2s2_2ch_src", + "clk_i2s2_2ch_frac", "xin12m" }; +PNAME(mclk_i2s3_8ch_sai_src_p) =3D { "clk_i2s3_8ch_src", + "clk_i2s3_8ch_frac", "xin12m" }; +PNAME(mclk_sai_i2s0_p) =3D { "mclk_i2s0_2ch_sai_src", + "i2s0_mclkin" }; +PNAME(mclk_sai_i2s1_p) =3D { "mclk_i2s1_8ch_sai_src", + "i2s1_mclkin" }; +PNAME(mclk_spdif_src_p) =3D { "clk_spdif_src", "clk_spdif_= frac", + "xin12m" }; +PNAME(sclk_uart0_src_p) =3D { "clk_uart0_src", "clk_uart0_= frac", + "xin24m" }; +PNAME(sclk_uart1_src_p) =3D { "clk_uart1_src", "clk_uart1_= frac", + "xin24m" }; +PNAME(sclk_uart2_src_p) =3D { "clk_uart2_src", "clk_uart2_= frac", + "xin24m" }; +PNAME(sclk_uart3_src_p) =3D { "clk_uart3_src", "clk_uart3_= frac", + "xin24m" }; +PNAME(sclk_uart4_src_p) =3D { "clk_uart4_src", "clk_uart4_= frac", + "xin24m" }; +PNAME(sclk_uart5_src_p) =3D { "clk_uart5_src", "clk_uart5_= frac", + "xin24m" }; +PNAME(sclk_uart6_src_p) =3D { "clk_uart6_src", "clk_uart6_= frac", + "xin24m" }; +PNAME(sclk_uart7_src_p) =3D { "clk_uart7_src", "clk_uart7_= frac", + "xin24m" }; +PNAME(clk_32k_p) =3D { "xin_osc0_div", "clk_pvtm_32= k" }; + +static struct rockchip_pll_clock rk3528_pll_clks[] __initdata =3D { + [apll] =3D PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PLL_CON(0), + RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates), + + [cpll] =3D PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PLL_CON(8), + RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates), + + [gpll] =3D PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PLL_CON(24), + RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates), + + [ppll] =3D PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), + RK3528_MODE_CON, 6, 0, + ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), + + [dpll] =3D PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), + RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =3D + MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(6), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata =3D + MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(8), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata =3D + MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(10), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata =3D + MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(12), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata =3D + MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(14), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata =3D + MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(16), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata =3D + MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(18), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata =3D + MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(20), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata= =3D + MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", + mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(22), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata= =3D + MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", + mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(26), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata= =3D + MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", + mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(28), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata= =3D + MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", + mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(24), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata =3D + MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(32), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_clk_branches[] __initdata =3D { + /* top */ + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + + COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(0), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(0), 7, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 10, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(4), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS, + RK3528_CLKGATE_CON(3), 7, GFLAGS), + COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3528_CLKGATE_CON(3), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0, + RK3528_CLKSEL_CON(36), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(3), 13, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0, + RK3528_CLKSEL_CON(4), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(5), 0, + RK3528_CLKGATE_CON(0), 13, GFLAGS, + &rk3528_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, + RK3528_CLKGATE_CON(0), 14, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0, + RK3528_CLKSEL_CON(6), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(7), 0, + RK3528_CLKGATE_CON(1), 0, GFLAGS, + &rk3528_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3528_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0, + RK3528_CLKSEL_CON(8), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(9), 0, + RK3528_CLKGATE_CON(1), 3, GFLAGS, + &rk3528_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3528_CLKGATE_CON(1), 4, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0, + RK3528_CLKSEL_CON(10), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(11), 0, + RK3528_CLKGATE_CON(1), 6, GFLAGS, + &rk3528_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3528_CLKGATE_CON(1), 7, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0, + RK3528_CLKSEL_CON(12), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(13), 0, + RK3528_CLKGATE_CON(1), 9, GFLAGS, + &rk3528_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3528_CLKGATE_CON(1), 10, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0, + RK3528_CLKSEL_CON(14), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(15), 0, + RK3528_CLKGATE_CON(1), 12, GFLAGS, + &rk3528_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3528_CLKGATE_CON(1), 13, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0, + RK3528_CLKSEL_CON(16), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(17), 0, + RK3528_CLKGATE_CON(1), 15, GFLAGS, + &rk3528_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3528_CLKGATE_CON(2), 0, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0, + RK3528_CLKSEL_CON(18), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(19), 0, + RK3528_CLKGATE_CON(2), 2, GFLAGS, + &rk3528_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3528_CLKGATE_CON(2), 3, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0, + RK3528_CLKSEL_CON(20), 8, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", + "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(21), 0, + RK3528_CLKGATE_CON(2), 6, GFLAGS, + &mclk_i2s0_2ch_sai_src_fracmux), + GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", + "mclk_i2s0_2ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 7, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0, + RK3528_CLKSEL_CON(24), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", + "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(25), 0, + RK3528_CLKGATE_CON(2), 12, GFLAGS, + &mclk_i2s1_8ch_sai_src_fracmux), + GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", + "mclk_i2s1_8ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 13, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0, + RK3528_CLKSEL_CON(26), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", + "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(27), 0, + RK3528_CLKGATE_CON(2), 15, GFLAGS, + &mclk_i2s2_2ch_sai_src_fracmux), + GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", + "mclk_i2s2_2ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(3), 0, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0, + RK3528_CLKSEL_CON(22), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", + "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(23), 0, + RK3528_CLKGATE_CON(2), 9, GFLAGS, + &mclk_i2s3_8ch_sai_src_fracmux), + GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", + "mclk_i2s3_8ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 10, GFLAGS), + + COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0, + RK3528_CLKSEL_CON(30), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(3), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(31), 0, + RK3528_CLKGATE_CON(3), 5, GFLAGS, + &mclk_spdif_src_fracmux), + GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0, + RK3528_CLKGATE_CON(3), 6, GFLAGS), + + /* bus */ + COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", + mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 7, GFLAGS), + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(9), 1, GFLAGS), + + COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 4, GFLAGS), + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 2, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 4, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 11, GFLAGS), + COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS, + RK3528_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", + mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 2, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0, + RK3528_CLKGATE_CON(10), 14, GFLAGS), + + COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 5, GFLAGS), + + COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 6, GFLAGS), + GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(8), 13, GFLAGS), + GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(8), 15, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 5, GFLAGS), + GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 12, GFLAGS), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 15, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(10), 7, GFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 4, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 7, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(10), 13, GFLAGS), + GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 10, GFLAGS), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(11), 12, GFLAGS), + + COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(44), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(11), 5, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(44), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(11), 8, GFLAGS), + + GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0, + RK3528_CLKGATE_CON(11), 9, GFLAGS), + GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0, + RK3528_CLKGATE_CON(11), 6, GFLAGS), + GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0, + RK3528_CLKGATE_CON(9), 13, GFLAGS), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, + RK3528_CLKGATE_CON(10), 0, GFLAGS), + + GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0, + RK3528_CLKGATE_CON(8), 9, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 6, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 7, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 8, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 9, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 10, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 11, GFLAGS), + + /* pmu */ + GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS), + GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS), + + GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS), + + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS), + GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS), + + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0, + RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS, + RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS), + + GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, + RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, + RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS, + RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS), + + COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, + RK3528_PMU_CLKSEL_CON(1), 0, + RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS), + /* clk_32k: internal! No path from external osc 32k */ + MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL, + RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS), + GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0, + RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS, + RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0, + RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS, + RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS), + + /* core */ + COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(39), 11, 5, + DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3528_CLKGATE_CON(5), 12, GFLAGS), + COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(40), 1, 5, + DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3528_CLKGATE_CON(5), 13, GFLAGS), + GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(6), 1, GFLAGS), + GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(6), 2, GFLAGS), + + /* ddr */ + GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL, + RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS), + GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL, + RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS), + + COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(90), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(45), 0, GFLAGS), + GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 3, GFLAGS), + GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 8, GFLAGS), + GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 4, GFLAGS), + + GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 2, GFLAGS), + GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 6, GFLAGS), + GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 9, GFLAGS), + + GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 11, GFLAGS), + GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 12, GFLAGS), + GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 13, GFLAGS), + GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", + CLK_IS_CRITICAL, RK3528_CLKGATE_CON(45), 14, GFLAGS), + GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 15, GFLAGS), + + /* gpu */ + COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", + mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(76), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(34), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(76), 6, 1, MFLAGS, + RK3528_CLKGATE_CON(34), 7, GFLAGS), + GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0, + RK3528_CLKGATE_CON(34), 8, GFLAGS), + COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(76), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(34), 2, GFLAGS), + + /* rkvdec */ + COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", + mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(88), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 3, GFLAGS), + COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", + mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(88), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 2, GFLAGS), + GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", + CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(44), 4, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, + RK3528_CLKGATE_CON(44), 9, GFLAGS), + COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", + mux_600m_300m_200m_24m_p, 0, + RK3528_CLKSEL_CON(88), 11, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 11, GFLAGS), + MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", + aclk_rkvdec_pvtmux_root_p, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(88), 13, 1, MFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0, + RK3528_CLKGATE_CON(44), 8, GFLAGS), + + /* rkvenc */ + COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", + mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 1, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 7, GFLAGS), + + COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", + mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 2, GFLAGS), + GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", + CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(37), 10, GFLAGS), + GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", + CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(38), 6, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 11, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 13, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 2, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 8, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 2, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 4, GFLAGS), + GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 7, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 9, GFLAGS), + + COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0, + RK3528_CLKSEL_CON(80), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(38), 1, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(38), 8, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3528_CLKGATE_CON(38), 10, GFLAGS), + + COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", + mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 0, GFLAGS), + GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 9, GFLAGS), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 14, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 0, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 6, GFLAGS), + + COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", + mux_300m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(79), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 8, GFLAGS), + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 11, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 14, GFLAGS), + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 9, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 12, GFLAGS), + + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 13, 2, MFLAGS, + RK3528_CLKGATE_CON(37), 3, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(79), 8, 1, MFLAGS, + RK3528_CLKGATE_CON(36), 10, GFLAGS), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, + RK3528_CLKGATE_CON(37), 9, GFLAGS), + + /* vo */ + COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 1, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 2, GFLAGS), + GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 3, GFLAGS), + GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 7, GFLAGS), + GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 10, GFLAGS), + GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 3, GFLAGS), + GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 4, GFLAGS), + GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 1, GFLAGS), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 1, GFLAGS), + GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 7, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 9, GFLAGS), + GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 15, GFLAGS), + + COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(84), 1, 2, MFLAGS, + RK3528_CLKGATE_CON(41), 8, GFLAGS), + GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0, + RK3528_CLKGATE_CON(41), 10, GFLAGS), + + COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 2, GFLAGS), + GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 11, GFLAGS), + GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 4, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 5, GFLAGS), + GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(42), 7, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 11, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 7, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 9, GFLAGS), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 11, GFLAGS), + + GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 13, GFLAGS), + + GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(39), 13, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(39), 15, GFLAGS), + GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 6, GFLAGS), + GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 14, GFLAGS), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 2, GFLAGS), + + COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", + mux_339m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(83), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 12, GFLAGS), + COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", + mux_339m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(83), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 9, GFLAGS), + COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", + mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(84), 9, 2, MFLAGS, + RK3528_CLKGATE_CON(41), 15, GFLAGS), + GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0, + RK3528_CLKGATE_CON(41), 6, GFLAGS), + + COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 0, GFLAGS), + GATE_NO_SET_RATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 8, GFLAGS), + GATE_NO_SET_RATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 11, GFLAGS), + GATE_NO_SET_RATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 0, GFLAGS), + + COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(42), 8, GFLAGS), + + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS, + RK3528_CLKGATE_CON(40), 0, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, + RK3528_CLKGATE_CON(40), 5, GFLAGS), + + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(85), 13, 2, MFLAGS, + RK3528_CLKGATE_CON(43), 10, GFLAGS), + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(86), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(43), 12, GFLAGS), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, + RK3528_CLKGATE_CON(42), 6, GFLAGS), + + GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, + RK3528_CLKGATE_CON(43), 2, GFLAGS), + GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0, + RK3528_CLKGATE_CON(42), 3, GFLAGS), + GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0, + RK3528_CLKGATE_CON(43), 14, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RK3528_CLKGATE_CON(42), 12, GFLAGS), + FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", + 0, 1, 2), + + GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0, + RK3528_CLKGATE_CON(42), 2, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3528_CLKSEL_CON(84), 0, 1, MFLAGS, + RK3528_CLKGATE_CON(40), 3, GFLAGS), + GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT, + RK3528_CLKGATE_CON(40), 4, GFLAGS), + FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4, + RK3528_CLKGATE_CON(41), 4, GFLAGS), + GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0, + RK3528_CLKGATE_CON(41), 5, GFLAGS), + + FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4, + RK3528_CLKGATE_CON(40), 7, GFLAGS), + + GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0, + RK3528_CLKGATE_CON(40), 10, GFLAGS), + GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0, + RK3528_CLKGATE_CON(37), 15, GFLAGS), + GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0, + RK3528_CLKGATE_CON(40), 8, GFLAGS), + + /* vpu */ + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, + RK3528_CLKGATE_CON(26), 5, GFLAGS), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, + RK3528_CLKGATE_CON(27), 1, GFLAGS), + GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, + RK3528_CLKGATE_CON(33), 4, GFLAGS), + GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0, + RK3528_CLKGATE_CON(30), 2, GFLAGS), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, + RK3528_CLKGATE_CON(26), 3, GFLAGS), + GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, + RK3528_CLKGATE_CON(33), 2, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 1, GFLAGS), + + COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, + CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 5, GFLAGS), + GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(25), 12, GFLAGS), + GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(25), 11, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 11, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 7, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 4, GFLAGS), + GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 9, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 0, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 4, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 11, GFLAGS), + GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 13, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 13, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 9, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 14, GFLAGS), + GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 1, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 7, GFLAGS), + GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(26), 8, GFLAGS), + GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(30), 7, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(28), 1, GFLAGS), + GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 6, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 15, GFLAGS), + GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(28), 6, GFLAGS), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(28), 3, GFLAGS), + + COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", + mux_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(60), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 0, GFLAGS), + GATE_NO_SET_RATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(26), 1, GFLAGS), + GATE_NO_SET_RATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(28), 5, GFLAGS), + GATE_NO_SET_RATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(30), 3, GFLAGS), + + GATE_NO_SET_RATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(33), 1, GFLAGS), + + COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", + mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 4, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 10, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 13, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 0, GFLAGS), + GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 9, GFLAGS), + GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 11, GFLAGS), + + GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 4, GFLAGS), + GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 5, GFLAGS), + GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 2, GFLAGS), + GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 4, GFLAGS), + + COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0, + RK3528_CLKSEL_CON(60), 2, 8, DFLAGS, + RK3528_CLKGATE_CON(25), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0, + RK3528_CLKSEL_CON(60), 10, 5, DFLAGS, + RK3528_CLKGATE_CON(25), 2, GFLAGS), + + COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 10, GFLAGS), + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(64), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 4, GFLAGS), + + COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS, + RK3528_CLKGATE_CON(25), 14, GFLAGS), + COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(25), 15, GFLAGS), + + COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root", + mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 3, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 9, GFLAGS), + + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(27), 5, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 3, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3528_CLKSEL_CON(74), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(32), 15, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3528_CLKSEL_CON(74), 0, 3, DFLAGS, + RK3528_CLKGATE_CON(32), 12, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, + RK3528_CLKSEL_CON(74), 8, 5, DFLAGS, + RK3528_CLKGATE_CON(33), 0, GFLAGS), + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(62), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(26), 2, GFLAGS), + COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", + "mclk_i2s2_2ch_sai_src", 0, + RK3528_CLKSEL_CON(63), 0, 8, DFLAGS, + RK3528_CLKGATE_CON(26), 14, GFLAGS), + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 0, GFLAGS), + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 14, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 2, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, + CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(62), 10, 1, MFLAGS, + RK3528_CLKGATE_CON(26), 10, GFLAGS), + GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0, + RK3528_CLKGATE_CON(26), 12, GFLAGS), + + /* pcie */ + COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", + "ppll", CLK_IS_CRITICAL, + RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS, + RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", + "ppll", CLK_IS_CRITICAL, + RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS, + RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS), + MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", + clk_ref_pcie_inner_phy_p, 0, + RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS), + FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", + "clk_ppll_100m_src", + 0, 1, 1), + + /* gmac */ + DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "phy_50m_out", 0, + RK3528_CLKSEL_CON(84), 3, 6, DFLAGS), + GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0, + RK3528_CLKGATE_CON(41), 13, GFLAGS), + GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0, + RK3528_CLKGATE_CON(41), 14, GFLAGS), + GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "phy_50m_out", 0, + RK3528_CLKGATE_CON(41), 12, GFLAGS), + + FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src", + 0, 1, 1), + FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src", + 0, 1, 1), +}; + +static int __init clk_rk3528_probe(struct platform_device *pdev) +{ + struct rockchip_clk_provider *ctx; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + unsigned long nr_branches =3D ARRAY_SIZE(rk3528_clk_branches); + unsigned long nr_clks; + void __iomem *reg_base; + + nr_clks =3D rockchip_clk_find_max_clk_id(rk3528_clk_branches, + nr_branches) + 1; + + pr_warn("%s: nr_clks =3D %lu\n", __func__, nr_clks); + + reg_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return dev_err_probe(dev, PTR_ERR(reg_base), + "could not map cru region"); + + ctx =3D rockchip_clk_init(np, reg_base, nr_clks); + if (IS_ERR(ctx)) + return dev_err_probe(dev, PTR_ERR(ctx), + "rockchip clk init failed"); + + rockchip_clk_register_plls(ctx, rk3528_pll_clks, + ARRAY_SIZE(rk3528_pll_clks), + RK3528_GRF_SOC_STATUS0); + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", + mux_armclk, ARRAY_SIZE(mux_armclk), + &rk3528_cpuclk_data, rk3528_cpuclk_rates, + ARRAY_SIZE(rk3528_cpuclk_rates)); + rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); + + rockchip_register_softrst(np, 47, reg_base + RK3528_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); + rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); + + return 0; +} + +static const struct of_device_id clk_rk3528_match_table[] =3D { + { .compatible =3D "rockchip,rk3528-cru" }, + { /* end */ } +}; + +static struct platform_driver clk_rk3528_driver =3D { + .driver =3D { + .name =3D "clk-rk3528", + .of_match_table =3D clk_rk3528_match_table, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 360d16402fe5..1fc6f221088d 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -207,6 +207,26 @@ struct clk; #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) =20 +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BAS= E) +#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BA= SE) +#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CR= U_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_GLB_CNT_TH 0xc00 +#define RK3528_GLB_SRST_FST 0xc08 +#define RK3528_GLB_SRST_SND 0xc0c + #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) #define RK3568_MODE_CON0 0xc0 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layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id XM4t5ca97D9N; Tue, 1 Oct 2024 06:39:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1727757578; bh=qRlFYk4dROIAZ51SrQ+l7xbvXRsYyx2thqhkXohUYrI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hL9qMI7XWchMhs1+8uYVqMVSg699F4yDlTU6/3vuzX0dDJ19Hatnpd3yjIuyZnjBt 4YcH2Le5bk26lvbLqhWl0g85Np2rU1WxpGg9O103SJLn3i+MOowRVYkDMV5pLYmmSb gW7lGAYiUxaqBLt0yGludSzeFe0lpdyYCmOWaaJyeiutI3nS7/+cek+Q7LxqQvRFPO myiJxiZLZZomiWRz7WZP9IUxfV1YZ1Bg0uj3fhCdJYca6ZKkUtrIjq8MMR2nWH86vu k0XSj8xCaygNj+DiNnUTNu/5Ldar3YBDJPPpGeiMneBGr5VZjZvJfTEwCrWdQRCbhc 6SVq7M+0Y1ozg== From: Yao Zi To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Celeste Liu , Yao Zi Subject: [PATCH 7/8] arm64: dts: rockchip: Add clock generators for RK3528 SoC Date: Tue, 1 Oct 2024 04:38:37 +0000 Message-ID: <20241001043838.31963-1-ziyao@disroot.org> In-Reply-To: <20241001042401.31903-2-ziyao@disroot.org> References: <20241001042401.31903-2-ziyao@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt node for RK3528 clock and reset unit. Clock "phy_50m_out" is generated by internal Ethernet phy, a fixed clock node is added as a placeholder to avoid orphans. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index e58faa985aa4..c0552ff7cd31 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -6,6 +6,7 @@ =20 #include #include +#include =20 / { compatible =3D "rockchip,rk3528"; @@ -95,6 +96,13 @@ xin24m: clock-xin24m { #clock-cells =3D <0>; }; =20 + phy50m_clk: clock-phy50m { + compatible =3D "fixed-clock"; + clock-frequency =3D <50000000>; + clock-output-names =3D "phy_50m_out"; + #clock-cells =3D <0>; + }; + soc { compatible =3D "simple-bus"; ranges =3D <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; @@ -114,6 +122,47 @@ gic: interrupt-controller@fed01000 { #interrupt-cells =3D <3>; }; =20 + cru: clock-controller@ff4a0000 { + compatible =3D "rockchip,rk3528-cru"; + reg =3D <0x0 0xff4a0000 0x0 0x30000>; + assigned-clocks =3D + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>; + assigned-clock-rates =3D + <32768>, <1188000000>, + <1000000000>, <996000000>, + <408000000>, <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + uart0: serial@ff9f0000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xff9f0000 0x0 0x100>; --=20 2.46.0 From nobody Thu Nov 28 13:40:19 2024 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4A51B9837; Tue, 1 Oct 2024 04:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727757593; cv=none; b=em9Ir+ZwED/ua5IxigqFVCTwDWJDwaI5InNDx/Uusv1LjTXZrjy3jCxRNsfvwale9s9dvk/PXhsVvI0ynbS/9YMqSAx4Pk2jh3bbTfy2IBveBSbIzXgECje09pBM940kXQ5qZaRASww1YwywC6uHn3QaJ4EzRHCkU8+p0g7Xd2c= ARC-Message-Signature: i=1; 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charset="utf-8" Add missing clocks in UART nodes for RK3528 SoC. Signed-off-by: Yao Zi --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index c0552ff7cd31..9c28e1d0d7ea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -166,7 +166,8 @@ cru: clock-controller@ff4a0000 { uart0: serial@ff9f0000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xff9f0000 0x0 0x100>; - clock-frequency =3D <24000000>; + clocks =3D <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -176,6 +177,8 @@ uart0: serial@ff9f0000 { uart1: serial@ff9f8000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xff9f8000 0x0 0x100>; + clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -185,6 +188,8 @@ uart1: serial@ff9f8000 { uart2: serial@ffa00000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xffa00000 0x0 0x100>; + clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -193,6 +198,8 @@ uart2: serial@ffa00000 { =20 uart3: serial@ffa08000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; + clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names =3D "baudclk", "apb_pclk"; reg =3D <0x0 0xffa08000 0x0 0x100>; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -202,6 +209,8 @@ uart3: serial@ffa08000 { uart4: serial@ffa10000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xffa10000 0x0 0x100>; + clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -211,6 +220,8 @@ uart4: serial@ffa10000 { uart5: serial@ffa18000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xffa18000 0x0 0x100>; + clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -220,6 +231,8 @@ uart5: serial@ffa18000 { uart6: serial@ffa20000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xffa20000 0x0 0x100>; + clocks =3D <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; @@ -229,6 +242,8 @@ uart6: serial@ffa20000 { uart7: serial@ffa28000 { compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg =3D <0x0 0xffa28000 0x0 0x100>; + clocks =3D <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names =3D "baudclk", "apb_pclk"; interrupts =3D ; reg-io-width =3D <4>; reg-shift =3D <2>; --=20 2.46.0