From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0EE1043155 for ; Tue, 1 Oct 2024 02:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750651; cv=none; b=WgzpXe4AzpVUXQgTaBpqq9lNEbHagPHRO2nlzTWx2zajvYWbkc4ZaYm9oQTUVTKxqB66u1bnN5SyGcgKucMTaB0iI54ozMTul/q9C2dLD4gdv759n+buWUOKI9B+USmerydODHF92pMK1SgC7xkzgQQT/jlOTZtO3FiKUVajfww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750651; c=relaxed/simple; bh=7a2bZySkeelcOgD9Rl0bih7p0vbDi14REltXeg9WLdA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nIhx1K7bnoJnYDdvovSIs04JB9UAMA+niOOqqax7Dpl9e5usJaUmV0ayzrsxFOdQVK2Q8CutSM6u7s1tOTtSpL0f7An9Hf5fN7ekmW/HRKmhkZgBYVzyfAzhUKdOPy3eCuUDoS42zNazXH77+j4AfwCq0FScwwYQkG9pYjbRCN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D6372DA7; Mon, 30 Sep 2024 19:44:38 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E4FFD3F58B; Mon, 30 Sep 2024 19:44:05 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 01/47] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 Date: Tue, 1 Oct 2024 08:13:10 +0530 Message-Id: <20241001024356.1096072-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64MMFR0_EL1.FGT and ID_AA64MMFR0_EL1.PARANGE register fields as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6..41b0e54515eb 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1556,6 +1556,7 @@ EndEnum UnsignedEnum 59:56 FGT 0b0000 NI 0b0001 IMP + 0b0010 FGT2 EndEnum Res0 55:48 UnsignedEnum 47:44 EXS @@ -1617,6 +1618,7 @@ Enum 3:0 PARANGE 0b0100 44 0b0101 48 0b0110 52 + 0b0111 56 EndEnum EndSysreg =20 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CBFC643155 for ; Tue, 1 Oct 2024 02:44:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750655; cv=none; b=D2Wxypra7Zbo0CyNp9Sh6Ceb88QsYhKMP50uW2zVb8kxtZXvim/PYeeCSqUhisQcaN13Bg07tg4JdEbq51n9wk1AZTo2QR/nlpycxsga6Z+bm0vvpiewLJHiIWB/6NuXkYW0uDC9dmtiIUm4XwZSOSXLuEmZbrutr4XI/FseNH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750655; c=relaxed/simple; bh=6bqCXfETTYasIuDes0nDf/4jwHva8W0JBSb/uG9wrBg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RPuy7us/O1sDMtFvDzbfbKJjxv33UkJWkZCDJbWkcAZSdOK2LV1PLTDEiF1Iwc2DWcWD/5/7E88NVKanWqYsJrpxHK86PuI2H0VRUQXuIPs0MIcwgpVlMG7H6TbLXl/pRmTmztpwrjQV43aEv5XRM0nBdm/SsBGxuMeKhIKqv/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D2C701424; Mon, 30 Sep 2024 19:44:42 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E1D093F58B; Mon, 30 Sep 2024 19:44:09 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 02/47] arm64/sysreg: Update register fields for ID_AA64DFR0_EL1 Date: Tue, 1 Oct 2024 08:13:11 +0530 Message-Id: <20241001024356.1096072-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64DFR0_EL1.[SEBEP|PMSS|PMUVer] register fields as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 41b0e54515eb..0e90d40af2bd 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1226,9 +1226,15 @@ UnsignedEnum 35:32 PMSVer 0b0101 V1P4 EndEnum Field 31:28 CTX_CMPs -Res0 27:24 +UnsignedEnum 27:24 SEBEP + 0b0000 NI + 0b0001 IMP +EndEnum Field 23:20 WRPs -Res0 19:16 +UnsignedEnum 19:16 PMSS + 0b0000 NI + 0b0001 IMP +EndEnum Field 15:12 BRPs UnsignedEnum 11:8 PMUVer 0b0000 NI @@ -1238,6 +1244,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 046E83C6AC for ; Tue, 1 Oct 2024 02:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750659; cv=none; b=Cs/BTaVCg5bUf8VNQNkJ1MssIMKs+7xWDqmdlXrn/RWqBZouOwYTLp0cNMy/+I37e5Bh3hCeJgET4ipLwpbN6X8imPsxC9QEB0JqeX+HdHQA06Db6+QAyaMu3BRrue+iaLBSCh+wcht+z0uEGtVz8mtYsQMLhZOqvLie7XoU9gE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750659; c=relaxed/simple; bh=zy5jMEzeZKEQbK80Q1ALmj2NdOI7sH0SCnDz4cQBGS0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PtNXz+aNov9diZ8VwENoNF/j4A6z1DhBqcHbkGKNIOavzVXQqFPu3Fqxf2Gngk1chQTDzOkYEy9iY3r4ZaIl2u4pE7xsk3T9rsShcR4FWfRVDDICngkAR/d3MVNELDeNQ+F8UjBSmRBKVdb+JHZk8l62vEYnY828sfJ2lFTYZig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CD67C367; Mon, 30 Sep 2024 19:44:46 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DCB9A3F58B; Mon, 30 Sep 2024 19:44:13 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 03/47] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1 Date: Tue, 1 Oct 2024 08:13:12 +0530 Message-Id: <20241001024356.1096072-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This updates ID_AA64PFR0_EL1.RAS and ID_AA64PFR0_EL1.RME register fields as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0e90d40af2bd..6c0893d0204a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -873,6 +873,7 @@ EndEnum UnsignedEnum 55:52 RME 0b0000 NI 0b0001 IMP + 0b0010 GPC2 EndEnum UnsignedEnum 51:48 DIT 0b0000 NI @@ -899,6 +900,7 @@ UnsignedEnum 31:28 RAS 0b0000 NI 0b0001 IMP 0b0010 V1P1 + 0b0011 V2 EndEnum UnsignedEnum 27:24 GIC 0b0000 NI --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E306C3C6AC for ; Tue, 1 Oct 2024 02:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750663; cv=none; b=Uk4YwbeEgKdvXAIvvwFvH/jPjnUy+EI3Mfm+U0TvDMUD8/kD+ntQrNR3wB4Zs0C+vIx1MeD3EIO7lPINjBaq1uVJ1mqKo+lkFysbGl8hd53QZqdB4ffoY0aVsvTbdjLZfF26oMgwFTWIf10z0zJjicH6wXQIbLBVA/8N27a2LsA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750663; c=relaxed/simple; bh=iWmVd5KiP80E0rsgjUkS/5lP5sRP+tDud2E5rI6LG6M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZD2pYS6ZLAo7i7Cu3e7x8o7XxIIxyaxD4eRk5IbozywMVUnExAcTSgiq2EiZIbH6VKjOIsybXVknlDqZq9zsIHj5YytBR1Ty8+FHFuwz0hdEGWDfLVgNDiz+Fb2doAdjOinwLZeHjVK8+7VuORrh3HFt6uhJ8NiCrgOBmpgFwsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C68CBDA7; Mon, 30 Sep 2024 19:44:50 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D59943F58B; Mon, 30 Sep 2024 19:44:17 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 04/47] arm64/sysreg: Add register fields for ID_AA64DFR2_EL1 Date: Tue, 1 Oct 2024 08:13:13 +0530 Message-Id: <20241001024356.1096072-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for ID_AA64DFR2_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6c0893d0204a..dbaa58be2e52 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1296,6 +1296,19 @@ Field 15:8 BRPs Field 7:0 SYSPMUID EndSysreg =20 +Sysreg ID_AA64DFR2_EL1 3 0 0 5 2 +Res0 63:8 +UnsignedEnum 7:4 BWE + 0b0000 NI + 0b0001 IMP + 0b0010 IMP_WPT +EndEnum +UnsignedEnum 3:0 STEP + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64AFR0_EL1 3 0 0 5 4 Res0 63:32 Field 31:28 IMPDEF7 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C832F41AAC for ; Tue, 1 Oct 2024 02:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750668; cv=none; b=OubLzZFyVAvxokFDIE/XDjibFx/ooVgo87t459f7e5A/mpBJQHuWcHP8RwkpoUI4O0HmdLGCv/CfT8kX2IhQqCSVfVswvbnrgMsF5Gnu7txZeuOdjyxa72GIKQnPvzk0PqGW7pdirtKvXuFoQuFB13VfmAZSvc8KNQdZFrKCH08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750668; c=relaxed/simple; bh=ThyN2vIj83BOmPVXc8/s3ei33drmki21fWAy4QzYBvE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g3iZ4efhGpAN41wHYzsdHsGqmGlhEzeg+4z8lNaO9sINCJ6oIn/SFxakVV3D/gwIX7ZdETebzBjJnU7/+7a6J9r4nvSVLXF8tgFtiKxT1EAQlHddQ9QAzY+FszmLprjN8CgAAOvUfCCcp8uv9igEjp9GX3zyTr2QyP8zgbxcF/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB7D01424; Mon, 30 Sep 2024 19:44:54 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D30203F58B; Mon, 30 Sep 2024 19:44:21 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 05/47] arm64/sysreg: Add register fields for HDFGRTR2_EL2 Date: Tue, 1 Oct 2024 08:13:14 +0530 Message-Id: <20241001024356.1096072-6-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGRTR2_EL2 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index dbaa58be2e52..87f04c56dea2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2487,6 +2487,34 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg =20 +Sysreg HDFGRTR2_EL2 3 4 3 1 0 +Res0 63:24 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Res0 21 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Field 18 nSPMDEVAFF_EL1 +Field 17 nSPMID +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Field 6 nPMSSDATA +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 86146757E0 for ; Tue, 1 Oct 2024 02:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750670; cv=none; b=N11WqSlKNtqzn0TJUi84lHiovSTpDAbY7/ZFisHnJ9ukNNY/aow+kYCA307hpjh3qM2R3GDYLwWidRRcuSUckdjsNuCHDWs8k/edIj7v8peRlgjeFU8ABQGmpnOvgeQSvut0MjeCm++jA0uvU4Bu9pWF5Haned4F3xWMuq1Js7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750670; c=relaxed/simple; bh=puTX5qF4W0JxHnVlb9dI2HlRjKiipZ5oJ/7PRPc6lGc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hKlTStjSMu5+VZC2LylUStr7slhxvjw6AaBu1stAWmoGmxP9t8ZAWOLsYU5GactOCaAyHZqZYjKhdn//4sydQ9NdD4Rm2glTNaqBKQLfdsn1VNJbLxPq5wzApCca+c/deeibXc/KeB40LCz3tUdf8oLshEzp+oXWV3xZw6sujbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB87F367; Mon, 30 Sep 2024 19:44:58 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C397A3F58B; Mon, 30 Sep 2024 19:44:25 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 06/47] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Date: Tue, 1 Oct 2024 08:13:15 +0530 Message-Id: <20241001024356.1096072-7-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HDFGWTR2_EL2 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 87f04c56dea2..bd1dfcbcff79 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2515,6 +2515,33 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HDFGWTR2_EL2 3 4 3 1 1 +Res0 63:24 +Field 23 nMDSTEPOP_EL1 +Field 22 nTRBMPAM_EL1 +Field 21 nPMZR_EL0 +Field 20 nTRCITECR_EL1 +Field 19 nPMSDSFR_EL1 +Res0 18:17 +Field 16 nSPMSCR_EL1 +Field 15 nSPMACCESSR_EL1 +Field 14 nSPMCR_EL0 +Field 13 nSPMOVS +Field 12 nSPMINTEN +Field 11 nSPMCNTEN +Field 10 nSPMSELR_EL0 +Field 9 nSPMEVTYPERn_EL0 +Field 8 nSPMEVCNTRn_EL0 +Field 7 nPMSSCR_EL1 +Res0 6 +Field 5 nMDSELR_EL1 +Field 4 nPMUACR_EL1 +Field 3 nPMICFILTR_EL0 +Field 2 nPMICNTR_EL0 +Field 1 nPMIAR_EL1 +Field 0 nPMECR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B839641AAC for ; Tue, 1 Oct 2024 02:44:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750675; cv=none; b=gFjGSAxf4uZd4FN+SS6p77ul8Dldnaa9TDc3C+DxvzpDbEuaDBV2azu2ThviMvxaBas5eEDEqcqpvSw16PMSZ6Kq7yWOiESFhnMyfVY+kfOwg4FzcULMCcp6FOVxoLfg0BFmAEM6ffaJrZFBvdh7Nn/c+bjXz9h2s/dctUHDeBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750675; c=relaxed/simple; bh=I72ucOlZXOs0xBlhQi+IZX6bPCqUlvn2yLnrl4aZU+M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ua9keiMTsOWH1V49OW9KuOO1mcc9t5N956Wr4B2tiuMlKrMUEgz/d26bpJpjj2loMt9F9o0d/keTEU9V4oPDi4czKIDYpAJYu2RrbwNgaRluBBh6IVun3a5u4mUaajvFG7IUfoOr0IT13zJFVhIgtIOTa1zd5+cPyLES+l2udws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A9355DA7; Mon, 30 Sep 2024 19:45:02 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B89FD3F58B; Mon, 30 Sep 2024 19:44:29 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 07/47] arm64/sysreg: Add register fields for HFGITR2_EL2 Date: Tue, 1 Oct 2024 08:13:16 +0530 Message-Id: <20241001024356.1096072-8-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGITR2_EL2 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index bd1dfcbcff79..300c19b09f1b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2714,6 +2714,10 @@ Field 1 AMEVCNTR00_EL0 Field 0 AMCNTEN0 EndSysreg =20 +Sysreg HFGITR2_EL2 3 4 3 1 7 +Res0 63:0 +EndSysreg + Sysreg ZCR_EL2 3 4 1 2 0 Fields ZCR_ELx EndSysreg --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7D02B4EB2B for ; Tue, 1 Oct 2024 02:44:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750678; cv=none; b=Fc78WBEQxunrkedkTvkR4fRb/XDurVa8CSNpFusMA+L9vBs3wkUhtRIcGEX8kHuQtjT/EbpVqmdgH67JgmhaBOfQrwW1vhkATdBjYw5q0VAzxu7nojvycDS6jjYGhXf6K7+CowRGdDnD2HVpJ4eUTZssOg6Cl9mEsUudYOrLKKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750678; c=relaxed/simple; bh=/fU0r7cqeUPXYgiwFab5oK19TbNZZUqniLv7M7NBe9w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PjpgppAmKshrea6jcb3PUS1V8txzOrnLq54QZ3Mh70UyV83BkxoPcne9kQtqXPJmT+9xyq1CSTTKkoyfWJ8U+hc4n4GrgRbu4to9WVBwcPkQnCdHKfzxyGauUc0rWESrsoh2OXWjY3Cm4zNO7CYp7PAw/wq6Se42VQe/gKD94g8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A79B6367; Mon, 30 Sep 2024 19:45:06 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B52B83F58B; Mon, 30 Sep 2024 19:44:33 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 08/47] arm64/sysreg: Add register fields for HFGRTR2_EL2 Date: Tue, 1 Oct 2024 08:13:17 +0530 Message-Id: <20241001024356.1096072-9-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGRTR2_EL2 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 300c19b09f1b..a790e2cc8003 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2542,6 +2542,13 @@ Field 1 nPMIAR_EL1 Field 0 nPMECR_EL1 EndSysreg =20 +Sysreg HFGRTR2_EL2 3 4 3 1 2 +Res0 63:3 +Field 2 nRCWSMASK_EL1 +Field 1 nERXGSR_EL1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 793CF13C9CD for ; Tue, 1 Oct 2024 02:44:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750683; cv=none; b=o/12YnWjBVJNdGR080wCGtzRH6bByzQTy/0i8iyjfvUavTiCHIMvRXAqZx+MVGD7B4tCoTC9mg/vojxAKyWFQaDuv/TBavqe9fImiWmItHf7VjDT+k4hBk/Zk8bGHmTv/2b8GAJDzcWCeUlVE+lzLFPlHrTXX3GFqC4YdXxQTYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750683; c=relaxed/simple; bh=VfmzQzuyjW7A6Z03KLvTzw4NM+GaIF5JZ8dWr2bc3qw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tWlMuxWkNG0T+2r5PkUe1FER46Zkr/fFFWDo0+x+q3zqiF8lIObzXN4J6LcMDeHJGAlW7GKCMMevs817xUhRvDYI0ijLmiYPJbtpIKQFbHrl2iaHjaM8Y1T2f7BPBUo7r03MCjPehZH1HnR9wGWaj1EFn+vdW7T7PTnA+jIJNNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E295DA7; Mon, 30 Sep 2024 19:45:10 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ADF483F58B; Mon, 30 Sep 2024 19:44:37 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 09/47] arm64/sysreg: Add register fields for HFGWTR2_EL2 Date: Tue, 1 Oct 2024 08:13:18 +0530 Message-Id: <20241001024356.1096072-10-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for HFGWTR2_EL2 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a790e2cc8003..6a1db83ac44e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2549,6 +2549,13 @@ Field 1 nERXGSR_EL1 Field 0 nPFAR_EL1 EndSysreg =20 +Sysreg HFGWTR2_EL2 3 4 3 1 3 +Res0 63:3 +Field 2 nRCWSMASK_EL1 +Res0 1 +Field 0 nPFAR_EL1 +EndSysreg + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6D89E1448ED for ; Tue, 1 Oct 2024 02:44:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750686; cv=none; b=e8xFR3RkTt39ZmkUl4yWYSH8t/UJtDWB/x73U4B59tJwdH3/xDZjgDuhwwrS5u03qFZkKqgu+seZxPB3ZjpGc2qK52B8hX6XPeR9uBn3ezPpfI+Dn7G1olbq7qkT8gGt6Wu7Ni0Cpv4jiiIxItQRPr7NJz5QXSNPRdPmeUo+uXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750686; c=relaxed/simple; bh=gGVHvhnKlXN/KZ4foWMen91Tls6SILXygcfJeiDuSck=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A6cnW3Jg/iggLLqsDQRW8Puw1GxNPxXdptpCVotwnPf3KikDPeTU4G2GkL5WkruyeyY74fd22keD53a/4PaJMfH6X5Qhwv4UjqvPojQ8p1SWj1LW0Ip0TanQfe+gi8b4gGfKaKLBvADMhxpaVX9BetA/mvqN/NZBrX7VnGNZoDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98024367; Mon, 30 Sep 2024 19:45:14 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A6ED23F58B; Mon, 30 Sep 2024 19:44:41 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 10/47] arm64/sysreg: Add register fields for MDSELR_EL1 Date: Tue, 1 Oct 2024 08:13:19 +0530 Message-Id: <20241001024356.1096072-11-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSELR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mark Brown Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6a1db83ac44e..b1ee29783628 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -93,6 +93,17 @@ Res0 63:32 Field 31:0 DTRTX EndSysreg =20 +Sysreg MDSELR_EL1 2 0 0 4 2 +Res0 63:6 +Enum 5:4 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +Res0 3:0 +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 69A7C13CF9E for ; Tue, 1 Oct 2024 02:44:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750690; cv=none; b=jjgaTToIOU2xwmhtxfJAtViJCOmCOUVXI+gRFDjshB4MRT7MppCqaWg25CLT0AM7XUkSSVmPo7w303zvFzbdUsv5ER2Z/8Tml4rcOneawGRm7llcUpoKrXjgAblzEzfSwTzH1MYC3+zwAlPZJ/h7ro4cuOcPPu3TvGGt83cZwI4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750690; c=relaxed/simple; bh=oQj98SQqbWjtBlbdRFDsOzuafqgXr/rZSTtlZabcbtY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KjbkY/4giLIzRSEVYnsf684etwGkNOAnHY89xjYlU+WBN/eRuR4JRZ4pS5IgWiY0BsnB8uNzeryWulxEY4EsNno8wS7Bv2FgMcx6SpqNag/0YtslPNFk884zoG6mQzdlrdQROwZBUJQJoHrKjM4AnRl6FAvjWa3rvE9FEEcbnqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 91ADD367; Mon, 30 Sep 2024 19:45:18 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A029A3F58B; Mon, 30 Sep 2024 19:44:45 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 11/47] arm64/sysreg: Add register fields for PMSIDR_EL1 Date: Tue, 1 Oct 2024 08:13:20 +0530 Message-Id: <20241001024356.1096072-12-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSIDR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b1ee29783628..eb2935df13f2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2139,7 +2139,16 @@ Field 15:0 MINLAT EndSysreg =20 Sysreg PMSIDR_EL1 3 0 9 9 7 -Res0 63:25 +Res0 63:33 +Field 32 SME +UnsignedEnum 31:28 ALTCLK + 0b0000 NI + 0b0001 IMP + 0b1111 IMP_DEF +EndEnum +Field 27 FPF +Field 26 EFT +Field 25 CRR Field 24 PBT Field 23:20 FORMAT Enum 19:16 COUNTSIZE @@ -2157,7 +2166,10 @@ Enum 11:8 INTERVAL 0b0111 3072 0b1000 4096 EndEnum -Res0 7 +UnsignedEnum 7 FDS + 0b0 NI + 0b1 IMP +EndEnum Field 6 FnE Field 5 ERND Field 4 LDS --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A304657CB5 for ; Tue, 1 Oct 2024 02:44:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750695; cv=none; b=YKzVtGguUMxepG+mY81Y+NzOCo3ijJilyJ077TMYl1cwIU6o34lQWni1ha3zuqnOnzmkw9rSP9ohXa/RGdDGLRfXP/N+mn8IVdIs4dwQkGd/ZiiHkvLrFzzQXi0jYeeD5ZEumcCBzS2fQ/oxEdEyhEIIsuuef4rI6zheuPQU/oA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750695; c=relaxed/simple; bh=pKveXfB3oFzcfsjv0L2NkOXo/5r/6JD2XngcRa8bozI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XlFJ0IkERUYMIvZolHLmafYdSZDwJK8xlTnxff8MOYb1FIuHgI491yAedpw/pZSa6lgXGlYzyNqMLA7hFN2ecq2cYl+VZDnfhdr8jKzggQS7lS1/9SeKHOtgqqNcDETLGCQNLTN2B1eOOi7QmM9+tEeWdKw00QrRt8ObVSD/BDY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8BC63367; Mon, 30 Sep 2024 19:45:22 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9A93A3F58B; Mon, 30 Sep 2024 19:44:49 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 12/47] arm64/sysreg: Add register fields for TRBIDR_EL1 Date: Tue, 1 Oct 2024 08:13:21 +0530 Message-Id: <20241001024356.1096072-13-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for TRBIDR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index eb2935df13f2..5ea714ec8f0e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3148,7 +3148,12 @@ Field 31:0 TRG EndSysreg =20 Sysreg TRBIDR_EL1 3 0 9 11 7 -Res0 63:12 +Res0 63:16 +UnsignedEnum 15:12 MPAM + 0b0000 NI + 0b0001 PMG + 0b0010 IMP +EndEnum Enum 11:8 EA 0b0000 NON_DESC 0b0001 IGNORE --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6285143AB4 for ; Tue, 1 Oct 2024 02:44:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750698; cv=none; b=IWK5+cdEt6hwooPlRBVEJ8471LaR/DxPOWi6CASr8/teN4CjG0q/Z1OvR3G7ZAh0MKrUAwsIZFTv2loo74ZeXo92NuYPrj6/7R52Xly8YhtgSvFtvZMhqvx2ZmJ1L7rACIZ6FtbXUwVPgt/qMhgIEManBqiPT1/QHuZgbsB61/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750698; c=relaxed/simple; bh=Hg1b8g0TPM8x0PusuTjVhZRcmZw3bg7qAno4BsXHjS0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Hm+u8KVeRln2AHF/+5u6ppKRlkI9XaUxPRtwSWdR0o8vPl16qNxckd8hYEzBoF6PlnN9Ixdg/IfysID6SMvsuZkgu7dSM53Ljzz/fwzZG7WOWx6V0vc5c4GryZF5vfde+Np8cbyNo3Gty4+Xi8RPV506m+sIGuMpn1IK7Z8gv9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88324DA7; Mon, 30 Sep 2024 19:45:26 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 949403F58B; Mon, 30 Sep 2024 19:44:53 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 13/47] arm64/sysreg: Add register fields for TRBMPAM_EL1 Date: Tue, 1 Oct 2024 08:13:22 +0530 Message-Id: <20241001024356.1096072-14-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for TRBMPAM_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 5ea714ec8f0e..8d931142e01a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3142,6 +3142,19 @@ EndEnum Field 7:0 Attr EndSysreg =20 +Sysreg TRBMPAM_EL1 3 0 9 11 5 +Res0 63:27 +Field 26 EN +UnsignedEnum 25:24 MPAM_SP + 0b00 SECURE_PARTID + 0b01 NON_SECURE_PARTID + 0b10 ROOT_PARTID + 0b11 REALM_PARTID +EndEnum +Field 23:16 PMG +Field 15:0 PARTID +EndSysreg + Sysreg TRBTRG_EL1 3 0 9 11 6 Res0 63:32 Field 31:0 TRG --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8A72B184533 for ; Tue, 1 Oct 2024 02:45:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750702; cv=none; b=CJn120MP+tBRjSQe6YQuOmvz6aXzK8wE086TjfrEOiiGuQRYIy6BvrgmZUvupZexjl4gjUwX1IsURSF1Y8gqcEKDN2me/MBccrAs7FQC/My/tiYryJn0favMSIClBt7by234sK3E4qpupt6HwJlrthNHudqUM4+ntwUBIrzFSYE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750702; c=relaxed/simple; bh=fveslmsGDp/OwpYM7VZgU4Z2NHQtZwfSn3DUxUehzHQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XfQkc1/i2Sp+YhMBJ4CBZgG9vABBY/7hKD96faSDjzR+Y3j+7id6m09DCOEoeovJulV9e4+7XNZX2kiRSQNaGs7XLDNMJTB0blshR5PhMjl3jwWEpfeDD58O3kMD+TgEh3Y56vupndZiZtq9QCExle6RsrzzpV+7ygf9G8qS3K0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 802B1367; Mon, 30 Sep 2024 19:45:30 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8E1833F58B; Mon, 30 Sep 2024 19:44:57 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 14/47] arm64/sysreg: Add register fields for PMSDSFR_EL1 Date: Tue, 1 Oct 2024 08:13:23 +0530 Message-Id: <20241001024356.1096072-15-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSDSFR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d931142e01a..865de0549a07 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2212,6 +2212,10 @@ Field 16 COLL Field 15:0 MSS EndSysreg =20 +Sysreg PMSDSFR_EL1 3 0 9 10 4 +Field 63:0 SM +EndSysreg + Sysreg PMBIDR_EL1 3 0 9 10 7 Res0 63:12 Enum 11:8 EA --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4F71318661C for ; Tue, 1 Oct 2024 02:45:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750709; cv=none; b=d4vkmdpm7VCBcDTOjwnFq1aU07Y06wS1Bc9Fp6OlOAP+EcKu5+0exgqJcB0sMu/7hIGCartJoTtKE+6AyVwiIiqmjCPQJUJpGcQdvL3UfqsDOo4/WXiXJ+rprKCb49PkPnwt/JtwMBUbf3YklSVo4tLrDNFEFruVwmAOVmhZAes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750709; c=relaxed/simple; bh=FmFgT7i4AWqEXHQB7lv0Vtfna1SJAAlcwLCClwLwyn4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gtqB7OBxMZU6C80zljEogigJfVDlR58Is5V/1geGtV3LjCC7uzfmjb2iIjMP5thd+RRdiMVJOS9IJPqiarrRN7L2Q0qh4RfcY3UzGVGvzL+yz4HmpIQ2tpWht28ncwKgBbFMquHOK9uMyLOIJ/T/bEopn/JLYRxGlly7JQpPJpE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 78D01367; Mon, 30 Sep 2024 19:45:34 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 871D43F58B; Mon, 30 Sep 2024 19:45:01 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 15/47] arm64/sysreg: Add register fields for SPMDEVAFF_EL1 Date: Tue, 1 Oct 2024 08:13:24 +0530 Message-Id: <20241001024356.1096072-16-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMDEVAFF_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 865de0549a07..5d76c0ddcb85 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,18 @@ Res0 63:1 Field 0 OSLK EndSysreg =20 +Sysreg SPMDEVAFF_EL1 2 0 9 13 6 +Res0 63:40 +Field 39:32 Aff3 +Field 31 F0V +Field 30 U +Res0 29:25 +Field 24 MT +Field 23:16 Aff2 +Field 15:8 Aff1 +Field 7:0 Aff0 +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5DD43208B0 for ; Tue, 1 Oct 2024 02:45:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750710; cv=none; b=WuElESQrsfEPGLERhBiMh6/ot2JTGEZt69NvIrBTNp/5not06IoPF0ausc5SHCeIVtFSAAOiVCFMODgYnavjpHQKj69n+Drr9HhfGaXiK9Xuom2TQ7C8zovUar9iShzxblSRoVdL409Uelppg4Y5dU71qHZFEkGCfEHDzliay4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750710; c=relaxed/simple; bh=YFSb3ZsAqNsZ4XsrD/4QG2OoAqj9LuUp28hiPLF3Nbo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UiTZtUDcz/i+zV76Zwo2dUdaJmFwrUQXm/YrkVtivNapEABiBatZosVR1gD+kuC4okMhrUdIIkQUS9qQyn+bGq657qCciZgbXqxAtg9SEcp0usLLCPsXHwQ9dd4LUtsxU95PEA2c05DZQhBFN+Jc8a/Gsp6vgIouYkK1XGHgQkQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71BE8DA7; Mon, 30 Sep 2024 19:45:38 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 80BC43F58B; Mon, 30 Sep 2024 19:45:05 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 16/47] arm64/sysreg: Add register fields for PFAR_EL1 Date: Tue, 1 Oct 2024 08:13:25 +0530 Message-Id: <20241001024356.1096072-17-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PFAR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 5d76c0ddcb85..ad0ab412e42f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3193,3 +3193,10 @@ Field 5 F Field 4 P Field 3:0 Align EndSysreg + +Sysreg PFAR_EL1 3 0 6 0 5 +Field 63 NS +Field 62 NSE +Res0 61:56 +Field 55:0 PA +EndSysreg --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 52EAC7347B for ; Tue, 1 Oct 2024 02:45:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750714; cv=none; b=kdd1mKpLfvHGjoGuUMt6XM6XkP6u51+pTTRrHU4Q4vcL1egd9kp3GKMAFC4jUiYP3dG/MwrrZfQEge6YgJltKYxyIdLc++Xjj1oNwP29EAa/fbzVVJYG7QCBEBEB3GijP1VoYVIUXDG2avWDStU6gm/pbMI1G4beHT08Fm9ETNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750714; c=relaxed/simple; bh=itrU9JEhVZDIDtlF96rJo51TQL5y7k4Z95/hdx6Pz1w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iBywcPKNJIG+Y6ptB0NmhpsXfPaZl6DrZEs9IBADElm7BPbFH1eDYdWDantiAalPnNUhSUY0v01DJSUlEhLGINiLDHIbGmPrvzE0020zCxW3pDiLBG7e01+2KVZL4j2geZ9lpWVYwdTZmIDt91rBd4AzHwRQ6C9CDugCD3wF9S8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7217E367; Mon, 30 Sep 2024 19:45:42 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7DEE73F58B; Mon, 30 Sep 2024 19:45:09 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 17/47] arm64/sysreg: Add register fields for PMIAR_EL1 Date: Tue, 1 Oct 2024 08:13:26 +0530 Message-Id: <20241001024356.1096072-18-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMIAR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ad0ab412e42f..b237813f6606 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2246,6 +2246,10 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMIAR_EL1 3 0 9 14 7 +Field 63:0 ADDRESS +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4220C7406F for ; Tue, 1 Oct 2024 02:45:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750718; cv=none; b=TG7X23KbXtbRywEnlT8/fBk9N/CvEphO/VRv1Dj6eiPUGApw8VuJf4wRpA7CwrIplJR3fAUuN2pVaiEfb2yLDrCyA12RHk1/YGx0y1C9K71I4WcMZkCUr0FfGlGGsl46ykQURaDtFmKgWQ6EAn1XgAlk5tpQ57/UrpEdUao5lOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750718; c=relaxed/simple; bh=lO0hxxeHm+toHm9ZcCaYAjpqeAynTqAjw4d2muiuxlY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fYhiMfqe55Qe/Gr1HcYdwPf174aRB+G04YnKPzwicNhghLKI3QHRMq7vTwGxnZ/2dkO91AtKTdZrzv77/3O15wdSoHDjfE7ait42v7hlDLPYx8JJ6Nt7LeSWVTj0ManSrWTD1gsdJhuq/yyDChoOdhEDvPwfkxXM/5c4tIqdD8A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6DBA8367; Mon, 30 Sep 2024 19:45:46 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7C96E3F58B; Mon, 30 Sep 2024 19:45:13 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 18/47] arm64/sysreg: Add register fields for PMECR_EL1 Date: Tue, 1 Oct 2024 08:13:27 +0530 Message-Id: <20241001024356.1096072-19-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMECR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b237813f6606..7e16e436eb58 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2246,6 +2246,21 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMECR_EL1 3 0 9 14 5 +Res0 63:5 +UnsignedEnum 4:3 SSE + 0b00 DISABLED + 0b10 ENABLED_PROHIBITED + 0b11 ENABLED_ALLOWED +EndEnum +Field 2 KPME +UnsignedEnum 1:0 PMEE + 0b00 PMUIRQ_E_PMU_D + 0b10 PMUIRQ_D_PMU_D + 0b11 PMUIRQ_D_PMU_E +EndEnum +EndSysreg + Sysreg PMIAR_EL1 3 0 9 14 7 Field 63:0 ADDRESS EndSysreg --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4BDCB74E26 for ; Tue, 1 Oct 2024 02:45:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750722; cv=none; b=ODP5rUzqfY9XF18ux6Vxd9BV6VViE5JK/4IZ6WNVq6NHCarxvpPIVpmCn29xA4Fvn0UiaL66G1SlM7PXvdZCpqmhBHwUw+UnQ0Lf4ZhPCKQhVPoZQ0NCk7SVwioKo2A4zVUAQG1aOYmKflAwk0/IWQ1K+NmXBTKG46hyUmjo2nk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750722; c=relaxed/simple; bh=QpWWLEKHzMWsLJ7pOprUWrOxJOJasgVq7bpn6Xc0Q/g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OjOsfOXdvf/55UChEbNB7EaWntyhtFCoHgBFljcXjZGIZ4s0oHYHM3LScTiHvmVQS813wc9s5fKEgWPxza6KJSio6nq/pqVNc8+WTQspaUEpJAMd/a/9XWZDk+6rjpfiGaGkocEhEzwuJTda6dGB3symNwG4YgBeoP9Yx3+mA7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B2A4367; Mon, 30 Sep 2024 19:45:50 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 79C413F58B; Mon, 30 Sep 2024 19:45:17 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 19/47] arm64/sysreg: Add register fields for PMUACR_EL1 Date: Tue, 1 Oct 2024 08:13:28 +0530 Message-Id: <20241001024356.1096072-20-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMUACR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7e16e436eb58..05799570a2d0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2246,6 +2246,43 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMUACR_EL1 3 0 9 14 4 +Res0 63:33 +Field 32 FM +Field 31 C +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg PMECR_EL1 3 0 9 14 5 Res0 63:5 UnsignedEnum 4:3 SSE --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7529977F1B for ; Tue, 1 Oct 2024 02:45:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750726; cv=none; b=jh1KGDW8kT/g6630KND6uScvbqoNgu/nObJeXkJQBdhPAqkM4nC1eDVD0m3fwMX8kD4bVAs/3bGvP8CJdWE7IkpVnEp/nvv+xgamIx5RAkEazhSL1HX5SBMmUF76VuZjI9polGEbCAikjPDCrAvEBmsClfKfp1a0R3vHuIz1hu0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750726; c=relaxed/simple; bh=+F8tRyA1w3O78zCq1NlwZ/vBUO2SB6DVEEOBFCq/wnc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lz6EuIe7v+r3k4zdbZJFgEkUFgUzgBT9+MLLXJAciHiavlD8SC002DiR/4CNWoS2U42WQIKT2Zc5UvmE+o5IOZSbevhfz9LlXCNmE1xjLTxg98SoTSL2rf3HCMMZLYAFwVYaXNp9cHvekbOL5+QEq/RAmSEEnmxXQ6+NugqW6IE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 69026367; Mon, 30 Sep 2024 19:45:54 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 76E933F58B; Mon, 30 Sep 2024 19:45:21 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 20/47] arm64/sysreg: Add register fields for PMCCNTSVR_EL1 Date: Tue, 1 Oct 2024 08:13:29 +0530 Message-Id: <20241001024356.1096072-21-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMCCNTSVR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 05799570a2d0..55836abbc8cc 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -126,6 +126,10 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg PMCCNTSVR_EL1 2 0 14 11 7 +Field 63:0 CCNT +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 38D69763EE for ; Tue, 1 Oct 2024 02:45:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750730; cv=none; b=qQJx7E4mGCKzjvsbwKbzKoj6RH68GEtS9Fef7QqepxLd02PmTr6PACHTROInhGi9cKFHrFeDNISm574+rHZiEjZOcsnFA7uJHfHaF2hBFGukDlik7m3pBIbUWqh0fRC4fCiu8JQkhY5poYdrXG45wI+RtYGCSSKujYyLoxcDvoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750730; c=relaxed/simple; bh=7u5nFux/52j9MoejXR4YQMHVLiIUFy4BZ9o6CgEXtKM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LpQxsrSTeFp5HhW2DlcDB66BFr1W//PhaQ+Q2qkQeA09QBk4a0EUVsdkQ53uL/gg/NIXAFXtTvzAwcRPDwlGEVBWs39hlyqOXD0MCEflubcUos9EpDJKDlOH3+jR97VaA/VyHeq4p41P7VSc4vHfRgp5DD/cn4nO/iRhGmNVaRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 620C5367; Mon, 30 Sep 2024 19:45:58 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7187E3F58B; Mon, 30 Sep 2024 19:45:25 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 21/47] arm64/sysreg: Add register fields for SPMSCR_EL1 Date: Tue, 1 Oct 2024 08:13:30 +0530 Message-Id: <20241001024356.1096072-22-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMSCR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 55836abbc8cc..44fabd1f3aef 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -130,6 +130,15 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg =20 +Sysreg SPMSCR_EL1 2 7 9 14 7 +Field 63:32 IMP_DEF +Field 31 RAO +Res0 30:5 +Field 4 NAO +Res0 3:1 +Field 0 SO +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 45CBF8060A for ; Tue, 1 Oct 2024 02:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750734; cv=none; b=CnRWa4CxO5vwA1u1iSUArwWB8XV0WHmeUSRjQ1u5GQnshugJ7qQozaEbB74SclFQc8mdA17/oQZnQ/Hxex0gv2vjXPGCF6+z4uodENb5bLIGhyQnOP3GKaP+hImMSvYKHEsDuA4YJ7UDRPz9C35E02utmxcX6J7H4jyy8UgOLOU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750734; c=relaxed/simple; bh=r3OxOh2YS1VHcZpxqA9dBOjugJRp7vOIfIKBj998eYQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jPFQ0qrzDQHePmlk5D1K2WDa6JH8mqYeJL/uin2bNMBvd1VFc8MveRYE0iVn2NAlWkpAnJZ924ygZw48lVMFnfbc8JfC3C4nQnfFFlIrsuXSXVjBed5ZinNDGstKpXGEFTmD8llzr1tHVF3mEi0Djl17f8LQ67EFP3+ALC1m9gc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56BDE367; Mon, 30 Sep 2024 19:46:02 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6DFEE3F58B; Mon, 30 Sep 2024 19:45:29 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 22/47] arm64/sysreg: Add register fields for SPMACCESSR_EL1 Date: Tue, 1 Oct 2024 08:13:31 +0530 Message-Id: <20241001024356.1096072-23-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMACCESSR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 44fabd1f3aef..06888559e5da 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,41 @@ Res0 63:1 Field 0 OSLK EndSysreg =20 +Sysreg SPMACCESSR_EL1 2 0 9 13 3 +Field 63:62 P31 +Field 61:60 P30 +Field 59:58 P29 +Field 57:56 P28 +Field 55:54 P27 +Field 53:52 P26 +Field 51:50 P25 +Field 49:48 P24 +Field 47:46 P23 +Field 45:44 P22 +Field 43:42 P21 +Field 41:40 P20 +Field 39:38 P19 +Field 37:36 P18 +Field 35:34 P17 +Field 33:32 P16 +Field 31:30 P15 +Field 29:28 P14 +Field 27:26 P13 +Field 25:24 P12 +Field 23:22 P11 +Field 21:20 P10 +Field 19:18 P9 +Field 17:16 P8 +Field 15:14 P7 +Field 13:12 P6 +Field 11:10 P5 +Field 9:8 P4 +Field 7:6 P3 +Field 5:4 P2 +Field 3:2 P1 +Field 1:0 P0 +EndSysreg + Sysreg SPMDEVAFF_EL1 2 0 9 13 6 Res0 63:40 Field 39:32 Aff3 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7814482863 for ; Tue, 1 Oct 2024 02:45:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750738; cv=none; b=BxcRTO+zM5/2/X0fheo8CUCv5wa4BG4fDNGPM9ZH1OGYCzZNeRvmQZ5gg1hRQ8KFL4k9TtBNkllz4KdomYskO0L/rSF2aG7PghIQLcfaLrrPVT/K8TeyCSWyzviGULCBBOOHTl+XMz+TrkrsEYZW+eO37P3/mABFEQEHavk5pzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750738; c=relaxed/simple; bh=Dzgs/drmGjnO+F3UdiewN51k5k7qXALUKxAAjI2K9mo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FcuSvP8rkdTg2q49byCR5GPs94+k48URG1xjoEujl1ClAXgC/E4cDPGRih0WBt3dkic0d34hPFd4eyBdbP3m8Y+4VTKdTg1JHGovrk3jmSMveSQ3SFd6yFVwzC4CdVRohOm7glAaXvT5WTnIPT7TFWn4f3YilcA5FTOIEFYNwOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E39A367; Mon, 30 Sep 2024 19:46:06 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5E3D03F58B; Mon, 30 Sep 2024 19:45:33 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 23/47] arm64/sysreg: Add register fields for PMICNTR_EL0 Date: Tue, 1 Oct 2024 08:13:32 +0530 Message-Id: <20241001024356.1096072-24-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMICNTR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 06888559e5da..4bf8ae6d8a26 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2488,6 +2488,10 @@ UnsignedEnum 2:0 F8S1 EndEnum EndSysreg =20 +Sysreg PMICNTR_EL0 3 3 9 4 0 +Field 63:0 ICNT +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23B12126BE3 for ; Tue, 1 Oct 2024 02:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750742; cv=none; b=Z+84ldIhCUwjNn1kS1Vqn7HKXW+Gr5EH5UX3FQbekJyPtFUDcHXFDsBoslIsk3bZ2nNe/pedoalGypplSDd7d9PWi1c9aRmOPfYgnS64XQzOuoP5BC7AbL7+10Sz5pIDXHZ93LWQyvfmeyg835JHotlAqby3wirHiKXJ19PktyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750742; c=relaxed/simple; bh=6u6zzcQCLNKKhc3FZ7bUkh38Q1So228MDyoO088uQOY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bNGSkuWJT9K0zUrRFmrgP59/cSCxq1Z+pLmru5C96JumR6pgI9U/dRbQFNNo2Dk2wgUu3D9C3L8EPMzGWKc/F+zKa7sxvTVa8pP9TedEP4KfoFh8c8Uf3QWYI+ULFAdqfOc4Yy8VKSM8JI7qH7dk1PlPw+cJaQQI2M3qG+cq5gc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47768367; Mon, 30 Sep 2024 19:46:10 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 56B883F58B; Mon, 30 Sep 2024 19:45:37 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 24/47] arm64/sysreg: Add register fields for PMICFILTR_EL0 Date: Tue, 1 Oct 2024 08:13:33 +0530 Message-Id: <20241001024356.1096072-25-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMICFILTR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4bf8ae6d8a26..300c213f39da 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2492,6 +2492,27 @@ Sysreg PMICNTR_EL0 3 3 9 4 0 Field 63:0 ICNT EndSysreg =20 +Sysreg PMICFILTR_EL0 3 3 9 6 0 +Res0 63:59 +Field 58 SYNC +Field 57:56 VS +Res0 55:32 +Field 31 P +Field 30 U +Field 29 NSK +Field 28 NSU +Field 27 NSH +Field 26 M +Res0 25 +Field 24 SH +Field 23 T +Field 22 RLK +Field 21 RLU +Field 20 RLH +Res0 19:16 +Field 15:0 evtCount +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 229064F20E for ; Tue, 1 Oct 2024 02:45:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750753; cv=none; b=UbkjE5frFGxJttY6kBP8nmY4ZPf5lzChIK3Cxk01F5PCVZzLPjL9M9hejciNniA/0Tz2uYFknvge0+Oi6U2/aRasQvyLb6jRFWyfNYWLQaBDhxsMnBuB43IXCyE+lRtIfVvHRi+px6Gmd9Pk40F6Au08Gt8+Z/yho/5Hqr/JPCk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750753; c=relaxed/simple; bh=Ebt5ETkYE1FsOPuL4prf6j1i6AmIrRJkdzLCZV7stM0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FJtwpl1U4hDiiZ7PXIkukepknLYJdo31JFwRAudW1RxnkJ2SQzwhagX9kK4L2FVA56wR+qV2Oz+mrnI9zKFtqgEZGUefmrnMJE9HHFPjqQfsHWpt8WQkMrbsOm2FWf2gNRyCs4CHzsB42zE2Sb7VfSRQngNoFdc3+VvTR0RFNJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 43A0B367; Mon, 30 Sep 2024 19:46:14 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 530BB3F58B; Mon, 30 Sep 2024 19:45:41 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 25/47] arm64/sysreg: Add register fields for SPMCR_EL0 Date: Tue, 1 Oct 2024 08:13:34 +0530 Message-Id: <20241001024356.1096072-26-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 300c213f39da..770c7ae23ce8 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -165,6 +165,19 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg =20 +Sysreg SPMCR_EL0 2 3 9 12 0 +Res0 63:12 +Field 11 TR0 +Field 10 HDBG +Field 9 FZ0 +Field 8 NA +Res0 7:5 +Field 4 EX +Res0 3:2 +Field 1 P +Field 0 E +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0C5DB502B1 for ; Tue, 1 Oct 2024 02:45:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750750; cv=none; b=RBtTs0w9Si6f4SdcMjkdWN9bJrIw50YsHFN9AsiusYbLsj2iUrtmmRilyuL5JBsmn6x6/Mzsg0gy2sfi5nIqN7BCmQfmpgOsAImDsWokD0Sza5nFkXGXB8iZyarUlEcAV+tOmi5F31d8EZqCjyktlf96mIZT1LuGs3xTWi42g6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750750; c=relaxed/simple; bh=FLRR8dtN1Z5ddxSR3XWn3bbxkjuosX1JdY4n+O0q6X0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=C2SzjFKNEx9RXJzbQvabGrfRcPVp+YUP46j0RKQkOb8gaFbCRrFsKLwRT2opiMDZDOcjnAcAUcUaMd8BY6xcMnPNcdpzkW/ru/oYH0F74I0QwhVR/LQaH/C/hBP8hk7wFl7JitzE3JxP1deokuE7kFZ5dlzg3Kg1Ij0zj73QvMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 373951424; Mon, 30 Sep 2024 19:46:18 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4E9693F58B; Mon, 30 Sep 2024 19:45:45 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 26/47] arm64/sysreg: Add register fields for SPMOVSCLR_EL0 Date: Tue, 1 Oct 2024 08:13:35 +0530 Message-Id: <20241001024356.1096072-27-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMOVSCLR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 770c7ae23ce8..b0ec176f099c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -178,6 +178,73 @@ Field 1 P Field 0 E EndSysreg =20 +Sysreg SPMOVSCLR_EL0 2 3 9 12 3 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 09E32199250 for ; Tue, 1 Oct 2024 02:45:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750754; cv=none; b=pEhhHEgLWrSxnK2smH2mYYBgb2O3JplZds48N7pxTcFMo3o8qXhTCzb7JZlhTIjCAuHGepAAmBBr8DdKvLTaV516cJj8YLYmMFibzW8QHL2r/HQM3Uo2P6fIHGCS3tAu0Kck2JYRj2HqDlvJHul16/PSF57ehqPqTYM4uSK2wek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750754; c=relaxed/simple; bh=uGRdedEYQ435jqic7LtklcgutzvTQlJE6lkx17iR5VM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uQuBb5HrpbNYMYnd5qKI1nk8qgiq7NJ35EfkCLAVR+VGrSQxwC096qzVaDbxq8FzaKh5H5RmUz0rwJCo2MFbWN0EDhozEhWQp7f8QmY3wBmsxsSzritCLr2hHbeyDsh97T6d91O9E+FFzcswb0E6UtfX9m7M9nRr8UTtZTH1m6Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2839DDA7; Mon, 30 Sep 2024 19:46:22 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3E7B23F58B; Mon, 30 Sep 2024 19:45:48 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 27/47] arm64/sysreg: Add register fields for SPMOVSSET_EL0 Date: Tue, 1 Oct 2024 08:13:36 +0530 Message-Id: <20241001024356.1096072-28-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMOVSSET_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b0ec176f099c..6086fcced8cf 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -245,6 +245,73 @@ Field 1 P1 Field 0 P0 EndSysreg =20 +Sysreg SPMOVSSET_EL0 2 3 9 14 3 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A0F21A2563 for ; Tue, 1 Oct 2024 02:45:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750758; cv=none; b=JfdKxg55J4F9c9u6iTs9Lq9nP9IalFG0teFfUSgIDPDmA3lnFU7q0cYHkoTh2CvF4Uek/4cdpBatf3RwrloaahSC3oVXKqtq778Srd/2QVDXgNbOALlWm/e6WxbkdlgXzIh4uHqMgo3Yea0+F4OkvVuYLTlI8xp6o4Db2axnPo8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750758; c=relaxed/simple; bh=XJe7RQF6fg9aFZh4nLFYUKte66aBl4qGde+CDtOwU3o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i0EMoFTyXsifUuEY1Odvl38COqb943NrYgKCT5lpmayzJOH1k9OWZaJcQ6scSOcMb+2wrMwSyNPOTHf7oKF7/FPBkLIlrqp9EYthSZq7ZJQfFww5r8WUIkG76uHYGAg5nOZpMzLq8eKTxOUuAqXAFBbgfeGejHfnE7V9vkkv7s4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16A82367; Mon, 30 Sep 2024 19:46:26 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2F1413F58B; Mon, 30 Sep 2024 19:45:52 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 28/47] arm64/sysreg: Add register fields for SPMINTENCLR_EL1 Date: Tue, 1 Oct 2024 08:13:37 +0530 Message-Id: <20241001024356.1096072-29-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMINTENCLR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6086fcced8cf..6c2696640083 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -161,6 +161,73 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg SPMINTENCLR_EL1 2 0 9 14 2 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DDCD13D0AD for ; Tue, 1 Oct 2024 02:46:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750762; cv=none; b=J35yNXsyIMSvVCx85yNvWB6PSYq5ReqRjlIcFWW7Krg/xEXZLArljotcrnP+LNkF4xusHufwmZ0f/eWLxO+1ozPYvlFe9y0EclyV94uBzw4N8JaMqbDwctcjzhHGc0V9gON+2oydaA4qYmF+cxZiYUfgddnoqcQqVrWVjUD6U+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750762; c=relaxed/simple; bh=vvHL7uNHZdTtxc5jbDqAKCnw4MdrQdYoxbelcglDZZ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qWQ4K2IfXu+Y7FFZ5eY//U6WrlE3bjssPZByslp6pP3lFhhTO5WhoI2SStI0rlTGPkUYLuESmQ//IV3I5uIRVWAyGeYL4GQXiQi6jZ10JPXELvtz/8xWFwqBCbkUJWWNyQLZQXCMCdlBNCYZMRcWQNR9NKzNn8XuW79T6O6Yeek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CC94DA7; Mon, 30 Sep 2024 19:46:30 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 242283F58B; Mon, 30 Sep 2024 19:45:56 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 29/47] arm64/sysreg: Add register fields for SPMINTENSET_EL1 Date: Tue, 1 Oct 2024 08:13:38 +0530 Message-Id: <20241001024356.1096072-30-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMINTENSET_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6c2696640083..e25418b95b96 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -161,6 +161,73 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg SPMINTENSET_EL1 2 0 9 14 1 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMINTENCLR_EL1 2 0 9 14 2 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D1F5D1A2633 for ; Tue, 1 Oct 2024 02:46:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750766; cv=none; b=J/6HcK+glQLPU4eL8GuhmWyrNNv3QQUdOrTMv0q5nTW/KSOYd0/obQvJUjyRGBhOp+ouNNDBCR9/ehoDddwAeEVe8uG3d8zLoh+YpIMUnVMTFzAJwXp4xnB1726QoCxgbrTPSGxW/Ox0WuMFuXqdqESNP4z37fZf0XsxWDge8rY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750766; c=relaxed/simple; bh=aReQRgm1qR02ccyZXkfHevWy9n0FnrXE0Xktos37xKY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r8v7o+WQa8+AR2GRD3CiUxsWVxOTyFohAMkG9TIOkQh4mGGODLmzWRj9k6bqa6LwaXCidUBJR061oU4f9/ddD48XdbVTzZvQdoMQIDhlenO1pPUQFbIRPyiTgAI8DOrywxRNYCwD/z7bQJpdkTh5V86Jpffn9TxkzjaB7L9Br40= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3DB3367; Mon, 30 Sep 2024 19:46:33 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 17CDC3F58B; Mon, 30 Sep 2024 19:46:00 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 30/47] arm64/sysreg: Add register fields for SPMCNTENCLR_EL0 Date: Tue, 1 Oct 2024 08:13:39 +0530 Message-Id: <20241001024356.1096072-31-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCNTENCLR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e25418b95b96..92cc19d3b7af 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -312,6 +312,73 @@ Field 1 P Field 0 E EndSysreg =20 +Sysreg SPMCNTENCLR_EL0 2 3 9 12 2 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMOVSCLR_EL0 2 3 9 12 3 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 06DE713F012 for ; Tue, 1 Oct 2024 02:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750770; cv=none; b=uVEgwDgzohJbrgf6C8FamgmwqzrXmkwt8AlM0V/H9XBgqUPWki6niH+WDkXR+r4mniOAT3ft/G0NHtmmj64pDxgg5CKlH9QMIJD845rF58Se8Vt2xp0ua8JNfyqklK1pI94EaER4oLR44oWH9+m2w/J13d3hY7th4LsmUZcTblU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750770; c=relaxed/simple; bh=Vo475ne4KrDObYsCEwpClhlolk1TVHYqTj94k04m48E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BCfCT4O44AJq+B3R00+W80rCalMbpNKGkp7iet+hdmStGULY1Fh+3TStxNpr/f54TmIiPeilcfQU+vhWB8Qz04oDqLTbk4RazT0ttynSkUZxNrWpWFQHTZOXzCTYMnOubrWcOuX+OGfHFEf9feY7r8+MUZ/nvF0O3WrFj0zxIXw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8617DA7; Mon, 30 Sep 2024 19:46:37 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0BEDF3F58B; Mon, 30 Sep 2024 19:46:04 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 31/47] arm64/sysreg: Add register fields for SPMCNTENSET_EL0 Date: Tue, 1 Oct 2024 08:13:40 +0530 Message-Id: <20241001024356.1096072-32-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCNTENSET_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 92cc19d3b7af..7369a044c649 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -312,6 +312,73 @@ Field 1 P Field 0 E EndSysreg =20 +Sysreg SPMCNTENSET_EL0 2 3 9 12 1 +Field 63 P63 +Field 62 P62 +Field 61 P61 +Field 60 P60 +Field 59 P59 +Field 58 P58 +Field 57 P57 +Field 56 P56 +Field 55 P55 +Field 54 P54 +Field 53 P53 +Field 52 P52 +Field 51 P51 +Field 50 P50 +Field 49 P49 +Field 48 P48 +Field 47 P47 +Field 46 P46 +Field 45 P45 +Field 44 P44 +Field 43 P43 +Field 42 P42 +Field 41 P41 +Field 40 P40 +Field 39 P39 +Field 38 P38 +Field 37 P37 +Field 36 P36 +Field 35 P35 +Field 34 P34 +Field 33 P33 +Field 32 P32 +Field 31 P31 +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + Sysreg SPMCNTENCLR_EL0 2 3 9 12 2 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B69E413F012 for ; Tue, 1 Oct 2024 02:46:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750774; cv=none; b=IoLqpwCzKicBDSqNsQ1OB5SEkewoGMUT5N8968PVF5bfhzZeU7oXd1dLwCeJZAO5lroy7gOuvq/Jyh3xwrGYXv2MsufLyfzKTBbjXoaiTGEzMDOKbvjaBOuWvxpTWiC6/k+QDrUyseCDUejOronWdwEt7ZvLRpUsiwYG8BCju/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750774; c=relaxed/simple; bh=OQyUWh4SFtdVNSomaxklDoFNEqsv6XPrHY/p9Twk2x4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hwyI2AzCKsOWrndLfsUD65465lWI53x1gZq8XOGfOVruRc+YihzWjzezfi45jjRsETp/dV8jOCP5pt6IdgJIu3k5WPr39IsAIkeF6PoUxlRz2qC0c63M/yZIHqgAG1y26bqvdRHwds6ROVwqZQHy1RXl59HB5Krg9Fvb+H/hLeo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2F70367; Mon, 30 Sep 2024 19:46:41 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F1B8F3F58B; Mon, 30 Sep 2024 19:46:08 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 32/47] arm64/sysreg: Add register fields for SPMSELR_EL0 Date: Tue, 1 Oct 2024 08:13:41 +0530 Message-Id: <20241001024356.1096072-33-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMSELR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7369a044c649..7144a65aed5e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -513,6 +513,18 @@ Field 1 P1 Field 0 P0 EndSysreg =20 +Sysreg SPMSELR_EL0 2 3 9 12 5 +Res0 63:10 +Field 9:4 SYSPMUSEL +Res0 3:2 +UnsignedEnum 1:0 BANK + 0b00 BANK_0 + 0b01 BANK_1 + 0b10 BANK_2 + 0b11 BANK_3 +EndEnum +EndSysreg + Sysreg SPMOVSSET_EL0 2 3 9 14 3 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0B0F014A097 for ; Tue, 1 Oct 2024 02:46:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750778; cv=none; b=YkoXb3QEDWmKtBQuKuWLU5wg2uk6AGs5zdK92TjSHUPtb2WZyr9PC3xpas356H7yhivbGuRcZe/JmtM614QwGOwB6dFV1b2XNn6dpYDiWL+aXFZKYaLUa3DaSCw+pJOtonNBpExLuVvqUrztZ8Yzyk3aid6X4GCIv+YlTEb1/+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750778; c=relaxed/simple; bh=ubfRMvxZ5Lv9bgIsKArS+CAeVMvdnhHm+EeXakFjK6c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ciah3rJGZ1T0ZPMoZBkwOqjFoVeOSlfvhffhAOULlaCxkXh/PVQzAjDmLhHtnQQNhLEoho38zWL2dt7A+MITJmn6ssTj+7R+w628f9S57baSZvddSgsohl/cmZlw9ABJghiuASBOsgGRHoRyY6WO3eLl3xdcxql6jC095C/jtAw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC050367; Mon, 30 Sep 2024 19:46:45 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EB09E3F58B; Mon, 30 Sep 2024 19:46:12 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 33/47] arm64/sysreg: Add register fields for PMICNTSVR_EL1 Date: Tue, 1 Oct 2024 08:13:42 +0530 Message-Id: <20241001024356.1096072-34-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMICNTSVR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7144a65aed5e..a649958b9fe8 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -299,6 +299,10 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg =20 +Sysreg PMICNTSVR_EL1 2 0 14 12 0 +Field 63:0 ICNT +EndSysreg + Sysreg SPMCR_EL0 2 3 9 12 0 Res0 63:12 Field 11 TR0 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 00CBD1448ED for ; Tue, 1 Oct 2024 02:46:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750782; cv=none; b=FPWk2tzdN7yXyULnLntA4AhORofIezswGbGTG8HQY5qXFZG+oXq7cF3m5BgFajM/JXWYm3H4ebQEk6FOjHvJrCg2RJhdI2c3nVT9TKzUTDvACYdgLumbXcpviLa8O1Iq+17wygBm5or0VEwhcBawTSBYHTOSzb86bB4YaJEplPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750782; c=relaxed/simple; bh=Om6ymydDeguPMUB5Oc+eo1SUOxo80N/JEHUsZwT5Uyo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iNWucNh3fmiNCRpeZy1i+F/iGduCCm8PvxrGrQSg2emqD7xFH6Yd9maiFCxa9k9ojjL383q8wtLJNmLqL7n7mSjQIziU0+80aIlSYqGC7sHayGitcAfqHmXw0xBGYiGk3IZ/n/BOoGCjyIbyNVCAu/emOQY8EUWtwikd8an2fAI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D9494367; Mon, 30 Sep 2024 19:46:49 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E7CD93F58B; Mon, 30 Sep 2024 19:46:16 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 34/47] arm64/sysreg: Add register fields for SPMIIDR_EL1 Date: Tue, 1 Oct 2024 08:13:43 +0530 Message-Id: <20241001024356.1096072-35-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMIIDR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a649958b9fe8..073d92fd085a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -149,6 +149,16 @@ Field 3:2 P1 Field 1:0 P0 EndSysreg =20 +Sysreg SPMIIDR_EL1 2 0 9 13 4 +Res0 63:32 +Field 31:20 ProductID +Field 19:16 Variant +Field 15:12 Revision +Field 11:8 Implementer_high +Res0 7 +Field 6:0 Implementer_low +EndSysreg + Sysreg SPMDEVAFF_EL1 2 0 9 13 6 Res0 63:40 Field 39:32 Aff3 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B5BD11552FF for ; Tue, 1 Oct 2024 02:46:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750786; cv=none; b=X6WFHoq8oa1n5zTPN7mI/U0J0uo/VtJX+ANB5YOXi1AX4GvWYJgkwcWF3Uehq7vP9vjXR/anXRayFIKxgS62TNIOGsFoVPAriYqhuzaAJpgrd9CVrWBZoY48tfF3p216Nmu4RgXB06YmI7hNvX75MOEvWp+i6i/QCbRkkhyw448= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750786; c=relaxed/simple; bh=SxvH6E3B8wImK1plrdYNyoq0sY2qMC5fGKPFE8UmKeg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q9CqL+B7DDrs4LYOKCwjDTSNnrS++FeewaDpSksQVtKNC4DluxFgrLpzqxRGlLUkHOBCZ8aMgNv9eeF5oKowEoZ7vIpSGAfYNZmSV6o9fK0VPLMxzeSYuoarlIUSNFepvpHNnFg1EMwM2kRxdrQDmE87A0rxQI/s/WA7ymO0OUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3AB9367; Mon, 30 Sep 2024 19:46:53 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E1A993F58B; Mon, 30 Sep 2024 19:46:20 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 35/47] arm64/sysreg: Add register fields for SPMDEVARCH_EL1 Date: Tue, 1 Oct 2024 08:13:44 +0530 Message-Id: <20241001024356.1096072-36-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMDEVARCH_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 073d92fd085a..270058558a24 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -159,6 +159,15 @@ Res0 7 Field 6:0 Implementer_low EndSysreg =20 +Sysreg SPMDEVARCH_EL1 2 0 9 13 5 +Res0 63:32 +Field 31:21 ARCHITECT +Field 20 PRESENT +Field 19:16 REVISION +Field 15:12 ARCHVER +Field 11:0 ARCHPART +EndSysreg + Sysreg SPMDEVAFF_EL1 2 0 9 13 6 Res0 63:40 Field 39:32 Aff3 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A88BB1552FF for ; Tue, 1 Oct 2024 02:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750789; cv=none; b=drGf4BvnKRThZeCeG7wjqg0W8481Ja0wBfiyvbpKMQ4lpqan0kpOC+hBiolvxfpvpglc+4r7JSwzwwCauKyDqqAUSAY1pRNh4TOb6NgxxyGMjtVS6zzG/EjQ9G8xa+Vo4UNs4pDJywLiSgOC2KAX8R8cFzcn3VhZrCOz3DYT9pY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750789; c=relaxed/simple; bh=7KiUN9C94ygCdrTgHsh9IlzGgra5s6KZhi1EQrwXttI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hRBxTG0+toSSNSmkJduuoA8irxQ9hX1bCBKFJd/1CwBexagMkFx4g5ufOrjIY5lhl/63TKgnF07Q2ubUcgLemudv+qt9m73fwXlZakvWr+okuqeqnji/TPRgg/bQtONdlawGjS3yQZ0CyOY13UvSSMDYqa4MO+BsofDHgTO58bM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1957367; Mon, 30 Sep 2024 19:46:57 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DF6263F58B; Mon, 30 Sep 2024 19:46:24 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 36/47] arm64/sysreg: Add register fields for SPMCFGR_EL1 Date: Tue, 1 Oct 2024 08:13:45 +0530 Message-Id: <20241001024356.1096072-37-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCFGR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 270058558a24..a07d89e43498 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -180,6 +180,24 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg =20 +Sysreg SPMCFGR_EL1 2 0 9 13 7 +Res0 63:32 +Field 31:28 NCG +Res0 27:25 +Field 24 HDBG +Field 23 TR0 +Field 22 SS +Field 21 FZ0 +Field 20 MSI +Field 19 RAO +Res0 18 +Field 17 NA +Field 16 EX +Field 15:14 RAZ +Field 13:8 SIZE +Field 7:0 N +EndSysreg + Sysreg SPMINTENSET_EL1 2 0 9 14 1 Field 63 P63 Field 62 P62 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A7B5159164 for ; Tue, 1 Oct 2024 02:46:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750793; cv=none; b=X1IGcApJ5I08Mf3EfLuw6yvtyVEaK1IFzC+Ho7lSq7WElvnhOv5+pbQ4he1+RTqSmD59KdpmNLogtkPwFvNsf3UXDHSQE22ESRJVG3sjQm18GbjNYKCIMgB8NXI5rjXDYz1yMTbNZ70nzC2I+8iFpLNpnEzeidGFtalzTXLWS5M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750793; c=relaxed/simple; bh=pLQu8xGE55F4N35v7rKltcJJAwb2/9S9HrZG8kTwoLo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=vCE/3yQuuGAENLiZYMxSbDP9UNL90569QmpG4W3/3u7eDMGnrtU/1ahVFIb/wsaX08PQYddSxA7dBYoXQ0zrIsvP65co2xxOQ4gLrGEVSq6tMRbo7Igbpko/k/+pY7Km9oyaPVmX+e3FgxxJTRBTgVbvbuRcEI4AKnzxuEAbVeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9537367; Mon, 30 Sep 2024 19:47:01 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D948B3F58B; Mon, 30 Sep 2024 19:46:28 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 37/47] arm64/sysreg: Add register fields for PMSSCR_EL1 Date: Tue, 1 Oct 2024 08:13:46 +0530 Message-Id: <20241001024356.1096072-38-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMSSCR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a07d89e43498..0043268765d5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2762,6 +2762,13 @@ Res0 63:5 Field 4:0 SEL EndSysreg =20 +Sysreg PMSSCR_EL1 3 0 9 13 3 +Res0 63:33 +Field 32 NC +Res0 31:1 +Field 0 SS +EndSysreg + Sysreg PMUACR_EL1 3 0 9 14 4 Res0 63:33 Field 32 FM --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ADB1916EB65 for ; Tue, 1 Oct 2024 02:46:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750798; cv=none; b=OiF/RReE3oBiNJol7ub/MZwaiYIczbIV4E+ljmYm5EPUdBqgg/Lem4TURbGvnYZ5w54iGa982xchZlsu0AUFK05i7ICnt5aR7jaKan11zK46oOkS+Ur8tBny2MRuPcYA4634I5UhzzMX5iVmqtBa8V9A/ebZ3PEJMTwfPlJQRD8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750798; c=relaxed/simple; bh=MsnaYWW7jfLrjyZAXfBIbCKlZUwms0GEnswCChULUyc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Sq0J4/RjicWR304xanHejggRzdZiYvsPMaIVFY3WisbZqtFfrjKqM2pF5oVjvXhL7/a1kcnBWEgdh6oRB1hhKKW5Gdo9G+8Qy92etrQkKH0DQR2HatjxbT2EDC1F/ZIZBPgf2Z54oXpg280Xul22UDjyMyjQi1xszca4ghJ7x/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C7D24367; Mon, 30 Sep 2024 19:47:05 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D68C13F58B; Mon, 30 Sep 2024 19:46:32 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 38/47] arm64/sysreg: Add register fields for PMZR_EL0 Date: Tue, 1 Oct 2024 08:13:47 +0530 Message-Id: <20241001024356.1096072-39-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for PMZR_EL0 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0043268765d5..020fda4fbd9b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2988,6 +2988,43 @@ Res0 19:16 Field 15:0 evtCount EndSysreg =20 +Sysreg PMZR_EL0 3 3 9 13 4 +Res0 63:33 +Field 32 FM +Field 31 C +Field 30 P30 +Field 29 P29 +Field 28 P28 +Field 27 P27 +Field 26 P26 +Field 25 P25 +Field 24 P24 +Field 23 P23 +Field 22 P22 +Field 21 P21 +Field 20 P20 +Field 19 P19 +Field 18 P18 +Field 17 P17 +Field 16 P16 +Field 15 P15 +Field 14 P14 +Field 13 P13 +Field 12 P12 +Field 11 P11 +Field 10 P10 +Field 9 P9 +Field 8 P8 +Field 7 P7 +Field 6 P6 +Field 5 P5 +Field 4 P4 +Field 3 P3 +Field 2 P2 +Field 1 P1 +Field 0 P0 +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9E59B175D36 for ; Tue, 1 Oct 2024 02:46:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750801; cv=none; b=owtIIay9KzojfdxTwp+esyW7cII0a72aH9FxE6AMP13Wr5pORP2eQvyZvat8UqJCHZsJPzZxpRi+8YH543aYYolHoKrAPquffY0bPzUbjk2NSsh0vjBKYXO7WftBGBjggGth1IeVhBNFbK/6Fxiqwmd7A9zQkzOIxgvQ4tT35Go= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750801; c=relaxed/simple; bh=8euke0Pyg6fNNprpVG35CncQYJaSm5+HM39YFbVmpGU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V1aXlWOmf35ZPKHNH5iCVbrQrqm7jvJqdybHcHVR5RgKKb4/P9tTPBEsC+W/xpoG2vf98o69NGGeDQLUG/PMYKgheDhfCogV+RBw6O+FscNm4s9F6IfAKBD3MiNL2eDPrbHP2f64A/TvX2k46MKhD04bedcnTVJUXxIwETKxdcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4DA9367; Mon, 30 Sep 2024 19:47:09 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D3A873F58B; Mon, 30 Sep 2024 19:46:36 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 39/47] arm64/sysreg: Add register fields for SPMCGCR0_EL1 Date: Tue, 1 Oct 2024 08:13:48 +0530 Message-Id: <20241001024356.1096072-40-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCGCR0_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 020fda4fbd9b..50397a1a5799 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -114,6 +114,21 @@ Res0 63:1 Field 0 OSLK EndSysreg =20 +SysregFields SPMCGCRx_EL1 +Field 63:56 N7 +Field 55:48 N6 +Field 47:40 N5 +Field 39:32 N4 +Field 31:24 N3 +Field 23:16 N2 +Field 15:8 N1 +Field 7:0 N0 +EndSysregFields + +Sysreg SPMCGCR0_EL1 2 0 9 13 0 +Fields SPMCGCRx_EL1 +EndSysreg + Sysreg SPMACCESSR_EL1 2 0 9 13 3 Field 63:62 P31 Field 61:60 P30 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 99F1E1A3BB1 for ; Tue, 1 Oct 2024 02:46:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750805; cv=none; b=Up7akMc30VCcxgjeOxlnZiXrBluGPsOPuTKn4cMVUEJhrYbd7zNBEc9MyQuRFOLWkTRxsq7FMb4x4jzNfa7bMDTkodkYpc4p2hTpN3D7gvveZ2kqJIfo5YweQ16mf7A2Txlj/fWWOVRIVFVPMBHJmqikDuv5AGsAVqrTt4dELbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750805; c=relaxed/simple; bh=Z7TScUmHHCtsxMxrUnLqllB6ap7TuudPJwolTLaBJAA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SReGIT4FGu6+YJFjg+vBM8/oCWMCAH54Wv8ByBFNL7sdSxPYf1KDgGFFWA0R/3ckCUtWs6FsCT+GzZJLPOCxme19o+zPsnasXppG/95iM/oAS8Di8OiVd4Y06UvaKmX6xSrpkq0AGYF6JyMIKoj2g3Qq1PIVt1Mj+lUbO/7m0G8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C072F367; Mon, 30 Sep 2024 19:47:13 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CDA4F3F58B; Mon, 30 Sep 2024 19:46:40 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 40/47] arm64/sysreg: Add register fields for SPMCGCR1_EL1 Date: Tue, 1 Oct 2024 08:13:49 +0530 Message-Id: <20241001024356.1096072-41-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMCGCR1_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 50397a1a5799..ad7a1dc05f8a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -129,6 +129,10 @@ Sysreg SPMCGCR0_EL1 2 0 9 13 0 Fields SPMCGCRx_EL1 EndSysreg =20 +Sysreg SPMCGCR1_EL1 2 0 9 13 1 +Fields SPMCGCRx_EL1 +EndSysreg + Sysreg SPMACCESSR_EL1 2 0 9 13 3 Field 63:62 P31 Field 61:60 P30 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 98D491A4E85 for ; Tue, 1 Oct 2024 02:46:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750809; cv=none; b=AD/seYuQAHn6JygK/7pttxtQDu//PkHgMDNqus3gZdYludToOuD/lV4MDg4PQ82LIvox0H+BhUm9XH6mUxTtyB8k33E5PDdEvwMAv3zHb1kmkaY7cfCucY90qff/aV/mjXKGjRlhjdilOW38G4Lkq9iB2c/teuDC5Dw0z9LRQf4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750809; c=relaxed/simple; bh=wMgypnA2sT2rJyjd3iDWDOsyQMje46x8yLReSJDYUMQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Oa1s9SW9oZPfcJF7dz3anCGn5otlAceVVKMY7FxlaoYQuqq493w36DQsi3eosMsXXkgWZ7zSuSjP2tWSU2rCj9wWRjVZ9W6z5pX3T7Q025bhHNrWqU/nPtxTzUPaG8PUgP6hNcvaM/qds4ne0BgwTAzYvwYm7+5bc0vvvTi1Xvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B98C1367; Mon, 30 Sep 2024 19:47:17 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C6E163F58B; Mon, 30 Sep 2024 19:46:44 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 41/47] arm64/sysreg: Add register fields for MDSTEPOP_EL1 Date: Tue, 1 Oct 2024 08:13:50 +0530 Message-Id: <20241001024356.1096072-42-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for MDSTEPOP_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index ad7a1dc05f8a..815e53200823 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -104,6 +104,11 @@ EndEnum Res0 3:0 EndSysreg =20 +Sysreg MDSTEPOP_EL1 2 0 0 5 2 +Res0 63:32 +Field 31:0 OPCODE +EndSysreg + Sysreg OSECCR_EL1 2 0 0 6 2 Res0 63:32 Field 31:0 EDECCR --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8000F171E69 for ; Tue, 1 Oct 2024 02:46:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750813; cv=none; b=GWRkalfHMLfvJNybSQbgpn9o8nEf3+I1PCkhYfvqEYo5h0i5VX+mJmsV+9AYRBZ+MAQTZh4NtZ8fCojShJnr0aLbqDsvmzg42I+9uBTcgX7sS2c+y2QeNFWvh9QJ9kUw8GY5ym/6CgRh/Tynj8tdtdPMGb8CAU8eozWsExXXbc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750813; c=relaxed/simple; bh=+3w73czdioQwj6aiUTB7t0Sm7NVDA77y+7j8AoScM0M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LS2oKvAlaY+s6h5GNy85mNwqK1PCvgDA3VOrNq+z2rHj9a2j+xQeSqPhX/dl29mrkQcGFL22wmynifcM/vF7pJ3CzUSV11c2fT8CO6981YjWonNkeASjEVgsZAiXl2U9utX2yUKVx3JlstKZIkJ8zQo8Tjy/wAFdWLrw22f/4rA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A92EB367; Mon, 30 Sep 2024 19:47:21 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C0EB53F58B; Mon, 30 Sep 2024 19:46:48 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 42/47] arm64/sysreg: Add register fields for ERXGSR_EL1 Date: Tue, 1 Oct 2024 08:13:51 +0530 Message-Id: <20241001024356.1096072-43-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for ERXGSR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 815e53200823..b464d02e5fb9 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3641,6 +3641,73 @@ Field 15:8 Attr1 Field 7:0 Attr0 EndSysregFields =20 +Sysreg ERXGSR_EL1 3 0 5 3 2 +Field 63 S63 +Field 62 S62 +Field 61 S61 +Field 60 S60 +Field 59 S59 +Field 58 S58 +Field 57 S57 +Field 56 S56 +Field 55 S55 +Field 54 S54 +Field 53 S53 +Field 52 S52 +Field 51 S51 +Field 50 S50 +Field 49 S49 +Field 48 S48 +Field 47 S47 +Field 46 S46 +Field 45 S45 +Field 44 S44 +Field 43 S43 +Field 42 S42 +Field 41 S41 +Field 40 S40 +Field 39 S39 +Field 38 S38 +Field 37 S37 +Field 36 S36 +Field 35 S35 +Field 34 S34 +Field 33 S33 +Field 32 S32 +Field 31 S31 +Field 30 S30 +Field 29 S29 +Field 28 S28 +Field 27 S27 +Field 26 S26 +Field 25 S25 +Field 24 S24 +Field 23 S23 +Field 22 S22 +Field 21 S21 +Field 20 S20 +Field 19 S19 +Field 18 S18 +Field 17 S17 +Field 16 S16 +Field 15 S15 +Field 14 S14 +Field 13 S13 +Field 12 S12 +Field 11 S11 +Field 10 S10 +Field 9 S9 +Field 8 S8 +Field 7 S7 +Field 6 S6 +Field 5 S5 +Field 4 S4 +Field 3 S3 +Field 2 S2 +Field 1 S1 +Field 0 S0 +EndSysreg + Sysreg MAIR2_EL1 3 0 10 2 1 Fields MAIR2_ELx EndSysreg --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A8030186E50 for ; Tue, 1 Oct 2024 02:46:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750819; cv=none; b=lcFYIrzoy3jEtp8ZSI8B+12bbB8CVARnaj1fvIJ/w4qjbIxBD9FHFtssMLOM/jTTMZAuBTO9X8JAMNznLYyc1XAQkBSai+EBWQhSz9YvJMe+8e/Q+VimQc4Cfj4tOPVTy39JQoSFrFWTLG6TV38uBKQWqz/3Bn6Zc4Y9MIbS7WQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750819; c=relaxed/simple; bh=4kHulIleLo7wrq2uuTN3bbXMYM955m5MTjifdw3TuF0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z6P9dWG65+u4iItnDyXCgIx03zWaiIKGmzhXgq3901hPugD06xq9fKYToKfiPtXbiQpMhvbBujkfxQEGatq+jVbFgmVR01gXzoB6UxztNveOHH4RZ6nVL8/CC3unOb0Mulz2psk7B4BvybAKPAh/Yf7qnn6KR7gEI/sizI0FP84= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A09E6DA7; Mon, 30 Sep 2024 19:47:25 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B4E373F58B; Mon, 30 Sep 2024 19:46:52 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 43/47] arm64/sysreg: Add register fields for SPMACCESSR_EL2 Date: Tue, 1 Oct 2024 08:13:52 +0530 Message-Id: <20241001024356.1096072-44-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds register fields for SPMACCESSR_EL2 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/tools/sysreg | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b464d02e5fb9..974218762525 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -657,6 +657,41 @@ Field 1 P1 Field 0 P0 EndSysreg =20 +Sysreg SPMACCESSR_EL2 2 4 9 13 3 +Field 63:62 P31 +Field 61:60 P30 +Field 59:58 P29 +Field 57:56 P28 +Field 55:54 P27 +Field 53:52 P26 +Field 51:50 P25 +Field 49:48 P24 +Field 47:46 P23 +Field 45:44 P22 +Field 43:42 P21 +Field 41:40 P20 +Field 39:38 P19 +Field 37:36 P18 +Field 35:34 P17 +Field 33:32 P16 +Field 31:30 P15 +Field 29:28 P14 +Field 27:26 P13 +Field 25:24 P12 +Field 23:22 P11 +Field 21:20 P10 +Field 19:18 P9 +Field 17:16 P8 +Field 15:14 P7 +Field 13:12 P6 +Field 11:10 P5 +Field 9:8 P4 +Field 7:6 P3 +Field 5:4 P2 +Field 3:2 P1 +Field 1:0 P0 +EndSysreg + Sysreg SPMSCR_EL1 2 7 9 14 7 Field 63:32 IMP_DEF Field 31 RAO --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 68F431A7AFA for ; Tue, 1 Oct 2024 02:47:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750824; cv=none; b=dMda2C8HfUIEy62v0Uf99hfwe9upmrnwzAo2U7epVtnXONWippDPgbEn6IaG06C1Ld5r6ujADYe5DCAr7oTxtEzk45QbstcEYERCBVcbPPGJxWyAIX355AtjkAIu6ihDHsye2DmMW89LES4ezJfglGqQ5yqye2Q2jnJsV70MY6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750824; c=relaxed/simple; bh=c5iqpaTf95rRwldBsOxLSTGZIJ/5YKpcEJwc6kNMkig=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FkJ87RPxmBNDZCJsGRBydzXR6aD5JNZAossJNKu6jcaHDuDzbyMA0aIlGNnuJtH6HBwC8ZKzlbEkGg4bXrmXgqgmXcLABOL7hl7Puh2oPdxUT1w4ouhPCocNjxvUy8eLTTYzhvINkvoi97WfnJq2O5Wg680XzBj2jvUr+F5oYuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9150D367; Mon, 30 Sep 2024 19:47:29 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A96F33F58B; Mon, 30 Sep 2024 19:46:56 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 44/47] arm64/sysreg: Add remaining debug registers affected by HDFGxTR2_EL2 Date: Tue, 1 Oct 2024 08:13:53 +0530 Message-Id: <20241001024356.1096072-45-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The HDFGxTR2_EL2 registers trap a set of debug and trace related registers. Almost all of those register encodings have been added in the tools sysreg format. Let's also add all the remaining encodings which are formula based (and only that, because we really don't care about what these registers actually do at this stage). Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/sysreg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 9ea97dddefc4..85cbce07ce77 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -270,6 +270,12 @@ #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) =20 +#define SYS_SPMEVCNTR_EL0(m) sys_reg(2, 3, 14, (0 | (m >> 3)), (m & 7)) +#define SYS_SPMEVTYPER_EL0(m) sys_reg(2, 3, 14, (2 | (m >> 3)), (m & 7)) +#define SYS_SPMEVFILTR_EL0(m) sys_reg(2, 3, 14, (4 | (m >> 3)), (m & 7)) +#define SYS_SPMEVFILT2R_EL0(m) sys_reg(2, 3, 14, (6 | (m >> 3)), (m & 7)) +#define SYS_PMEVCNTSVR_EL1(m) sys_reg(2, 0, 14, (8 | (m >> 3)), (m & 7)) + /* ETM */ #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) =20 --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 569E7186E50 for ; Tue, 1 Oct 2024 02:47:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750825; cv=none; b=qa8+zVMBZqDE3mZ3/bKU2c2uDJoBhoIAKDoboyY7+VoaKaPxmgHP0OmqHj26gbq4SzMUAhZkjf7NnLskdAP1ENgHm7QxGA78nEZ+NuEhxmqt+3FBZqAuikB4eMKQ6BhcFXBbOjucvbPfeHfT+iBz8A1+vuBNpnvZeUT70I/wwUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727750825; c=relaxed/simple; bh=QGnBB22jmRptXYSHNoWtj18XmGZ3BQmCB3OHM2NXs4M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=of/AkkX6kZUZCWQucs1zBWUg0GTvLZQdgCr1WT1tr/OylZ488YltOMRH4y23Rv96EEnism16kqIhFA3Hv5NfIcdeSssyPrtCwHzkYCfGeLQiXwerx9xLsinIAZUNDJtUSS4sNjVrGtSAuNKOU2U2EK8KC9P1DHALaZUDXqhuO1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 82E6DDA7; Mon, 30 Sep 2024 19:47:33 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9A91A3F58B; Mon, 30 Sep 2024 19:47:00 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 45/47] KVM: arm64: nv: Add FEAT_FGT2 registers access from virtual EL2 Date: Tue, 1 Oct 2024 08:13:54 +0530 Message-Id: <20241001024356.1096072-46-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds VNCR-capable HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2 and HFGITR2_EL2 FEAT_FGT2 registers into enum vcpu_sysreg, and also enables their access from virtual EL2 environment. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/kvm_host.h | 5 +++++ arch/arm64/include/asm/vncr_mapping.h | 5 +++++ arch/arm64/kvm/sys_regs.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 329619c6fa96..09291e1e42c9 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -532,6 +532,11 @@ enum vcpu_sysreg { VNCR(HDFGWTR_EL2), VNCR(HAFGRTR_EL2), =20 + VNCR(HDFGRTR2_EL2), + VNCR(HDFGWTR2_EL2), + VNCR(HFGITR2_EL2), + VNCR(HFGRTR2_EL2), + VNCR(HFGWTR2_EL2), VNCR(CNTVOFF_EL2), VNCR(CNTV_CVAL_EL0), VNCR(CNTV_CTL_EL0), diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index 06f8ec0906a6..8eab837196d0 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -38,6 +38,8 @@ #define VNCR_HFGRTR_EL2 0x1B8 #define VNCR_HFGWTR_EL2 0x1C0 #define VNCR_HFGITR_EL2 0x1C8 +#define VNCR_HDFGRTR2_EL2 0x1A0 +#define VNCR_HDFGWTR2_EL2 0x1B0 #define VNCR_HDFGRTR_EL2 0x1D0 #define VNCR_HDFGWTR_EL2 0x1D8 #define VNCR_ZCR_EL1 0x1E0 @@ -53,6 +55,9 @@ #define VNCR_PIRE0_EL2 0x298 #define VNCR_PIR_EL1 0x2A0 #define VNCR_POR_EL1 0x2A8 +#define VNCR_HFGRTR2_EL2 0x2C0 +#define VNCR_HFGWTR2_EL2 0x2C8 +#define VNCR_HFGITR2_EL2 0x310 #define VNCR_ICH_LR0_EL2 0x400 #define VNCR_ICH_LR1_EL2 0x408 #define VNCR_ICH_LR2_EL2 0x410 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dad88e31f953..778731491f79 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2794,9 +2794,14 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG_VNCR(VTCR_EL2, reset_val, 0), =20 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, + EL2_REG_VNCR(HDFGRTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HDFGWTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HFGRTR2_EL2, reset_val, 0), + EL2_REG_VNCR(HFGWTR2_EL2, reset_val, 0), EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0), EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0), EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0), + EL2_REG_VNCR(HFGITR2_EL2, reset_val, 0), EL2_REG_REDIR(SPSR_EL2, reset_val, 0), EL2_REG_REDIR(ELR_EL2, reset_val, 0), { SYS_DESC(SYS_SP_EL1), access_sp_el1}, --=20 2.25.1 From nobody Wed Dec 17 17:41:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9DAED22338 for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B8A8FDA7; Mon, 30 Sep 2024 19:47:37 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 915C03F58B; Mon, 30 Sep 2024 19:47:04 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 46/47] KVM: arm64: nv: Add FEAT_FGT2 registers based FGU handling Date: Tue, 1 Oct 2024 08:13:55 +0530 Message-Id: <20241001024356.1096072-47-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This enables FEAT_FGT2 registers based FGU handling by adding the following new groups in 'enum fgt_group_id' for all respective FGT control registers and also adding FGU behaviour for their individual managed registers access traps. 1. HDFGRTR2_GROUP 2. HDFGWTR2_GROUP 3. HFGRTR2_GROUP 4. HFGWTR2_GROUP 5. HFGITR2_GROUP Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/kvm_arm.h | 20 +++ arch/arm64/include/asm/kvm_host.h | 5 + arch/arm64/kvm/emulate-nested.c | 182 ++++++++++++++++++++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 26 ++++ arch/arm64/kvm/nested.c | 52 +++++++ arch/arm64/kvm/sys_regs.c | 59 ++++++++ 6 files changed, 344 insertions(+) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 109a85ee6910..449bccffd529 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -354,6 +354,26 @@ #define __HFGRTR_EL2_MASK GENMASK(49, 0) #define __HFGRTR_EL2_nMASK ~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK) =20 +#define __HDFGRTR2_EL2_RES0 HDFGRTR2_EL2_RES0 +#define __HDFGRTR2_EL2_MASK 0 +#define __HDFGRTR2_EL2_nMASK ~(__HDFGRTR2_EL2_RES0 | __HDFGRTR2_EL2_MASK) + +#define __HDFGWTR2_EL2_RES0 HDFGWTR2_EL2_RES0 +#define __HDFGWTR2_EL2_MASK 0 +#define __HDFGWTR2_EL2_nMASK ~(__HDFGWTR2_EL2_RES0 | __HDFGWTR2_EL2_MASK) + +#define __HFGITR2_EL2_RES0 HFGITR2_EL2_RES0 +#define __HFGITR2_EL2_MASK 0 +#define __HFGITR2_EL2_nMASK ~(__HFGITR2_EL2_RES0 | __HFGITR2_EL2_MASK) + +#define __HFGRTR2_EL2_RES0 HFGRTR2_EL2_RES0 +#define __HFGRTR2_EL2_MASK 0 +#define __HFGRTR2_EL2_nMASK ~(HFGRTR2_EL2_RES0 | __HFGRTR2_EL2_MASK) + +#define __HFGWTR2_EL2_RES0 HFGWTR2_EL2_RES0 +#define __HFGWTR2_EL2_MASK 0 +#define __HFGWTR2_EL2_nMASK ~(HFGWTR2_EL2_RES0 | __HFGWTR2_EL2_MASK) + /* * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any * future additions, define __HFGWTR* macros relative to __HFGRTR* ones. diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 09291e1e42c9..ca98f6d810c2 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -266,6 +266,11 @@ enum fgt_group_id { HDFGWTR_GROUP =3D HDFGRTR_GROUP, HFGITR_GROUP, HAFGRTR_GROUP, + HDFGRTR2_GROUP, + HDFGWTR2_GROUP =3D HDFGRTR2_GROUP, + HFGRTR2_GROUP, + HFGWTR2_GROUP =3D HFGRTR2_GROUP, + HFGITR2_GROUP, =20 /* Must be last */ __NR_FGT_GROUP_IDS__ diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 05b6435d02a9..f22a5f10ffe5 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1899,6 +1899,158 @@ static const struct encoding_to_trap_config encodin= g_to_fgt[] __initconst =3D { SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1), SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1), SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1), + + /* HDFGRTR2_EL2 */ + SR_FGT(SYS_MDSTEPOP_EL1, HDFGRTR2, nMDSTEPOP_EL1, 0), + SR_FGT(SYS_TRBMPAM_EL1, HDFGRTR2, nTRBMPAM_EL1, 0), + SR_FGT(SYS_TRCITECR_EL1, HDFGRTR2, nTRCITECR_EL1, 0), + SR_FGT(SYS_PMSDSFR_EL1, HDFGRTR2, nPMSDSFR_EL1, 0), + SR_FGT(SYS_SPMDEVAFF_EL1, HDFGRTR2, nSPMDEVAFF_EL1, 0), + + SR_FGT(SYS_SPMCGCR0_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMCGCR1_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMIIDR_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMDEVARCH_EL1, HDFGRTR2, nSPMID, 0), + SR_FGT(SYS_SPMCFGR_EL1, HDFGRTR2, nSPMID, 0), + + SR_FGT(SYS_SPMSCR_EL1, HDFGRTR2, nSPMSCR_EL1, 0), + SR_FGT(SYS_SPMACCESSR_EL1, HDFGRTR2, nSPMACCESSR_EL1, 0), + SR_FGT(SYS_SPMCR_EL0, HDFGRTR2, nSPMCR_EL0, 0), + SR_FGT(SYS_SPMOVSCLR_EL0, HDFGRTR2, nSPMOVS, 0), + SR_FGT(SYS_SPMOVSSET_EL0, HDFGRTR2, nSPMOVS, 0), + SR_FGT(SYS_SPMINTENCLR_EL1, HDFGRTR2, nSPMINTEN, 0), + SR_FGT(SYS_SPMINTENSET_EL1, HDFGRTR2, nSPMINTEN, 0), + SR_FGT(SYS_SPMCNTENCLR_EL0, HDFGRTR2, nSPMCNTEN, 0), + SR_FGT(SYS_SPMCNTENSET_EL0, HDFGRTR2, nSPMCNTEN, 0), + SR_FGT(SYS_SPMSELR_EL0, HDFGRTR2, nSPMSELR_EL0, 0), + + SR_FGT(SYS_SPMEVTYPER_EL0(0), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(1), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(2), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(3), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(4), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(5), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(6), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(7), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(8), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(9), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(10), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(11), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(12), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(13), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(14), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVTYPER_EL0(15), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + + SR_FGT(SYS_SPMEVFILTR_EL0(0), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(1), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(2), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(3), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(4), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(5), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(6), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(7), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(8), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(9), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(10), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(11), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(12), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(13), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(14), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILTR_EL0(15), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + + SR_FGT(SYS_SPMEVFILT2R_EL0(0), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(1), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(2), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(3), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(4), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(5), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(6), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(7), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(8), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(9), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(10), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(11), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(12), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(13), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(14), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + SR_FGT(SYS_SPMEVFILT2R_EL0(15), HDFGRTR2, nSPMEVTYPERn_EL0, 0), + + SR_FGT(SYS_SPMEVCNTR_EL0(0), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(1), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(2), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(3), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(4), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(5), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(6), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(7), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(8), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(9), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(10), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(11), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(12), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(13), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(14), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + SR_FGT(SYS_SPMEVCNTR_EL0(15), HDFGRTR2, nSPMEVCNTRn_EL0, 0), + + SR_FGT(SYS_PMSSCR_EL1, HDFGRTR2, nPMSSCR_EL1, 0), + SR_FGT(SYS_PMCCNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMICNTSVR_EL1, HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(0), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(1), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(2), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(3), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(4), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(5), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(6), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(7), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(8), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(9), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(10), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(11), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(12), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(13), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(14), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(15), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(16), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(17), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(18), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(19), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(20), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(21), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(22), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(23), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(24), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(25), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(26), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(27), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(28), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(29), HDFGRTR2, nPMSSDATA, 0), + SR_FGT(SYS_PMEVCNTSVR_EL1(30), HDFGRTR2, nPMSSDATA, 0), + + SR_FGT(SYS_MDSELR_EL1, HDFGRTR2, nMDSELR_EL1, 0), + SR_FGT(SYS_PMUACR_EL1, HDFGRTR2, nPMUACR_EL1, 0), + SR_FGT(SYS_PMICFILTR_EL0, HDFGRTR2, nPMICFILTR_EL0, 0), + SR_FGT(SYS_PMICNTR_EL0, HDFGRTR2, nPMICNTR_EL0, 0), + SR_FGT(SYS_PMIAR_EL1, HDFGRTR2, nPMIAR_EL1, 0), + SR_FGT(SYS_PMECR_EL1, HDFGRTR2, nPMECR_EL1, 0), + + /* + * HDFGWTR2_EL2 + * + * Although HDFGRTR2_EL2 and HDFGWTR2_EL2 registers largely + * overlap in their bit assignment, there are a number of bits + * that are RES0 on one side, and an actual trap bit on the + * other. The policy chosen here is to describe all the + * read-side mappings, and only the write-side mappings that + * differ from the read side, and the trap handler will pick + * the correct shadow register based on the access type. + */ + SR_FGT(SYS_PMZR_EL0, HDFGWTR2, nPMZR_EL0, 0), + + /* HFGRTR2_EL2 */ + SR_FGT(SYS_RCWSMASK_EL1, HFGRTR2, nRCWSMASK_EL1, 0), + SR_FGT(SYS_ERXGSR_EL1, HFGRTR2, nERXGSR_EL1, 0), + SR_FGT(SYS_PFAR_EL1, HFGRTR2, nPFAR_EL1, 0), }; =20 static union trap_config get_trap_config(u32 sysreg) @@ -2154,6 +2306,14 @@ static bool check_fgt_bit(struct kvm *kvm, bool is_r= ead, sr =3D is_read ? HDFGRTR_EL2 : HDFGWTR_EL2; break; =20 + case HDFGRTR2_GROUP: + sr =3D is_read ? HDFGRTR2_EL2 : HDFGWTR2_EL2; + break; + + case HFGRTR2_GROUP: + sr =3D is_read ? HFGRTR2_EL2 : HFGWTR2_EL2; + break; + case HAFGRTR_GROUP: sr =3D HAFGRTR_EL2; break; @@ -2162,6 +2322,10 @@ static bool check_fgt_bit(struct kvm *kvm, bool is_r= ead, sr =3D HFGITR_EL2; break; =20 + case HFGITR2_GROUP: + sr =3D HFGITR2_EL2; + break; + default: WARN_ONCE(1, "Unhandled FGT group"); return false; @@ -2228,6 +2392,20 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) val =3D __vcpu_sys_reg(vcpu, HDFGWTR_EL2); break; =20 + case HDFGRTR2_GROUP: + if (is_read) + val =3D __vcpu_sys_reg(vcpu, HDFGRTR2_EL2); + else + val =3D __vcpu_sys_reg(vcpu, HDFGWTR2_EL2); + break; + + case HFGRTR2_GROUP: + if (is_read) + val =3D __vcpu_sys_reg(vcpu, HFGRTR2_EL2); + else + val =3D __vcpu_sys_reg(vcpu, HFGWTR2_EL2); + break; + case HAFGRTR_GROUP: val =3D __vcpu_sys_reg(vcpu, HAFGRTR_EL2); break; @@ -2247,6 +2425,10 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) } break; =20 + case HFGITR2_GROUP: + val =3D __vcpu_sys_reg(vcpu, HFGITR2_EL2); + break; + case __NR_FGT_GROUP_IDS__: /* Something is really wrong, bail out */ WARN_ONCE(1, "__NR_FGT_GROUP_IDS__"); diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 46d52e8a3df3..570c061e8ccd 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -84,10 +84,21 @@ static inline void __activate_traps_fpsimd32(struct kvm= _vcpu *vcpu) case HFGITR_EL2: \ id =3D HFGITR_GROUP; \ break; \ + case HFGITR2_EL2: \ + id =3D HFGITR2_GROUP; \ + break; \ case HDFGRTR_EL2: \ case HDFGWTR_EL2: \ id =3D HDFGRTR_GROUP; \ break; \ + case HDFGRTR2_EL2: \ + case HDFGWTR2_EL2: \ + id =3D HDFGRTR2_GROUP; \ + break; \ + case HFGRTR2_EL2: \ + case HFGWTR2_EL2: \ + id =3D HFGRTR2_GROUP; \ + break; \ case HAFGRTR_EL2: \ id =3D HAFGRTR_GROUP; \ break; \ @@ -159,6 +170,11 @@ static inline void __activate_traps_hfgxtr(struct kvm_= vcpu *vcpu) CHECK_FGT_MASKS(HDFGWTR_EL2); CHECK_FGT_MASKS(HAFGRTR_EL2); CHECK_FGT_MASKS(HCRX_EL2); + CHECK_FGT_MASKS(HDFGRTR2_EL2); + CHECK_FGT_MASKS(HDFGWTR2_EL2); + CHECK_FGT_MASKS(HFGITR2_EL2); + CHECK_FGT_MASKS(HFGRTR2_EL2); + CHECK_FGT_MASKS(HFGWTR2_EL2); =20 if (!cpus_have_final_cap(ARM64_HAS_FGT)) return; @@ -170,6 +186,11 @@ static inline void __activate_traps_hfgxtr(struct kvm_= vcpu *vcpu) update_fgt_traps(hctxt, vcpu, kvm, HFGITR_EL2); update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR_EL2); update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HDFGRTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HDFGWTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HFGITR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HFGRTR2_EL2); + update_fgt_traps(hctxt, vcpu, kvm, HFGWTR2_EL2); =20 if (cpu_has_amu()) update_fgt_traps(hctxt, vcpu, kvm, HAFGRTR_EL2); @@ -199,6 +220,11 @@ static inline void __deactivate_traps_hfgxtr(struct kv= m_vcpu *vcpu) __deactivate_fgt(hctxt, vcpu, kvm, HFGITR_EL2); __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR_EL2); __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HDFGRTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HDFGWTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HFGITR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HFGRTR2_EL2); + __deactivate_fgt(hctxt, vcpu, kvm, HFGWTR2_EL2); =20 if (cpu_has_amu()) __deactivate_fgt(hctxt, vcpu, kvm, HAFGRTR_EL2); diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index f9e30dd34c7a..845fa765fcef 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1125,6 +1125,52 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |=3D HDFGRTR_EL2_nPMSNEVFR_EL1; set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1); =20 + /* HDFG[RW]TR2_EL2 */ + res0 =3D res1 =3D 0; + if (!kvm_has_feat_enum(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + res0 |=3D HDFGRTR2_EL2_nMDSTEPOP_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, ExtTrcBuff, IMP)) + res0 |=3D HDFGRTR2_EL2_nTRBMPAM_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, ITE, IMP)) + res0 |=3D HDFGRTR2_EL2_nTRCITECR_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, PMSVer, V1P4)) + res0 |=3D HDFGRTR2_EL2_nPMSDSFR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + res0 |=3D (HDFGRTR2_EL2_nSPMDEVAFF_EL1 | HDFGRTR2_EL2_nSPMID | + HDFGRTR2_EL2_nSPMSCR_EL1 | HDFGRTR2_EL2_nSPMACCESSR_EL1 | + HDFGRTR2_EL2_nSPMCR_EL0 | HDFGRTR2_EL2_nSPMOVS | + HDFGRTR2_EL2_nSPMINTEN | HDFGRTR2_EL2_nSPMCNTEN | + HDFGRTR2_EL2_nSPMSELR_EL0 | HDFGRTR2_EL2_nSPMEVTYPERn_EL0 | + HDFGRTR2_EL2_nSPMEVCNTRn_EL0); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + res0 |=3D (HDFGRTR2_EL2_nPMSSCR_EL1 | HDFGRTR2_EL2_nPMSSDATA); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + res0 |=3D HDFGRTR2_EL2_nMDSELR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) + res0 |=3D HDFGRTR2_EL2_nPMUACR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) + res0 |=3D (HDFGRTR2_EL2_nPMICFILTR_EL0 | HDFGRTR2_EL2_nPMICNTR_EL0); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, SEBEP, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMIAR_EL1; + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP) && + !kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + res0 |=3D HDFGRTR2_EL2_nPMECR_EL1; + set_sysreg_masks(kvm, HDFGRTR2_EL2, res0 | HDFGRTR2_EL2_RES0, res1 | HDFG= RTR2_EL2_RES1); + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) + res0 |=3D HDFGWTR2_EL2_nPMZR_EL0; + set_sysreg_masks(kvm, HDFGWTR2_EL2, res0 | HDFGWTR2_EL2_RES0, res1 | HDFG= WTR2_EL2_RES1); + + /* HFG[R|W]TR2_EL2 */ + res0 =3D res1 =3D 0; + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, THE, IMP)) + res0 |=3D HFGRTR2_EL2_nRCWSMASK_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, V2)) + res0 |=3D HFGRTR2_EL2_nERXGSR_EL1; + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, PFAR, IMP)) + res0 |=3D HFGRTR2_EL2_nPFAR_EL1; + set_sysreg_masks(kvm, HFGRTR2_EL2, res0 | HFGRTR2_EL2_RES0, res1 | HFGRTR= 2_EL2_RES1); + set_sysreg_masks(kvm, HFGWTR2_EL2, res0 | HFGWTR2_EL2_RES0, res1 | HFGWTR= 2_EL2_RES1); + /* Reuse the bits from the read-side and add the write-specific stuff */ if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP)) res0 |=3D (HDFGWTR_EL2_PMCR_EL0 | HDFGWTR_EL2_PMSWINC_EL0); @@ -1168,6 +1214,12 @@ int kvm_init_nv_sysregs(struct kvm *kvm) res0 |=3D HFGITR_EL2_ATS1E1A; set_sysreg_masks(kvm, HFGITR_EL2, res0, res1); =20 + /* HFGITR2_EL2 */ + res0 =3D HFGITR2_EL2_RES0; + res1 =3D HFGITR2_EL2_RES1; + set_sysreg_masks(kvm, HFGITR2_EL2, res0 | HFGITR2_EL2_RES0, res1 | HFGITR= 2_EL2_RES1); + set_sysreg_masks(kvm, HFGITR2_EL2, res0 | HFGITR2_EL2_RES0, res1 | HFGITR= 2_EL2_RES1); + /* HAFGRTR_EL2 - not a lot to see here */ res0 =3D HAFGRTR_EL2_RES0; res1 =3D HAFGRTR_EL2_RES1; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 778731491f79..4fbe6c6731c6 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4723,6 +4723,65 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) kvm->arch.fgu[HAFGRTR_GROUP] |=3D ~(HAFGRTR_EL2_RES0 | HAFGRTR_EL2_RES1); =20 + if (!kvm_has_feat_enum(kvm, ID_AA64DFR2_EL1, STEP, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nMDSTEPOP_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, ExtTrcBuff, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nTRBMPAM_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, ITE, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nTRCITECR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64DFR0_EL1, PMSVer, V1P4)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMSDSFR_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, SPMU, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nSPMDEVAFF_EL1 | + HDFGRTR2_EL2_nSPMID | + HDFGRTR2_EL2_nSPMSCR_EL1 | + HDFGRTR2_EL2_nSPMACCESSR_EL1 | + HDFGRTR2_EL2_nSPMCR_EL0 | + HDFGRTR2_EL2_nSPMOVS | + HDFGRTR2_EL2_nSPMINTEN | + HDFGRTR2_EL2_nSPMCNTEN | + HDFGRTR2_EL2_nSPMSELR_EL0 | + HDFGRTR2_EL2_nSPMEVTYPERn_EL0 | + HDFGRTR2_EL2_nSPMEVCNTRn_EL0; + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) { + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMSSCR_EL1; + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMSSDATA; + } + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, DebugVer, V8P9)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nMDSELR_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, V3P9)) { + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMUACR_EL1; + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGWTR2_EL2_nPMZR_EL0; + } + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, PMICNTR, IMP)) { + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMICFILTR_EL0; + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMICNTR_EL0; + } + + if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, SEBEP, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMIAR_EL1; + + if (!kvm_has_feat(kvm, ID_AA64DFR1_EL1, EBEP, IMP) && + !kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSS, IMP)) + kvm->arch.fgu[HDFGRTR2_GROUP] |=3D HDFGRTR2_EL2_nPMECR_EL1; + + if (!kvm_has_feat_enum(kvm, ID_AA64PFR1_EL1, THE, IMP)) + kvm->arch.fgu[HFGRTR2_GROUP] |=3D HFGRTR2_EL2_nRCWSMASK_EL1; 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Mon, 30 Sep 2024 19:47:08 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 47/47] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers Date: Tue, 1 Oct 2024 08:13:56 +0530 Message-Id: <20241001024356.1096072-48-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe remaining MDCR_EL2 register, and associate that with all FEAT_FGT2 exposed system registers it allows to trap. Cc: Marc Zyngier Cc: Oliver Upton Cc: James Morse Cc: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org Cc: kvmarm@lists.linux.dev Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/kvm_arm.h | 2 + arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/emulate-nested.c | 262 ++++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 449bccffd529..850fac9a7840 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -323,6 +323,7 @@ #define MDCR_EL2_TTRF (UL(1) << 19) #define MDCR_EL2_HPMD (UL(1) << 17) #define MDCR_EL2_TPMS (UL(1) << 14) +#define MDCR_EL2_EnSPM (UL(1) << 15) #define MDCR_EL2_E2PB_MASK (UL(0x3)) #define MDCR_EL2_E2PB_SHIFT (UL(12)) #define MDCR_EL2_TDRA (UL(1) << 11) @@ -333,6 +334,7 @@ #define MDCR_EL2_TPM (UL(1) << 6) #define MDCR_EL2_TPMCR (UL(1) << 5) #define MDCR_EL2_HPMN_MASK (UL(0x1F)) +#define MDCR_EL2_HPMN_SHIFT (UL(0)) #define MDCR_EL2_RES0 (GENMASK(63, 37) | \ GENMASK(35, 30) | \ GENMASK(25, 24) | \ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index ca98f6d810c2..802ad88235af 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -433,6 +433,7 @@ enum vcpu_sysreg { PMINTENSET_EL1, /* Interrupt Enable Set Register */ PMOVSSET_EL0, /* Overflow Flag Status Set Register */ PMUSERENR_EL0, /* User Enable Register */ + SPMSELR_EL0, /* System PMU Select Register */ =20 /* Pointer Authentication Registers in a strict increasing order. */ APIAKEYLO_EL1, @@ -491,6 +492,7 @@ enum vcpu_sysreg { CNTHP_CVAL_EL2, CNTHV_CTL_EL2, CNTHV_CVAL_EL2, + SPMACCESSR_EL2, /* System PMU Access Register */ =20 __VNCR_START__, /* Any VNCR-capable reg goes after this point */ =20 diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index f22a5f10ffe5..d66722c71b45 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -75,6 +75,7 @@ enum cgt_group_id { CGT_MDCR_TDRA, CGT_MDCR_E2PB, CGT_MDCR_TPMS, + CGT_MDCR_EnSPM, CGT_MDCR_TTRF, CGT_MDCR_E2TB, CGT_MDCR_TDCC, @@ -120,6 +121,38 @@ enum cgt_group_id { __COMPLEX_CONDITIONS__, CGT_CNTHCTL_EL1PCTEN =3D __COMPLEX_CONDITIONS__, CGT_CNTHCTL_EL1PTEN, + CGT_SPMSEL_SPMACCESS, + CGT_CNTR_ACCESSIBLE_0, + CGT_CNTR_ACCESSIBLE_1, + CGT_CNTR_ACCESSIBLE_2, + CGT_CNTR_ACCESSIBLE_3, + CGT_CNTR_ACCESSIBLE_4, + CGT_CNTR_ACCESSIBLE_5, + CGT_CNTR_ACCESSIBLE_6, + CGT_CNTR_ACCESSIBLE_7, + CGT_CNTR_ACCESSIBLE_8, + CGT_CNTR_ACCESSIBLE_9, + CGT_CNTR_ACCESSIBLE_10, + CGT_CNTR_ACCESSIBLE_11, + CGT_CNTR_ACCESSIBLE_12, + CGT_CNTR_ACCESSIBLE_13, + CGT_CNTR_ACCESSIBLE_14, + CGT_CNTR_ACCESSIBLE_15, + CGT_CNTR_ACCESSIBLE_16, + CGT_CNTR_ACCESSIBLE_17, + CGT_CNTR_ACCESSIBLE_18, + CGT_CNTR_ACCESSIBLE_19, + CGT_CNTR_ACCESSIBLE_20, + CGT_CNTR_ACCESSIBLE_21, + CGT_CNTR_ACCESSIBLE_22, + CGT_CNTR_ACCESSIBLE_23, + CGT_CNTR_ACCESSIBLE_24, + CGT_CNTR_ACCESSIBLE_25, + CGT_CNTR_ACCESSIBLE_26, + CGT_CNTR_ACCESSIBLE_27, + CGT_CNTR_ACCESSIBLE_28, + CGT_CNTR_ACCESSIBLE_29, + CGT_CNTR_ACCESSIBLE_30, =20 CGT_CPTR_TTA, =20 @@ -344,6 +377,12 @@ static const struct trap_bits coarse_trap_bits[] =3D { .mask =3D MDCR_EL2_TPMS, .behaviour =3D BEHAVE_FORWARD_ANY, }, + [CGT_MDCR_EnSPM] =3D { + .index =3D MDCR_EL2, + .value =3D MDCR_EL2_EnSPM, + .mask =3D MDCR_EL2_EnSPM, + .behaviour =3D BEHAVE_FORWARD_ANY, + }, [CGT_MDCR_TTRF] =3D { .index =3D MDCR_EL2, .value =3D MDCR_EL2_TTRF, @@ -498,6 +537,65 @@ static enum trap_behaviour check_cptr_tta(struct kvm_v= cpu *vcpu) return BEHAVE_HANDLE_LOCALLY; } =20 +static enum trap_behaviour check_spmsel_spmaccess(struct kvm_vcpu *vcpu) +{ + u64 spmaccessr_el2, spmselr_el2; + int syspmusel; + + if (__vcpu_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_EnSPM) { + spmselr_el2 =3D __vcpu_sys_reg(vcpu, SPMSELR_EL0); + spmaccessr_el2 =3D __vcpu_sys_reg(vcpu, SPMACCESSR_EL2); + syspmusel =3D FIELD_GET(SPMSELR_EL0_SYSPMUSEL_MASK, spmselr_el2); + + if (((spmaccessr_el2 >> (syspmusel * 2)) & 0x3) =3D=3D 0x0) + return BEHAVE_FORWARD_ANY; + } + return BEHAVE_HANDLE_LOCALLY; +} + +#define check_cntr_accessible(num) \ +static enum trap_behaviour check_cntr_accessible_##num(struct kvm_vcpu *vc= pu) \ +{ \ + u64 mdcr_el2 =3D __vcpu_sys_reg(vcpu, MDCR_EL2); \ + int cntr =3D FIELD_GET(MDCR_EL2_HPMN_MASK, mdcr_el2); \ + \ + if (num >=3D cntr) \ + return BEHAVE_FORWARD_ANY; \ + return BEHAVE_HANDLE_LOCALLY; \ +} \ + +check_cntr_accessible(0) +check_cntr_accessible(1) +check_cntr_accessible(2) +check_cntr_accessible(3) +check_cntr_accessible(4) +check_cntr_accessible(5) +check_cntr_accessible(6) +check_cntr_accessible(7) +check_cntr_accessible(8) +check_cntr_accessible(9) +check_cntr_accessible(10) +check_cntr_accessible(11) +check_cntr_accessible(12) +check_cntr_accessible(13) +check_cntr_accessible(14) +check_cntr_accessible(15) +check_cntr_accessible(16) +check_cntr_accessible(17) +check_cntr_accessible(18) +check_cntr_accessible(19) +check_cntr_accessible(20) +check_cntr_accessible(21) +check_cntr_accessible(22) +check_cntr_accessible(23) +check_cntr_accessible(24) +check_cntr_accessible(25) +check_cntr_accessible(26) +check_cntr_accessible(27) +check_cntr_accessible(28) +check_cntr_accessible(29) +check_cntr_accessible(30) + #define CCC(id, fn) \ [id - __COMPLEX_CONDITIONS__] =3D fn =20 @@ -505,6 +603,38 @@ static const complex_condition_check ccc[] =3D { CCC(CGT_CNTHCTL_EL1PCTEN, check_cnthctl_el1pcten), CCC(CGT_CNTHCTL_EL1PTEN, check_cnthctl_el1pten), CCC(CGT_CPTR_TTA, check_cptr_tta), + CCC(CGT_SPMSEL_SPMACCESS, check_spmsel_spmaccess), + CCC(CGT_CNTR_ACCESSIBLE_0, check_cntr_accessible_0), + CCC(CGT_CNTR_ACCESSIBLE_1, check_cntr_accessible_1), + CCC(CGT_CNTR_ACCESSIBLE_2, check_cntr_accessible_2), + CCC(CGT_CNTR_ACCESSIBLE_3, check_cntr_accessible_3), + CCC(CGT_CNTR_ACCESSIBLE_4, check_cntr_accessible_4), + CCC(CGT_CNTR_ACCESSIBLE_5, check_cntr_accessible_5), + CCC(CGT_CNTR_ACCESSIBLE_6, check_cntr_accessible_6), + CCC(CGT_CNTR_ACCESSIBLE_7, check_cntr_accessible_7), + CCC(CGT_CNTR_ACCESSIBLE_8, check_cntr_accessible_8), + CCC(CGT_CNTR_ACCESSIBLE_9, check_cntr_accessible_9), + CCC(CGT_CNTR_ACCESSIBLE_10, check_cntr_accessible_10), + CCC(CGT_CNTR_ACCESSIBLE_11, check_cntr_accessible_11), + CCC(CGT_CNTR_ACCESSIBLE_12, check_cntr_accessible_12), + CCC(CGT_CNTR_ACCESSIBLE_13, check_cntr_accessible_13), + CCC(CGT_CNTR_ACCESSIBLE_14, check_cntr_accessible_14), + CCC(CGT_CNTR_ACCESSIBLE_15, check_cntr_accessible_15), + CCC(CGT_CNTR_ACCESSIBLE_16, check_cntr_accessible_16), + CCC(CGT_CNTR_ACCESSIBLE_17, check_cntr_accessible_17), + CCC(CGT_CNTR_ACCESSIBLE_18, check_cntr_accessible_18), + CCC(CGT_CNTR_ACCESSIBLE_19, check_cntr_accessible_19), + CCC(CGT_CNTR_ACCESSIBLE_20, check_cntr_accessible_20), + CCC(CGT_CNTR_ACCESSIBLE_21, check_cntr_accessible_21), + CCC(CGT_CNTR_ACCESSIBLE_22, check_cntr_accessible_22), + CCC(CGT_CNTR_ACCESSIBLE_23, check_cntr_accessible_23), + CCC(CGT_CNTR_ACCESSIBLE_24, check_cntr_accessible_24), + CCC(CGT_CNTR_ACCESSIBLE_25, check_cntr_accessible_25), + CCC(CGT_CNTR_ACCESSIBLE_26, check_cntr_accessible_26), + CCC(CGT_CNTR_ACCESSIBLE_27, check_cntr_accessible_27), + CCC(CGT_CNTR_ACCESSIBLE_28, check_cntr_accessible_28), + CCC(CGT_CNTR_ACCESSIBLE_29, check_cntr_accessible_29), + CCC(CGT_CNTR_ACCESSIBLE_30, check_cntr_accessible_30), }; =20 /* @@ -912,6 +1042,7 @@ static const struct encoding_to_trap_config encoding_t= o_cgt[] __initconst =3D { SR_TRAP(SYS_ERXPFGF_EL1, CGT_HCR_nFIEN), SR_TRAP(SYS_ERXPFGCTL_EL1, CGT_HCR_nFIEN), SR_TRAP(SYS_ERXPFGCDN_EL1, CGT_HCR_nFIEN), + SR_TRAP(SYS_PMCR_EL0, CGT_MDCR_TPM_TPMCR), SR_TRAP(SYS_PMCNTENSET_EL0, CGT_MDCR_TPM), SR_TRAP(SYS_PMCNTENCLR_EL0, CGT_MDCR_TPM), @@ -1085,6 +1216,7 @@ static const struct encoding_to_trap_config encoding_= to_cgt[] __initconst =3D { SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), + SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), @@ -1092,6 +1224,136 @@ static const struct encoding_to_trap_config encodin= g_to_cgt[] __initconst =3D { SR_TRAP(SYS_TRBPTR_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBSR_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBTRG_EL1, CGT_MDCR_E2TB), + + SR_TRAP(SYS_MDSTEPOP_EL1, CGT_MDCR_TDE_TDA), + SR_TRAP(SYS_TRBMPAM_EL1, CGT_MDCR_E2TB), + SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS), + + SR_TRAP(SYS_SPMDEVAFF_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCGCR0_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCGCR1_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMIIDR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMDEVARCH_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCFGR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMSCR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMACCESSR_EL1, CGT_MDCR_EnSPM), + SR_TRAP(SYS_SPMCR_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMOVSCLR_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMOVSSET_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMINTENCLR_EL1, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMINTENSET_EL1, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMCNTENCLR_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMCNTENSET_EL0, CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMSELR_EL0, CGT_MDCR_EnSPM), + + SR_TRAP(SYS_SPMEVTYPER_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVTYPER_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_SPMEVFILTR_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILTR_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_SPMEVFILT2R_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVFILT2R_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_SPMEVCNTR_EL0(0), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(1), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(2), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(3), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(4), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(5), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(6), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(7), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(8), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(9), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(10), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(11), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(12), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(13), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(14), CGT_SPMSEL_SPMACCESS), + SR_TRAP(SYS_SPMEVCNTR_EL0(15), CGT_SPMSEL_SPMACCESS), + + SR_TRAP(SYS_PMEVCNTSVR_EL1(0), CGT_CNTR_ACCESSIBLE_0), + SR_TRAP(SYS_PMEVCNTSVR_EL1(1), CGT_CNTR_ACCESSIBLE_1), + SR_TRAP(SYS_PMEVCNTSVR_EL1(2), CGT_CNTR_ACCESSIBLE_2), + SR_TRAP(SYS_PMEVCNTSVR_EL1(3), CGT_CNTR_ACCESSIBLE_3), + SR_TRAP(SYS_PMEVCNTSVR_EL1(4), CGT_CNTR_ACCESSIBLE_4), + SR_TRAP(SYS_PMEVCNTSVR_EL1(5), CGT_CNTR_ACCESSIBLE_5), + SR_TRAP(SYS_PMEVCNTSVR_EL1(6), CGT_CNTR_ACCESSIBLE_6), + SR_TRAP(SYS_PMEVCNTSVR_EL1(7), CGT_CNTR_ACCESSIBLE_7), + SR_TRAP(SYS_PMEVCNTSVR_EL1(8), CGT_CNTR_ACCESSIBLE_8), + SR_TRAP(SYS_PMEVCNTSVR_EL1(9), CGT_CNTR_ACCESSIBLE_9), + SR_TRAP(SYS_PMEVCNTSVR_EL1(10), CGT_CNTR_ACCESSIBLE_10), + SR_TRAP(SYS_PMEVCNTSVR_EL1(11), CGT_CNTR_ACCESSIBLE_11), + SR_TRAP(SYS_PMEVCNTSVR_EL1(12), CGT_CNTR_ACCESSIBLE_12), + SR_TRAP(SYS_PMEVCNTSVR_EL1(13), CGT_CNTR_ACCESSIBLE_13), + SR_TRAP(SYS_PMEVCNTSVR_EL1(14), CGT_CNTR_ACCESSIBLE_14), + SR_TRAP(SYS_PMEVCNTSVR_EL1(15), CGT_CNTR_ACCESSIBLE_15), + SR_TRAP(SYS_PMEVCNTSVR_EL1(16), CGT_CNTR_ACCESSIBLE_16), + SR_TRAP(SYS_PMEVCNTSVR_EL1(17), CGT_CNTR_ACCESSIBLE_17), + SR_TRAP(SYS_PMEVCNTSVR_EL1(18), CGT_CNTR_ACCESSIBLE_18), + SR_TRAP(SYS_PMEVCNTSVR_EL1(19), CGT_CNTR_ACCESSIBLE_19), + SR_TRAP(SYS_PMEVCNTSVR_EL1(20), CGT_CNTR_ACCESSIBLE_20), + SR_TRAP(SYS_PMEVCNTSVR_EL1(21), CGT_CNTR_ACCESSIBLE_21), + SR_TRAP(SYS_PMEVCNTSVR_EL1(22), CGT_CNTR_ACCESSIBLE_22), + SR_TRAP(SYS_PMEVCNTSVR_EL1(23), CGT_CNTR_ACCESSIBLE_23), + SR_TRAP(SYS_PMEVCNTSVR_EL1(24), CGT_CNTR_ACCESSIBLE_24), + SR_TRAP(SYS_PMEVCNTSVR_EL1(25), CGT_CNTR_ACCESSIBLE_25), + SR_TRAP(SYS_PMEVCNTSVR_EL1(26), CGT_CNTR_ACCESSIBLE_26), + SR_TRAP(SYS_PMEVCNTSVR_EL1(27), CGT_CNTR_ACCESSIBLE_27), + SR_TRAP(SYS_PMEVCNTSVR_EL1(28), CGT_CNTR_ACCESSIBLE_28), + SR_TRAP(SYS_PMEVCNTSVR_EL1(29), CGT_CNTR_ACCESSIBLE_29), + SR_TRAP(SYS_PMEVCNTSVR_EL1(30), CGT_CNTR_ACCESSIBLE_30), + + SR_TRAP(SYS_MDSELR_EL1, CGT_MDCR_TDE_TDA), + SR_TRAP(SYS_PMUACR_EL1, CGT_MDCR_TPM), + SR_TRAP(SYS_PMICFILTR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_PMICNTR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_PMIAR_EL1, CGT_MDCR_TPM), + SR_TRAP(SYS_PMECR_EL1, CGT_MDCR_TPM), + SR_TRAP(SYS_PMZR_EL0, CGT_MDCR_TPM), + SR_TRAP(SYS_CPACR_EL1, CGT_CPTR_TCPAC), SR_TRAP(SYS_AMUSERENR_EL0, CGT_CPTR_TAM), SR_TRAP(SYS_AMCFGR_EL0, CGT_CPTR_TAM), --=20 2.25.1