From nobody Thu Nov 28 15:37:52 2024 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2EFF1D04A4 for ; Tue, 1 Oct 2024 16:08:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727798889; cv=none; b=nR+099bXQYI9RudUQ1Y1++9FghlnMSYVYg4fR7QJ4aazHrXHuDB0UrBWONy8aqHhSZjVIINMTL6zEyX4opXiDHT6Fg2hQWCVH0hqUs6MABhKQoH7po6Bfv5kpo4FbofHGn9rv3BVHtK91p1HXBj46DeEYFURu6/AxAfyGKDBOz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727798889; c=relaxed/simple; bh=qI5Qq0dTMkIfgm+jx9/Mexvqh85pdkFunA6cb0VuDdo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HMKPwfoT72/aXuqfA40o27RCbZ4UKZ95i7XT46/Gv4LNxA+vIUKex16VQEB2WzgIXizUXRFsgWXvpbvNcv4+C5x9tOSH8Y42FewyQORalR5D2OCiYcT7kd13EckksLcr13QYFt+z5uly+8wMRkXE2bXLMFUeWmm08tT5zaFuKQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=2qP6ep9T; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="2qP6ep9T" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-20bb610be6aso8628565ad.1 for ; Tue, 01 Oct 2024 09:08:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1727798887; x=1728403687; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WrqzwiSz6htfj/EZwiH/KuGtkUyrK9yji0Ttd1ipzTM=; b=2qP6ep9Tbxiq71SKUZA2GtFoU6+Wzdk1CQfl+PkaLGaoSoebLE80l8nNEI2h37K9rr DqlFOTG5lXrJ59AgafUS13K75XiB9aWyGvjR1z/B5GpAmg61no/2cBcbwx+MEiZHmZpb ZKIKIB8B5wCE7okpsMnurTg26Hrnba6ynYJKLnA8IcTpyotha1Mtywp/NZL45glGhYA0 ETXesNQ8qUhsvaIdddd7s6fIpvpOuMl12Ze/J+9RVetLetmKvZN4zLGQOYpCufgGL1u0 MxrsrD5o8JoFpgnadFZLlJ0xNHIhhFh+xw3E2zkJi1qB/HfK1z2/5GzOxlKMcxqskS05 tPWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727798887; x=1728403687; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WrqzwiSz6htfj/EZwiH/KuGtkUyrK9yji0Ttd1ipzTM=; b=UaZkv1dot5FrYV/hhtIAuvNlQ0g06nuwjIXQIOH/INEHfj21Gc96x54a8m9E59jLGP XHGcjdRnP4kArY/wWXJoZv+KFkwhMCWG1SBibXmqqOjjf2elxYGNHo3Q2mZu6mzXBVh3 VmG/HBkuWxYb95L4F7owKN3EHqC+SCHqSrZAZqErZoyoNSEcwTKuixgoJreto5N3GmIa b0tGqRZ3mkvflnBzahSYjoGfdN2p/ZW7A21qcw6f8wTBjm4XJq/nkaoss+SFp6sq+ISy IVHGPHWcza6qE/06IwK7YXAG5nUYuDbdvaPNhMec49wqiUC770+WmEo+8LOzzsutb2T3 MKuQ== X-Gm-Message-State: AOJu0YxO5YthNMVDqAkNiRmj6wlprpMA2siYIUQn76R8z/oOuhKPsTFJ SU3nuUHIZwyelZgi6tue+qUqxAiqQBObpD68SCPWiE49BFMEhw07HrBJoSFDY0o= X-Google-Smtp-Source: AGHT+IHlpxV7uaOIVvjbu70DzDa5TSukvyO8oURavL8zubeHFYwJVNM/zX5lCBEo7prSC6bDzujUyA== X-Received: by 2002:a17:90b:3543:b0:2d8:8175:38c9 with SMTP id 98e67ed59e1d1-2e184804fc6mr236572a91.20.1727798886907; Tue, 01 Oct 2024 09:08:06 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e06e1d7d47sm13843973a91.28.2024.10.01.09.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 09:08:06 -0700 (PDT) From: Deepak Gupta Date: Tue, 01 Oct 2024 09:06:30 -0700 Subject: [PATCH 25/33] riscv/ptrace: riscv cfi status and state via ptrace and in core files Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-v5_user_cfi_series-v1-25-3ba65b6e550f@rivosinc.com> References: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> In-Reply-To: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling or disabling of feature is not allowed via ptrace set interface. However setting `elp` state or setting shadow stack pointer are allowed via ptrace set interface. It is expected `gdb` might have use to fixup `elp` state or `shadow stack` pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/ptrace.h | 18 ++++++++ arch/riscv/kernel/ptrace.c | 83 ++++++++++++++++++++++++++++++++= ++++ include/uapi/linux/elf.h | 1 + 3 files changed, 102 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi= /asm/ptrace.h index 659ea3af5680..e6571fba8a8a 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -131,6 +131,24 @@ struct __sc_riscv_cfi_state { unsigned long ss_ptr; /* shadow stack pointer */ }; =20 +struct __cfi_status { + /* indirect branch tracking state */ + __u64 lp_en : 1; + __u64 lp_lock : 1; + __u64 elp_state : 1; + + /* shadow stack status */ + __u64 shstk_en : 1; + __u64 shstk_lock : 1; + + __u64 rsvd : sizeof(__u64) - 5; +}; + +struct user_cfi_state { + struct __cfi_status cfi_status; + __u64 shstk_ptr; +}; + #endif /* __ASSEMBLY__ */ =20 #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 92731ff8c79a..c69b20ea6e79 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 enum riscv_regset { REGSET_X, @@ -28,6 +29,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_V REGSET_V, #endif +#ifdef CONFIG_RISCV_USER_CFI + REGSET_CFI, +#endif }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -152,6 +156,75 @@ static int riscv_vr_set(struct task_struct *target, } #endif =20 +#ifdef CONFIG_RISCV_USER_CFI +static int riscv_cfi_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs =3D task_pt_regs(target); + + user_cfi.cfi_status.lp_en =3D is_indir_lp_enabled(target); + user_cfi.cfi_status.lp_lock =3D is_indir_lp_locked(target); + user_cfi.cfi_status.elp_state =3D (regs->status & SR_ELP); + + user_cfi.cfi_status.shstk_en =3D is_shstk_enabled(target); + user_cfi.cfi_status.shstk_lock =3D is_shstk_locked(target); + user_cfi.shstk_ptr =3D get_active_shstk(target); + + return membuf_write(&to, &user_cfi, sizeof(user_cfi)); +} + +/* + * Does it make sense to allowing enable / disable of cfi via ptrace? + * Not allowing enable / disable / locking control via ptrace for now. + * Setting shadow stack pointer is allowed. GDB might use it to unwind or + * some other fixup. Similarly gdb might want to suppress elp and may want + * to reset elp state. + */ +static int riscv_cfi_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs =3D task_pt_regs(target); + + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1); + if (ret) + return ret; + + /* + * Not allowing enabling or locking shadow stack or landing pad + * There is no disabling of shadow stack or landing pad via ptrace + * rsvd field should be set to zero so that if those fields are needed in= future + */ + if (user_cfi.cfi_status.lp_en || user_cfi.cfi_status.lp_lock || + user_cfi.cfi_status.shstk_en || user_cfi.cfi_status.shstk_lock || + !user_cfi.cfi_status.rsvd) + return -EINVAL; + + /* If lpad is enabled on target and ptrace requests to set / clear elp, d= o that */ + if (is_indir_lp_enabled(target)) { + if (user_cfi.cfi_status.elp_state) /* set elp state */ + regs->status |=3D SR_ELP; + else + regs->status &=3D ~SR_ELP; /* clear elp state */ + } + + /* If shadow stack enabled on target, set new shadow stack pointer */ + if (is_shstk_enabled(target)) + set_active_shstk(target, user_cfi.shstk_ptr); + + return 0; +} +#endif + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -182,6 +255,16 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D riscv_vr_set, }, #endif +#ifdef CONFIG_RISCV_USER_CFI + [REGSET_CFI] =3D { + .core_note_type =3D NT_RISCV_USER_CFI, + .align =3D sizeof(__u64), + .n =3D sizeof(struct user_cfi_state) / sizeof(__u64), + .size =3D sizeof(__u64), + .regset_get =3D riscv_cfi_get, + .set =3D riscv_cfi_set, + } +#endif }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b9935988da5c..7ef63b2b67a1 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -450,6 +450,7 @@ typedef struct elf64_shdr { #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ +#define NT_RISCV_USER_CFI 0x902 /* RISC-V shadow stack state */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension regist= ers */ --=20 2.45.0