From nobody Thu Nov 28 13:45:34 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735C81C8FDC; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; cv=none; b=kMhx2GcxG/evcNMWv0pF+81vAS6yiyV/z2hpRqaY0fcvqxnTD6yQ2A0z8c1VdhJ3qTHEvfiQK9JMTSqW4TASGFVRiC0AjA0evXSoKQNMqrxiIZ/yiAlohGWHY4Val0bv3L5F6+g+u7B14bhiQHNn1/6/bp40gz/xBGdXSvk3TRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727793568; c=relaxed/simple; bh=xRKZsSbMkPuauoeApBaSWMeBF9J6EJER1zS21DadUP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PoLE0fgD5EMgKkFrE15C9YM3A2bTcjTi3yQ7QQYXeKNdctoxuewxlpq7zptmiwqHE80lWrRqmPlATDkcOVVPLKQovzxvQ+JhEiUOJmi2hQzoSAoflcmQJU7Xl8hL4g3lKd41rSThq/wHLDZtshIxZU5NfzjslDM8e+Rj+BakQ6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RJ72vvmI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RJ72vvmI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3490AC4CEDF; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727793568; bh=xRKZsSbMkPuauoeApBaSWMeBF9J6EJER1zS21DadUP4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RJ72vvmICkgm/iCJqcz4yJZe1xvk9zmDXSsqc2GvvZxlYceAZnP1xSbl+6QYlMJ30 iSpFcs8+bjT1rEYVtGOEVS1eMNXU3U7XoOOmm8xDS4ZQMzFJ5qYnyWYHXyu/AvOrE0 ATZoGKES/5lubBobdgsIL8qrV412HQxw+tPO/mzPwuby3ir9SmkFznNnPAXW+4vnV4 /uRdVBVPC+1KgDXMdsqd7jquy8ttBu6lTEcK8z8mOvV4bXotHG4hivocwssPQUIuKw WGiAmGpOvJy7nOL6XOkcOsLY4E2efD/b/sfdkyq1VnE308j/DnBXR8gv7xhPDu3R2L 8GJUQwthdO4Ow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF26CEACCE; Tue, 1 Oct 2024 14:39:28 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 01 Oct 2024 16:37:34 +0200 Subject: [PATCH v13 04/12] dt-bindings: clock: Add Marvell PXA1908 clock bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241001-pxa1908-lkml-v13-4-6b9a7f64f9ae@skole.hr> References: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> In-Reply-To: <20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Rob Herring , Krzysztof Kozlowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5085; i=duje.mihanovic@skole.hr; s=20240706; h=from:subject:message-id; bh=+wiZmG7RML75ebWcpNqefQgETbMc7ztfxKlJgaoEc7E=; b=owGbwMvMwCW21nBykGv/WmbG02pJDGl/OCdt89Jg7gy0TfeRuyUQ9U7Tt9GJ/VWT1KSy8/Etl j43lRo6SlkYxLgYZMUUWXL/O17j/SyydXv2MgOYOaxMIEMYuDgFYCLXdjMyHLlSfXJ2eEh6ZIRm 1OPC8Lei825ydTCkPz/9oJQlt2qZBCPD5BUTa19WmnjxnW5IWfNvTvdKY9acS3qTtVu268yJ2P6 PFwA= X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=6DFF41D60DF314B5B76BA630AD319352458FAD03 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/20240706 with auth_id=191 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanovi=C4=87 Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Duje Mihanovi=C4=87 --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++= ++++ 2 files changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 0000000000000000000000000000000000000000..4e78933232b6b925811425f853b= edf6e9f01a27d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanovi=C4=87 + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, = MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible =3D "marvell,pxa1908-apmu"; + reg =3D <0xd4282800 0x400>; + #clock-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindi= ngs/clock/marvell,pxa1908.h new file mode 100644 index 0000000000000000000000000000000000000000..fb15b0d0cd4c1cd5760a78ea16a= 1980cd305ea21 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif --=20 2.46.2